CN102314034A - Active element, pixel structure, drive circuit and display panel - Google Patents

Abstract

The invention provides an active element, a pixel structure, a driving circuit and a display panel. The pixel structure comprises a scanning line, a data line, an active element, a first insulating layer, a pixel electrode, a capacitor electrode and a second insulating layer. The active element comprises a grid, a channel, a source and a drain, wherein the scanning line is electrically connected with the grid, and the source is electrically connected with the data line. The first insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected with the drain electrode. The capacitor electrode is located on the first insulating layer. The second insulating layer covers the first insulating layer and the capacitor electrode and is located between the capacitor electrode and the drain electrode.

Description

Active element, pixel structure, driving circuit and display panel

technical field

The invention relates to an active element, a pixel structure, a driving circuit and a display panel with the active element.

Background technique

Generally speaking, a pixel structure of a liquid crystal display includes an active element and a pixel electrode. The active element is used as the switching element of the liquid crystal display unit. In order to control individual pixel structures, a specific pixel is usually selected through corresponding scan lines and data lines, and display data corresponding to the pixel is displayed by providing an appropriate operating voltage. In addition, the pixel structure also includes a storage capacitor (storage capacitor), so that the pixel structure has a voltage holding function. That is, the storage capacitor can store the above-mentioned applied operating voltage to maintain the stability of the display picture of the pixel structure.

In order to provide a storage capacitor in the pixel structure, it is generally necessary to form a capacitor electrode in the pixel structure. However, if the area of the capacitor electrode is increased in order to increase the capacitance of the storage capacitor, the aperture ratio of the pixel structure will be reduced.

At present, there is a pixel structure in which capacitive electrodes are designed under the data lines to increase the aperture ratio of the pixel structure. However, since the overlapping of the capacitive electrode and the data line will increase the loading of the pixel structure, such a pixel structure will increase the power required for driving the display panel and consume more power.

Contents of the invention

The invention provides an active element, a pixel structure with the active element, a driving circuit and a display panel. The design of the capacitive electrode can make the pixel structure have a high aperture ratio without increasing the load of the pixel structure.

The present invention proposes a pixel structure, which includes a scan line, a data line, a first active element, a first insulating layer, a pixel electrode, a capacitor electrode and a second insulating layer. The first active element includes a first gate, a first channel, a first source and a first drain, wherein the scan line is electrically connected to the gate, and the source is electrically connected to the data line. The first insulating layer is located between the first gate and the first channel. The pixel electrode is electrically connected with the first drain. The capacitor electrodes are located on the first insulating layer. The second insulating layer covers the first insulating layer and the capacitor electrode, and the second insulating layer is located between the capacitor electrode and the first drain.

The present invention proposes a display panel, which has a display area and a non-display area, and the display area and the non-display area do not overlap with each other. The display panel includes a plurality of pixel structures as described above and at least one driving circuit. The pixel structure is located in the display area. The driving circuit is located in the non-display area, wherein the driving circuit includes at least one second active element, which includes a second gate, a second channel, a second source and a second drain. The second gate is located on the first insulating layer, and the second insulating layer covers the second gate. The second channel is located on the first insulating layer above the second gate. The second source and the second drain are located on the second channel.

The present invention proposes a driving circuit, comprising a first gate; a first insulating layer covering the first gate; a second gate located on the second insulating layer; a second insulating layer covering the first insulating layer and the second insulating layer. gate; first channel, disposed on the second insulating layer above the first gate; second channel, disposed on the second insulating layer above the second gate; first source and second drain , located on the first channel; and a second source and a second drain, located on the second channel.

The invention provides an active element, which includes a gate, a channel, a first insulating layer, a source, a drain, a capacitor electrode and a second insulating layer. The first insulating layer is located between the gate and the channel. A source and a drain are located above the channel. The capacitor electrodes are located on the first insulating layer. The second insulating layer covers the first insulating layer and the capacitor electrode, and is located between the capacitor electrode and the drain.

Based on the above, since the capacitor electrode of the present invention is located on the first insulating layer, and the second insulating layer is located between the capacitor electrode and the drain, the capacitor electrode and the drain form a capacitor. Since a thinner insulating layer can be used between the capacitor electrode and the drain electrode, the arrangement of the capacitor electrode can reduce the area occupied by the light-transmitting region of the pixel structure, thereby enabling the pixel structure to have a high aperture ratio. In addition, because the capacitive coupling portion of the capacitive electrode of the present invention is not overlapped with the data line, the design of the capacitive electrode will not increase the load of the pixel structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a schematic top view of a pixel structure according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view of Fig. 1A along the section line A-A'.

FIG. 2A is a schematic top view of a pixel structure according to an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view of Fig. 2A along the section line A-A'.

FIG. 3A is a schematic top view of a pixel structure according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view of Fig. 3A along the section line A-A'.

FIG. 4 is a schematic top view of a pixel structure according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

FIG. 7 is a schematic top view of a display panel according to another embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of a pixel structure and a driving circuit in the display panel of FIG. 7 .

FIG. 9 is a schematic cross-sectional view of a pixel structure and a driving circuit in a display panel according to another embodiment.

FIG. 10 is a schematic diagram of a driving circuit according to an embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of some active components and capacitors in the driving circuit of FIG. 10 .

FIG. 12 is a schematic cross-sectional view of some active elements and capacitors in a driving circuit according to another embodiment.

Explanation of reference signs

100, 200: substrate 102, 104: insulating layer

106, 170, 212: passivation layer 110a, 110a': connecting part

110b, 110b': capacitive coupling part 150, 160: pad

160a: Lower electrode 160b: Upper pad

202: polysilicon layer 202c: channel region

202s: source region 202d: drain region

204: The first insulating layer 206: Gate

208: auxiliary dielectric layer 210: second insulating layer

400: Display panel 402: Display area

404: Non-display area SL, SL’: scan line

DL, DL'; data lines CL, CL': capacitor electrodes

U, U’: Pixel area A: Alignment pattern

G, G’, G1, G2: Gate

CH, CH', CH1, CH2: channels

OM, OM1, OM2: Ohmic contact layer

S, S', SM, S1, S2: source

D, D’, DM, D1, D2: Drain

PE, PE', 214: pixel electrodes

V, V', V1～V3: contact window opening

DR: drive circuit T, T’, T1, T2: active components

C1, C2: capacitor Eb: lower electrode

Et: upper electrode E1: first electrode

E2: the second electrode E3: the third electrode

Gn, Gn-1, Gn+1: scan line Vss: data line

CK: Time Signal Line H, L, XCK: Signal Line

M1～M7: active components

Detailed ways

first embodiment

FIG. 1A is a schematic top view of a pixel structure according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view of Fig. 1A along the section line A-A'. Please refer to FIG. 1A and FIG. 1B at the same time. The pixel structure of this embodiment includes a scan line SL, a data line DL, an active element T, a first insulating layer 102, a pixel electrode PE, a capacitor electrode CL, and a second electrode arranged on a substrate 100. Two insulating layers 104 .

The substrate 100 has a pixel area U, and one pixel structure is disposed in one pixel area U. The material of the substrate 100 can be glass, quartz, organic polymer, or opaque/reflective material (eg, conductive material, chip, ceramic, or other applicable materials), or other applicable materials. The scan lines SL and the data lines DL are disposed on the substrate 100 .

The scan lines SL and the data lines DL are arranged to cross over each other. In other words, the extending direction of the data lines DL is not parallel to the extending direction of the scanning lines SL. Preferably, the extending direction of the data lines DL is perpendicular to the extending direction of the scanning lines SL. In addition, the scan lines SL and the data lines DL belong to different film layers, and the first insulating layer 102 and the second insulating layer 104 are sandwiched between the data lines DL and the scan lines SL. Based on the consideration of conductivity, the scan lines SL and the data lines DL are generally made of metal materials. However, the present invention is not limited thereto, and according to other embodiments, the scan lines SL and the data lines DL may also use other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials), or stacked layers of metal materials and other conductive materials.

The active element T includes a gate G, a channel CH, a source S and a drain D. As shown in FIG. The gate G is electrically connected to the scan line SL, and the source S is electrically connected to the data line DL. According to this embodiment, the gate G is disposed on the substrate 100 , and the gate G and the scan line SL belong to the same film layer, and the material of the gate G is the same or similar to that of the scan line SL. The channel CH is located on the second insulating layer 104 above the gate G. As shown in FIG. The material of the channel CH is, for example, amorphous silicon, polysilicon, metal oxide semiconductor or other semiconductor materials. The source S and the drain D are arranged on both sides of the channel CH. In this embodiment, the source S and the drain D belong to the same layer as the data line DL, in other words, they are formed by patterning the same layer, and the material of the source S and the drain D is the same as that of the data line. DL of the same or similar material. In an embodiment, if the channel CH is made of amorphous silicon, there may be an ohmic contact layer OM between the channel CH and the source S and the drain D, and the material thereof may be doped amorphous silicon.

The capacitive electrode CL is generally located above the gate G and below the drain D. As shown in FIG. In other words, the film layer of the capacitor electrode CL is located between the film layer of the gate G and the film layer of the drain D. According to this embodiment, the capacitive electrode CL includes a connecting portion 110a and a capacitive coupling portion 110b. Where the capacitive coupling portion 110b overlaps the drain D is a storage capacitor constituting the pixel structure. In other words, the capacitive coupling part 110b serves as the lower electrode of the storage capacitor, and the drain D serves as the upper electrode of the storage capacitor. In addition, the connection part 110a is connected to the capacitive coupling part 110b, and the connection part 110a extends to the periphery of the substrate 110 to be electrically connected to the common voltage (Vcom). Similarly, based on the consideration of conductivity, the capacitive electrode CL is generally made of metal material. However, the present invention is not limited thereto, and according to other embodiments, the capacitive electrodes CL may also use other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials), or stacked layers of metal materials and other conductive materials.

According to this embodiment, the extending direction of the connecting portion 110 a of the capacitive electrode CL is parallel to the extending direction of the scanning line SL. The extending direction of the capacitive coupling portion 110b of the capacitive electrode CL is perpendicular to the connecting portion 110a. In this embodiment, for each pixel structure, the capacitive coupling part 110b extends from the connecting part 110a to the position where the scan line SL is located. Furthermore, according to the present embodiment, the capacitive electrode CL overlaps part of the gate G. More specifically, the capacitive coupling portion 110 b of the capacitive electrode CL is partially overlapped with the gate G. In addition, the connecting portion 110 a of the capacitor electrode CL partially overlaps with the data line DL.

In this embodiment, a pad layer 150 may be further provided at the overlapping portion of the data line DL and the capacitor electrode CL. The pad layer 150 is, for example, composed of a channel material layer (not marked) and an ohmic contact material layer (not marked) (for example, the channel material layer 160a and the ohmic contact material layer 160b of the pad layer 160 in FIG. 2B are formed. The way). The channel material layer is defined simultaneously when the channel CH is formed, and the ohmic contact material layer is defined simultaneously when the ohmic contact layer OM is formed. Disposing the pad layer 150 between the data line DL and the capacitor electrode CL can reduce the generation of electric leakage where the two overlap. However, the present invention does not limit the material of the cushion layer 150 . According to other embodiments, the cushion layer 150 may also use other materials.

In this embodiment, as shown in FIG. 1B , a first insulating layer 102 and a second insulating layer 104 are sandwiched between the gate G and the channel CH, and the first insulating layer 104 located between the gate G and the channel CH The insulating layer 102 and the second insulating layer 104 serve as a gate insulating layer of the active device T. Referring to FIG. In addition, a second insulating layer 104 is sandwiched between the capacitive electrode CL (capacitive coupling part 110b) and the drain D, and the second insulating layer 104 located between the capacitive electrode CL (capacitive coupling part 110b) and the drain D acts as a capacitor dielectric layer. Materials of the first and second insulating layers 102 and 104 respectively include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In particular, the thickness of the second insulating layer 104 is smaller than the thickness of the first insulating layer 102 . Here, the thickness of the second insulating layer 104 (capacitor dielectric layer) is, for example, about 700˜1500 angstroms, and the total (gate insulating layer) thickness of the first insulating layer 102 and the second insulating layer 104 is, for example, about 3300 angstroms. ~5100 Angstroms.

The pixel electrode PE is electrically connected to the drain D of the active element T. As shown in FIG. The pixel electrode PE can be a transparent pixel electrode, a reflective pixel electrode or a combination of the transparent pixel electrode and the reflective pixel electrode. The material of the transparent pixel electrode may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides, or A stacked layer of at least two of the above. The material of the reflective pixel electrode is, for example, a metal material with high reflectivity.

According to this embodiment, the connection portion 110 a of the above-mentioned capacitor electrode CL partially overlaps with the pixel electrode PE. In addition, the pixel electrode PE shown in this embodiment further includes a plurality of alignment patterns A, such as alignment slits. However, the present invention is not limited thereto. According to other embodiments, the pixel electrode PE may not be provided with the alignment pattern A.

In addition, in this embodiment, as shown in FIG. 1B , passivation layers 106 and 170 are further provided between the pixel electrode PE and the active element T (source S and drain D). The passivation layer 106, 170 has a contact opening V for electrically connecting the pixel electrode PE and the drain D. The passivation layer 106 can also be generally called a protection layer, and its material can be silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. The passivation layer 170 can be called a flat layer, and its material is, for example, an inorganic insulating material, an organic insulating material, or an organic photosensitive material.

It is worth mentioning that, in the pixel structure shown in FIG. 1A , the data line DL is disposed at the edge of the pixel region U, and the scan line SL, the active element T and the capacitor electrode CL are disposed in the middle of the pixel region U. However, the present invention does not limit the positions of the data lines DL, scan lines SL, active elements T and capacitor electrodes CL in the pixel region U.

According to an embodiment of the present invention, a pad layer 150 may be provided where the data line DL overlaps with the capacitor electrode CL. The pad layer 150 may be defined while forming the channel CH and the ohmic contact layer OM. The purpose of disposing the pad layer 150 is to avoid short circuit or electric leakage between the data line DL and the capacitor electrode CL.

In addition, in the pixel structure shown in FIG. 1A and FIG. 1B , for example, the capacitive coupling part 110 b of the capacitive electrode CL overlaps with the channel CH or/and the gate G also partially overlaps. Since the capacitive coupling portion 110b of the capacitive electrode CL is overlapped with the channel CH, the channel CH can reduce short circuit or leakage between the capacitive coupling portion 110b of the capacitive electrode CL and the drain D.

According to other embodiments, the capacitor electrode may not overlap with the gate, as shown in FIG. 2A and FIG. 2B . FIG. 2A is a schematic top view of a pixel structure according to an embodiment of the present invention, and FIG. 2B is a schematic cross-sectional view of FIG. 2A along the section line A-A'.

Please refer to FIG. 2A and FIG. 2B, the embodiment of 2A and FIG. 2B is similar to the embodiment of FIG. 1A and FIG. Repeat. The embodiment of FIG. 2A and FIG. 2B is different from the embodiment of FIG. 1A and FIG. 1B in that the capacitor electrode CL is not overlapped with the gate G/channel CH. More specifically, the capacitive coupling part 110b of the capacitive electrode CL is not overlapped with the gate G/channel CH.

In addition, since the capacitive coupling portion 110b of the capacitive electrode CL is not overlapped with the gate G/channel CH, a pad layer 160 may be further provided at the overlapping portion of the drain D and the capacitive electrode CL. The cushion layer 160 includes a lower cushion layer 160a and an upper cushion layer 160b. The material of the lower pad layer 160a is, for example, the same as that of the channel CH, and the material of the upper pad layer 160b is, for example, the same as that of the ohmic contact layer OM. Disposing the pad layer 160 at the overlapping portion of the drain D and the capacitor electrode CL can prevent leakage or short circuit between the drain D and the capacitor electrode CL.

In the above embodiment, the capacitive electrode CL is located between the gate G and the drain D, and where the capacitive coupling portion 110 b of the capacitive electrode CL overlaps the drain D is a storage capacitor constituting the pixel structure. Since the gate G and the drain D of the active element T are located in the non-light-transmitting area originally. Therefore, compared with the design method of the capacitance electrode of the traditional storage capacitor, the design method of the capacitance electrode CL of the present invention can make the pixel structure have a higher aperture ratio. In addition, in the present invention, setting the capacitive electrode CL between the gate G and the drain D can further reduce the parasitic capacitance (Cgd) between the gate and the drain D, thereby reducing the coupling between the gate and the drain. , to improve picture quality, such as reducing flicker.

In addition, in this embodiment, the thickness of the second insulating layer 104 (capacitor dielectric layer) is only 700-1500 angstroms, which is much lower than that of the first insulating layer 102 and the second insulating layer 104 (gate insulating layer). Added thickness. Since the thickness of the second insulating layer 104 (capacitor dielectric layer) is sufficiently thin, even if the area of the capacitor electrode is reduced in order to increase the aperture ratio of the pixel structure, the storage capacitor can still have sufficient storage capacitance.

In addition, since the capacitor electrode CL is located between the gate G and the drain D, and covers part of the gate G. Therefore, the capacitive electrode CL can also block light from the back of the substrate 100 (such as light from a backlight module), so as to reduce the light leakage current effect caused by the backlight to the channel CH.

In the above two embodiments, the capacitive coupling portion 110 b of the capacitive electrode CL is disposed close to the active element T. As shown in FIG. However, the present invention is not limited thereto. According to other embodiments, the capacitive coupling portion 110b of the capacitive electrode CL may also be disposed away from the active element T, as shown in FIG. 3A and FIG. 3B .

FIG. 3A is a schematic top view of a pixel structure according to an embodiment of the present invention, and FIG. 3B is a schematic cross-sectional view of FIG. 3A along the section line A-A'. Please refer to FIG. 3A and FIG. 3B, the embodiment of 3A and FIG. 3B is similar to the embodiment of FIG. 3A and FIG. Repeat. The difference between the embodiment of FIG. 3A and FIG. 3B and the embodiment of FIG. 2A and FIG. 2B is that the active element T is disposed on the edge of the pixel region U, and the capacitive electrode CL is disposed in the middle of the pixel region U. Therefore, the capacitive electrode CL is not disposed close to the active element T. As shown in FIG.

In addition, in this embodiment, since the capacitive coupling portion 110b of the capacitive electrode CL does not overlap with the gate G/channel CH, a pad layer 160 can be further provided at the overlap between the drain D and the capacitive electrode CL. The cushion layer 160 includes a lower cushion layer 160a and an upper cushion layer 160b. The material of the lower pad layer 160a is, for example, the same as that of the channel CH, and the material of the upper pad layer 160b is, for example, the same as that of the ohmic contact layer OM. Disposing the pad layer 160 at the overlapping portion of the drain D and the capacitor electrode CL can prevent leakage or short circuit between the drain D and the capacitor electrode CL.

In addition to the above-mentioned several types of pixel structures, the present invention can also be applied to other types of pixel structures by disposing the capacitive electrode CL between the gate G and the drain D, as shown in FIG. 4 . The pixel structure in FIG. 4 is similar to the pixel structure in FIG. 1 , the main difference is that the pixel structure in FIG. 4 is a horizontally arranged pixel structure, and the scanning line is across the middle of the pixel area. Therefore, in the pixel structure of FIG. 4, the same elements as those of FIG. 1 are denoted by similar symbols.

Referring to FIG. 4, the pixel structure of this embodiment is disposed in the pixel area U', and the pixel structure includes a scan line SL', a data line DL', an active element T', a pixel electrode PE' and a capacitor electrode CL'.

The scan line SL' and the data line DL' are arranged to cross over each other. In other words, the extending direction of the data line DL' is not parallel to the extending direction of the scanning line SL', preferably, the extending direction of the data line DL' is perpendicular to the extending direction of the scanning line SL'. The material of the scan line SL' and the data line DL' may be the same as or similar to that of the scan line SL and the data line DL in FIG. 1 .

The active element T' includes a gate G', a channel CH', a source S' and a drain D'. The gate G' is electrically connected to the scan line SL', and the source S' is electrically connected to the data line DL'. Similarly, the materials of the gate G', the channel CH', the source S' and the drain D' can be the same or similar to those of the gate G, the channel CH, the source S and the drain D described in FIG. 1 .

The capacitor electrode CL' is located between the gate G' and the drain D'. According to this embodiment, the capacitive electrode CL' includes a connection part 110a' and a capacitive coupling part 110b'. Where the capacitive coupling portion 110b' overlaps the drain D' is a storage capacitor that constitutes the pixel structure. In other words, the capacitive coupling portion 110b' serves as the lower electrode of the storage capacitor, and the drain D' serves as the upper electrode of the storage capacitor. The connection part 110a' is connected to the capacitive coupling part 110b', and the connection part 110a' is electrically connected to the common voltage (Vcom). The material of the capacitive electrode CL' may be the same as or similar to that of the capacitive electrode CL of FIG. 1 described above.

Similarly, the extending direction of the connecting portion 110a' of the capacitive electrode CL' is parallel to the extending direction of the scanning line SL'. The extending direction of the capacitive coupling part 110b' of the capacitive electrode CL' is perpendicular to the connection part 110a'. In this embodiment, for each pixel structure, the capacitive coupling part 110b' extends from the connecting part 110a' to the position where the scan line SL' is located. In addition, according to this embodiment, the capacitor electrode CL' partially overlaps the gate G'. In more detail, the capacitive coupling portion 110b' of the capacitive electrode CL' is partially overlapped with the gate G'. In addition, the connecting portion 110a' of the capacitive electrode CL' partially overlaps with the data line DL'.

In this embodiment, a pad layer 150' may be further provided at the overlapping portion of the data line DL' and the capacitor electrode CL'. The pad layer 150' is composed of, for example, a channel material layer (not shown) and an ohmic contact material layer (not shown). Disposing the pad layer 150' between the data line DL' and the capacitor electrode CL' can reduce the generation of electric leakage where the two overlap.

The pixel electrode PE' is electrically connected to the drain D' of the active element T'. The pixel electrode PE' can be a transparent pixel electrode, a reflective pixel electrode, or a combination of a transparent pixel electrode and a reflective pixel electrode.

Similarly, in the pixel structure in FIG. 4 , a first insulating layer and a second insulating layer are further provided between the gate G' and the channel CH'. A second insulating layer is further included between the capacitive electrode CL' (capacitive coupling portion 110b') and the drain D'. The thickness of the second insulating layer is, for example, about 700-1500 angstroms, and the total thickness of the first insulating layer and the second insulating layer is, for example, about 3300-5100 angstroms. A passivation layer is also provided between the pixel electrode PE' and the active element T' (source S' and drain D'). The passivation layer has a contact window opening V' for electrically connecting the pixel electrode PE' and the drain electrode D'.

In the embodiment of FIG. 4, the capacitive electrode CL' is located between the gate G' and the drain D', and the capacitive coupling part 110b' of the capacitive electrode CL' overlaps the drain D' to constitute the pixel structure storage capacitor. Since the gate G' and the drain D' of the active element T' are originally located in the non-light-transmitting region. Therefore, compared with the design method of the capacitance electrode of the traditional storage capacitor, the design method of the capacitance electrode CL' of this embodiment can make the pixel structure have a higher aperture ratio. In addition, in the present invention, setting the capacitive electrode CL' between the gate G' and the drain D' can further reduce the parasitic capacitance (Cgd) between the gate G' and the drain D', thereby reducing the gate-to-drain Extreme coupling (coupling) improves picture quality, such as reducing flicker (flicker) phenomenon.

In addition, in this embodiment, since the thickness of the second insulating layer is sufficiently thin, even if the area of the capacitor electrode CL' is reduced in order to increase the aperture ratio of the pixel structure, the storage capacitor can still have sufficient storage capacitance. In addition, since the capacitor electrode CL' is located between the gate G' and the drain D', and covers part of the gate G'. Therefore, the capacitive electrode CL' can also block the light from the backlight module, so as to reduce the light leakage current effect caused by the backlight to the channel CH'.

In the pixel structures of the above-mentioned several embodiments, the active elements thereof are described by taking the bottom gate thin film transistor as an example. However, the present invention is not limited thereto. According to other embodiments, the pixel structure of the present invention may also use a top-gate thin film transistor, as described below.

FIG. 5 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention. Referring to FIG. 5, the active elements of the pixel structure include a polysilicon layer 202, a gate 206, a first insulating layer 204, an auxiliary dielectric layer 208, a second insulating layer 210, a source SM and a drain disposed on a substrate 200. The electrode DM, the capacitor electrode 220 and the pixel electrode 214, wherein the polysilicon layer 202, the gate 206, the source SM and the drain DM constitute active elements.

The polysilicon layer 202 has a source region 202s, a drain region 202d and a channel region 202c. The source region 202s and the drain region 202d are, for example, doped with N-type ions or doped with P-type ions.

The first insulating layer 204 covers the polysilicon layer 202 and the substrate 200 . The material of the first insulating layer 204 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

The gate 206 is disposed on the first insulating layer 204 above the channel region 202c. The gate 206 is electrically connected to the scan line (not shown), and the material of the gate 206 is, for example, metal, alloy, nitride of metal material, oxide of metal material, oxynitride of metal material, or other suitable materials. materials, or stacked layers of metal materials and other conductive materials.

The auxiliary dielectric layer 208 covers the gate 206 and the first insulating layer 204 . The material of the auxiliary dielectric layer 208 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

The capacitor electrode 220 is disposed on the auxiliary dielectric layer 208 . The material of the capacitor electrode 220 is, for example, metal, alloy, nitride of metal material, oxide of metal material, oxynitride of metal material, or other suitable materials, or stacked layers of metal material and other conductive materials.

The second insulating layer 210 covers the capacitor electrode 220 . The material of the second insulating layer 210 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

The source SM and the drain DM are disposed on the second insulating layer 210 . The source SM is electrically connected to the data line (not shown). The material of the source electrode SM and the drain electrode DM is, for example, a metal, an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or other suitable materials, or a stack of a metal material and other conductive materials. layer. In addition, the source SM and the drain DM are electrically connected to the source region 202 s and the drain region 202 d through the contact openings V1 and V2 respectively. In other words, the contact openings V1, V2 penetrate through the second insulating layer 210, the auxiliary dielectric layer 208 and the first insulating layer 204, so that the source SM and the drain DM can communicate with each other through the contact openings V1, V2 respectively. The source region 202s is electrically connected to the drain region 202d.

In particular, the capacitor electrode 220 is located between the gate 206 and the drain DM. Moreover, the overlap between the capacitor electrode 220 and the drain electrode DM is a storage capacitor constituting the pixel structure. In other words, the capacitor electrode 220 serves as the lower electrode of the storage capacitor, and the drain DM serves as the upper electrode of the storage capacitor. Since the capacitor electrode 220 is located between the gate 206 and the drain DM in this embodiment, the gate 206 and the drain DM are originally opaque. Therefore, disposing the capacitive electrode here can reduce the area occupied by the light-transmitting region of the pixel structure. In other words, compared with the design method of the capacitor electrode of the traditional storage capacitor, the design method of the capacitor electrode 220 of this embodiment can make the pixel structure have a higher aperture ratio. In addition, disposing the capacitive electrode 220 between the gate 206 and the drain DM in the present invention can further reduce the parasitic capacitance (Cgd) between the gate 206 and the drain DM, thereby improving picture quality.

In addition, the passivation layer 212 covers the source SM and the drain DM. The material of the passivation layer 212 can be an inorganic insulating material (such as silicon nitride, silicon oxide, silicon oxynitride), an organic insulating material, an organic photosensitive material or other materials.

The pixel electrode 214 is disposed on the passivation layer 212 and is electrically connected to the drain DM through the contact opening V3. In other words, the contact opening V3 penetrates through the passivation layer 212 , so that the pixel electrode 214 is electrically connected to the drain DM through the contact opening V3 .

FIG. 6 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. Referring to FIG. 6 , the display panel includes a first substrate 310 , a pixel array 312 , a second substrate 320 and a display medium 330 . The pixel array 312 is disposed on the first substrate 310, and the pixel array 312 is composed of a plurality of pixel structures, and the pixel structure can be the pixel structure shown in any one of the above-mentioned FIG. 1 to FIG. 5 embodiments. The second substrate 320 can be a simple blank substrate, a color filter substrate or a substrate provided with an electrode layer. The display medium 330 can be liquid crystal molecules, electrophoretic display medium, or other applicable medium.

In summary, in this embodiment, the capacitive electrode is disposed between the gate and the drain, so disposing the capacitive electrode here can reduce the occupied area of the light-transmitting region of the pixel structure. Therefore, compared with the design method of the capacitance electrode of the traditional storage capacitor, the design method of the capacitance electrode of the embodiment can make the pixel structure have a higher aperture ratio.

In addition, in this embodiment, disposing the capacitor electrode between the gate and the drain can further reduce the parasitic capacitance (Cgd) between the gate and the drain, thereby improving the image quality. In addition, since the thickness of the second insulating layer is sufficiently thin, even if the area of the capacitor electrode is reduced in order to increase the aperture ratio of the pixel structure, the storage capacitor can still have sufficient storage capacitance.

Furthermore, since the capacitor electrode is located between the gate and the drain, it covers part of the channel. Therefore, the capacitive electrodes can also block the light from the back of the substrate (for example, the light from the backlight module), so as to reduce the light leakage current effect caused by the backlight to the channel. In addition, because the capacitive coupling portion of the capacitive electrode in this embodiment is not overlapped with the data line, the design of the capacitive electrode will not increase the load of the pixel structure.

second embodiment

FIG. 7 is a schematic top view of a display panel according to another embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a pixel structure and a driving circuit located in a pixel region in the display panel of FIG. 7 . 7 and 8, the display panel 400 of this embodiment has a display area 402 and a non-display area 404, and has a plurality of pixel regions U in the display area 402 of the display panel 400, and in the non-display area 400 of the display panel 400 404 has at least one driving circuit DR. The non-display area 404 substantially surrounds the display area 402 . The driving circuit DR can be located on one side, two sides, three sides or around the display area 402 . In this embodiment, the driving circuit DR is located on both sides of the display area 402 as an example for illustration, but the present invention is not limited thereto.

As mentioned above, the plurality of pixel areas U in the display area 402 are arranged in an array, and each pixel area U is correspondingly provided with a pixel structure. Therefore, there are multiple pixel structures arranged in an array in the display area 402 .

The pixel structure in each pixel area U can be any pixel structure as described in the previous first embodiment. In other words, the pixel structure in each pixel area U can be the pixel structure in FIG. 1A and FIG. 1B , the pixel structure in FIG. 2A and FIG. 2B , the pixel structure in FIG. 3A and FIG. 3B , the pixel structure in FIG. pixel structure. Here, in order to describe the display panel of this embodiment in detail, the pixel structure in each pixel region U is illustrated by taking the pixel structure in FIG. 2A and FIG. 2B as an example, but not limited thereto.

In this embodiment, the pixel structure in each pixel area U includes a first active element T1 and a pixel electrode PE. The first active element T1 includes a first gate G1 , a first channel CH1 , a first source S1 and a first drain D1 . The first gate G1 is electrically connected to the scan line (not shown in FIG. 8 ), and the first source S1 is electrically connected to the data line (not shown in FIG. 8 ). The materials of the above-mentioned first gate G1, first channel CH1, first source S1 and first drain D1 are respectively the same as those of the gate G, channel CH, source S and drain described in the previous first embodiment. The poles D are the same or similar, so the description will not be repeated here. In addition, an ohmic contact layer OM1 may be further provided between the first channel CH1 and the first source S1/first drain D1. In addition, the pixel electrode PE is electrically connected to the first drain D1 of the first active element T1.

It is worth mentioning that, as shown in FIG. 8, the first insulating layer 102 and the second insulating layer 104 are sandwiched between the first gate G1 and the first channel CH1, so the first gate G1 and the first channel CH1 The first insulating layer 102 and the second insulating layer 104 between the channels CH1 are used as gate insulating layers of the first active device T1. Materials of the first and second insulating layers 102 and 104 respectively include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. The total (gate insulating layer) thickness of the first insulating layer 102 and the second insulating layer 104 is, for example, about 3300˜5100 angstroms.

In addition, each pixel region U may further include a capacitive electrode (capacitive coupling portion) 110b. The film layer of the capacitive electrode (capacitive coupling portion) 110b is located between the film layer of the first gate G1 and the film layer of the first drain D1. Where the capacitive electrode (capacitive coupling portion) 110b overlaps with the first drain D1 is a storage capacitor constituting the pixel structure. In other words, the capacitive electrode (capacitive coupling portion) 110b serves as the lower electrode of the storage capacitor, and the first drain D1 serves as the upper electrode of the storage capacitor. The second insulating layer 104 located between the capacitive electrode (capacitive coupling portion) 110 b and the first drain D1 is a capacitive dielectric layer as a storage capacitor. Here, the thickness of the second insulating layer 104 (capacitor dielectric layer) is, for example, about 700˜1500 angstroms.

The driving circuit DR disposed in the non-display area 404 is, for example, a gate driving circuit, a source driving circuit, or both of the gate driving circuit and the source driving circuit. In particular, the driving circuit DR includes at least one second active element T2, and the second active element T2 includes a second gate G2, a second channel CH2, a second source S2, and a second drain D2. The materials of the above-mentioned second channel CH2, the second source S2 and the second drain D2 are respectively the same as or similar to those of the channel CH, the source S and the drain D described in the previous first embodiment, and the above-mentioned first The material of the second gate G2 is, for example, the same as or similar to that of the capacitive electrode described in the first embodiment, so the description will not be repeated here. In addition, an ohmic contact layer OM2 may be further provided between the second channel CH2 and the second source S2/second drain D2.

It is worth mentioning that, as shown in FIG. 8 , the second gate G2 is located on the first insulating layer 102 , and the second insulating layer 104 covers the second gate G2 . Therefore, the second insulating layer 104 is sandwiched between the second gate G2 and the second channel CH2, and thus the second insulating layer 104 is used as a gate insulating layer of the second active element T2. Here, the thickness of the second insulating layer 104 is, for example, about 700-1500 angstroms.

According to this embodiment, the driving circuit DR further includes at least one capacitor. The capacitor includes a lower electrode Eb and an upper electrode Et. The lower electrode Eb is located on the first insulating layer 102 , and the second insulating layer 104 covers the lower electrode Eb. Here, the lower electrode E1 belongs to the same film layer as the capacitive electrode (capacitive coupling portion) 110b in the pixel structure, for example. In addition, the upper electrode Et is located on the second insulating layer 104 above the lower electrode Eb. Here, the upper electrode Et belongs to the same film layer as the first source S1/first drain D1 of the first active element T1 and the second source S2/second drain D2 of the second active element T2, for example. . Therefore, in this embodiment, the capacitor of the driving circuit DR is composed of the upper electrode Et, the lower electrode Eb and the second insulating layer 104 (capacitor dielectric layer).

As mentioned above, in the driving circuit DR of this embodiment, the second active element T2 uses the second insulating layer 104 as the gate insulating layer, and because the thickness of the second insulating layer 104 is sufficiently thin, the second active element T2 can be improved. Drain current of active element T2. Based on this, in this embodiment, the area of the second active element T2 can be reduced while maintaining the overall performance of the existing active elements, so that the driving circuit DR can be applied to a display panel with narrow borders.

In addition, in the driving circuit of this embodiment, the designed capacitor uses the second insulating layer 104 as the capacitor dielectric layer. Since the thickness of the second insulating layer 104 is sufficiently thin, the storage capacitance of the capacitor can be increased. Similarly, the present embodiment can reduce the area of the capacitor (the lower electrode Eb and the upper electrode Et) while maintaining the storage capacity of the existing capacitor, so that the driving circuit DR can be applied to a display panel with narrow borders.

FIG. 9 is a schematic cross-sectional view of a pixel structure and a driving circuit in a display panel according to another embodiment. The embodiment in FIG. 9 is similar to the above-mentioned embodiment in FIG. 8 , so the same elements are denoted by the same symbols and will not be described again. The embodiment of FIG. 9 is different from the embodiment of FIG. 8 in that the capacitor of the driving circuit DR includes a first electrode E1 , a second electrode E2 and a third electrode E3 . Here, the second electrode E2 is equivalent to the lower electrode Eb of FIG. 8 , and the third electrode E3 is equivalent to the upper electrode Et of FIG. 8 . However, in this embodiment, the first electrode E1 is further provided below the second electrode E2. Therefore, the first electrode E1 is located on the substrate 100, and the first insulating layer 102 covers the first electrode E1. The second electrode E2 is located on the first insulating layer 102 , and the second insulating layer 104 covers the second electrode E2 . The third electrode E3 is located on the second insulating layer 104 above the second electrode E2.

In other words, the capacitor of this embodiment is composed of two capacitors connected in parallel, so the storage capacity of the capacitor can be increased. Similarly, this embodiment can reduce the area of the capacitor (the first electrode E1, the second electrode E2 and the third electrode E3) under the premise of maintaining the storage capacitance value of the existing capacitor, so that the driving circuit DR can be applied in a narrow bezel display panel.

third embodiment

FIG. 10 is a schematic diagram of a driving circuit according to an embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of one of the active components and one of the capacitors in the driving circuit of FIG. 10 . Please refer to FIG. 10, the driving circuit of this embodiment is, for example, the driving circuit DR that can be applied to the display panel shown in FIG. 7, and the driving circuit DR of this embodiment is a gate driving circuit as an example, but the present invention is not limited to this. In this embodiment, the driving circuit includes a plurality of active elements M1 - M7 and a plurality of capacitors C1 - C2 . In addition, the scanning line Gn is electrically connected to the active elements M7 and M6 and the capacitor C2, the scanning lines Gn+1 and Gn-1 are electrically connected to the active elements M1 and M4 respectively, and the data line Vss is electrically connected to the active element M2. The signal line CK is electrically connected to the active element M7 and the capacitor C1 , the signal lines H and L are electrically connected to the active elements M4 and M1 respectively, and the signal line XCK is electrically connected to the active element M5 .

As mentioned above, in the driving circuit of FIG. 10 , the active elements M1 - M7 may be composed of the first active element T1 and the second active element T2 described in FIG. 11 . In other words, some of the active elements M1-M7 are composed of the first active element T1 shown in FIG. Component T2 constitutes.

Referring to FIG. 11 , the first active element T1 includes a first gate G1 , a first channel CH1 , a first source S1 and a first drain D1 . In addition, an ohmic contact layer OM1 may be further provided between the first channel CH1 and the first source S1/first drain D1. In addition, the first insulating layer 102 and the second insulating layer 104 are sandwiched between the first gate G1 and the first channel CH1, so the first insulating layer 102 between the first gate G1 and the first channel CH1 And the second insulating layer 104 is used as the gate insulating layer of the first active device T1. Materials of the first and second insulating layers 102 and 104 respectively include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. The total (gate insulating layer) thickness of the first insulating layer 102 and the second insulating layer 104 is, for example, about 3300˜5100 angstroms.

The second active element T2 includes a second gate G2 , a second channel CH2 , a second source S2 and a second drain D2 . In addition, an ohmic contact layer OM2 may be further provided between the second channel CH2 and the second source S2/second drain D2. Here, the second gate G2 is located on the first insulating layer 102, and the second insulating layer 104 covers the second gate G2. Therefore, the second insulating layer 104 is sandwiched between the second gate G2 and the second channel CH2, and thus the second insulating layer 104 is used as a gate insulating layer of the second active element T2. The thickness of the second insulating layer 104 is, for example, about 700-1500 angstroms.

In addition, the capacitors C1 and C2 respectively include a lower electrode Eb and an upper electrode Et. The lower electrode Eb is located on the first insulating layer 102 , and the second insulating layer 104 covers the lower electrode Eb. The upper electrode Et is located on the second insulating layer 104 above the lower electrode Eb. Therefore, the capacitors C1 and C2 are composed of the upper electrode Et, the lower electrode Eb, and the second insulating layer 104 (capacitive dielectric layer).

As mentioned above, in the driving circuit of this embodiment, the first active element T1 uses the first insulating layer 102 and the second insulating layer 104 as gate insulating layers, so the first active element T1 can be used in driving Active components in circuits that require a thicker gate insulating layer. In addition, the second active element T2 uses the second insulating layer 104 as a gate insulating layer. Since the thickness of the second insulating layer 104 is sufficiently thin, the drain current of the second active element T2 can be increased. Based on this, in this embodiment, the area of the second active element T2 can be reduced while maintaining the overall performance of the existing active elements, thereby reducing the overall area of the driving circuit.

In addition, because the capacitors C1 and C2 use the second insulating layer 104 as a capacitor dielectric layer. Since the thickness of the second insulating layer 104 is sufficiently thin, the storage capacitance of the capacitor can be increased. Similarly, in this embodiment, the area of the capacitor (the lower electrode Eb and the upper electrode Et) can be reduced while maintaining the storage capacity of the existing capacitor, thereby reducing the overall area of the driving circuit.

FIG. 12 is a schematic cross-sectional view of some active elements and capacitors in a driving circuit according to another embodiment. The embodiment in FIG. 12 is similar to the above-mentioned embodiment in FIG. 11 , so the same elements are denoted by the same symbols and will not be described again. The embodiment of FIG. 12 is different from the embodiment of FIG. 11 in that the capacitors C1 and C2 of the driving circuit include a first electrode E1 , a second electrode E2 and a third electrode E3 . Here, the second electrode E2 is equivalent to the lower electrode Eb of FIG. 11 , and the third electrode E3 is equivalent to the upper electrode Et of FIG. 11 . However, in this embodiment, the first electrode E1 is further provided below the second electrode E2. Therefore, the first electrode E1 is located on the substrate 100, and the first insulating layer 102 covers the first electrode E1. The second electrode E2 is located on the first insulating layer 102 , and the second insulating layer 104 covers the second electrode E2 . The third electrode E3 is located on the second insulating layer 104 above the second electrode E2.

In other words, the capacitor of this embodiment is composed of two capacitors connected in parallel, so the storage capacity of the capacitor can be increased. Similarly, in this embodiment, the area of the capacitor (the first electrode E1, the second electrode E2, and the third electrode E3) can be reduced while maintaining the storage capacitance value of the existing capacitor, thereby reducing the overall area of the driving circuit .

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the claims.

Claims (26)

1. A pixel structure, located on a substrate, comprising: Scanning lines and data lines; The first active element includes a first gate, a first channel, a first source and a first drain, wherein the scan line is electrically connected to the first gate, and the first source is connected to the data line electrical connection; a pixel electrode electrically connected to the first drain; a first insulating layer located between the first gate and the first channel; a capacitor electrode located on the first insulating layer; and The second insulating layer covers the first insulating layer and the capacitor electrode, and the second insulating layer is located between the capacitor electrode and the first drain. 2. The pixel structure according to claim 1, wherein the capacitive electrode comprises: a capacitive coupling portion overlapping with the first drain constitutes a storage capacitor; and The connection part is connected to the capacitive coupling part. 3. The pixel structure as claimed in claim 2, wherein an extending direction of the connecting portion is parallel to an extending direction of the scanning line. 4. The pixel structure as claimed in claim 2, wherein the connecting portion at least partially overlaps with the pixel electrode. 5. The pixel structure as claimed in claim 4, wherein the connecting portion at least partially overlaps with the data line. 6. The pixel structure as claimed in claim 2, wherein the capacitive coupling part is substantially perpendicular to the connecting part. 7. The pixel structure according to claim 1, wherein the thickness of the second insulating layer is smaller than that of the first insulating layer, and the thickness of the second insulating layer is about 700-1500 angstroms, and the first insulating layer and the first insulating layer are The total thickness of the second insulating layer is about 3300˜5100 angstroms. 8. The pixel structure as claimed in claim 1, wherein the substrate has a pixel area, the data line is arranged at the edge of the pixel area, and the scan line, the first active element and the capacitor electrode are arranged at the edge of the pixel area In the middle, the pixel electrode has a plurality of alignment patterns. 9. The pixel structure according to claim 1, further comprising a passivation layer located between the pixel electrode and the first active element, wherein the passivation layer has a contact window opening, and the pixel electrode passes through the contact window The opening is electrically connected with the first drain. 10. The pixel structure as claimed in claim 1, wherein the capacitor electrode does not overlap with the first gate. 11. The pixel structure as claimed in claim 1, wherein the capacitor electrode overlaps with the first gate or the first channel. 12. The pixel structure as claimed in claim 1, further comprising a passivation layer located between the pixel electrode and the first active element. 13. The pixel structure according to claim 12, further comprising an auxiliary dielectric layer located between the first gate and the second insulating layer, wherein the capacitor electrode is interposed between the auxiliary dielectric layer and the second insulating layer. between insulating layers. 14. A display panel having a display area and a non-display area, the display panel comprising: A plurality of pixel structures as claimed in claim 1 are located in the display area; and At least one driving circuit is located in the non-display area, wherein the driving circuit includes at least one second active element, and the second active element includes: a second gate located on the first insulating layer, and the second insulating layer covers the second gate; a second channel on the first insulating layer above the second gate; and The second source and the second drain are located on the second channel. 15. The display panel as claimed in claim 14, further comprising at least one capacitor located in the non-display area, wherein the capacitor comprises: a lower electrode located on the first insulating layer, and the second insulating layer covers the lower electrode; and The upper electrode is located on the second insulating layer above the lower electrode. 16. The display panel as claimed in claim 14, further comprising at least one capacitor located in the non-display area, wherein the capacitor comprises: a first electrode, and the first insulating layer covers the first electrode; a second electrode located on the first insulating layer, and the second insulating layer covers the second electrode; and The third electrode is located on the second insulating layer above the second electrode. 17. A drive circuit comprising: first grid; a first insulating layer covering the first gate; a second gate located on the first insulating layer; a second insulating layer covering the first insulating layer and the second gate; a first channel disposed on the second insulating layer above the first gate; a second channel disposed on the second insulating layer above the second gate; a first source and a second drain on the first channel; and The second source and the second drain are located on the second channel. 18. The driving circuit according to claim 17, wherein the thickness of the second insulating layer is smaller than the thickness of the first insulating layer, and the thickness of the second insulating layer is about 700˜1500 angstroms, and the first insulating layer and The total thickness of the second insulating layer is about 3300˜5100 angstroms. 19. The drive circuit of claim 17, further comprising at least one capacitor comprising: a lower electrode located on the first insulating layer, and the second insulating layer covers the lower electrode; and The upper electrode is located on the second insulating layer above the lower electrode. 20. The drive circuit of claim 17, further comprising at least one capacitor comprising: a first electrode, and the first insulating layer covers the first electrode; a second electrode located on the first insulating layer, and the second insulating layer covers the second electrode; and The third electrode is located on the second insulating layer above the second electrode. 21. An active component comprising: grid; ditch; a first insulating layer located between the gate and the channel; a source and a drain located above the channel; a capacitor electrode located on the first insulating layer; and The second insulating layer covers the first insulating layer and the capacitor electrode, and the second insulating layer is located between the capacitor electrode and the drain. 22 . The active device as claimed in claim 21 , wherein the capacitive electrode comprises a capacitive coupling portion, and a storage capacitor is formed where the capacitive coupling portion overlaps with the drain. 23. The active device as claimed in claim 21, wherein the capacitor electrode does not overlap with the gate. 24. The active device as claimed in claim 21, wherein the capacitor electrode overlaps with the gate or the channel. 25. The active device of claim 21, wherein the channel is located above the gate. 26. The active device according to claim 21, further comprising an auxiliary dielectric layer located between the gate and the second insulating layer, wherein the capacitor electrode is interposed between the auxiliary dielectric layer and the second insulating layer between layers, and the channel is under the gate.

Images