CN114122023A - A display panel and its manufacturing method - Google Patents
A display panel and its manufacturing method Download PDFInfo
- Publication number
- CN114122023A CN114122023A CN202111399636.4A CN202111399636A CN114122023A CN 114122023 A CN114122023 A CN 114122023A CN 202111399636 A CN202111399636 A CN 202111399636A CN 114122023 A CN114122023 A CN 114122023A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- metal
- interlayer dielectric
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 414
- 229910052751 metal Inorganic materials 0.000 claims abstract description 155
- 239000002184 metal Substances 0.000 claims abstract description 155
- 239000011229 interlayer Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000010409 thin film Substances 0.000 claims abstract description 29
- 239000010408 film Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910052755 nonmetal Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 14
- 238000002310 reflectometry Methods 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 description 18
- 239000004973 liquid crystal related substance Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- -1 polyethylene Polymers 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920000747 poly(lactic acid) Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004626 polylactic acid Substances 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
本申请提供一种显示面板及其制造方法，显示面板包括：衬底基板和设置于衬底基板上的薄膜晶体管层，薄膜晶体管层包括层间介质层和设置于层间介质层上的金属层，金属层包括多个间隔设置的金属电极；其中，层间介质层包括基体介质层和位于基体介质层上的非绝缘介质层，基体介质层与金属电极邻接设置，非绝缘介质层位于金属电极之间的间隙区域。本申请通过在层间介质层对应金属电极之间的间隙区域形成非绝缘介质层，从而能够降低金属层在图案化过程中电浆在层间介质层上的反射率，优化金属电极的侧面形态，大大降低显示面板出现黑阶条纹、亮暗线等问题的几率，达到提升显示面板良率的目的。
The present application provides a display panel and a manufacturing method thereof. The display panel includes: a base substrate and a thin film transistor layer disposed on the base substrate, the thin film transistor layer including an interlayer dielectric layer and a metal layer disposed on the interlayer dielectric layer , the metal layer includes a plurality of metal electrodes arranged at intervals; wherein, the interlayer dielectric layer includes a base dielectric layer and a non-insulating dielectric layer located on the base dielectric layer, the base dielectric layer is adjacent to the metal electrodes, and the non-insulating dielectric layer is located on the metal electrode. gap area between. In the present application, a non-insulating dielectric layer is formed in the gap region between the interlayer dielectric layer corresponding to the metal electrodes, so that the reflectivity of the metal layer on the interlayer dielectric layer during the patterning process can be reduced, and the side profile of the metal electrode can be optimized. , which greatly reduces the probability of black-level stripes, bright and dark lines, etc. on the display panel, and achieves the purpose of improving the yield of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a manufacturing method thereof.
Background
Liquid Crystal Displays (LCDs) have advantages such as high image quality, power saving, thin body, and wide application range, and are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and are becoming the mainstream of Display devices.
An array substrate in the liquid crystal display comprises thin film transistors which are arranged in an array mode, Low Temperature Polysilicon (LTPS) thin film transistors can enable the transistors to obtain a higher on-off current ratio due to higher carrier mobility, each pixel transistor can be smaller in size under the condition that required charging current is met, each pixel light-transmitting area is increased, the aperture opening ratio of a panel is improved, bright spots and high resolution of the panel are improved, power consumption of the panel is reduced, better visual experience is obtained, and the liquid crystal display is widely applied to the field of liquid crystal display.
However, in the conventional LTPS liquid crystal display panel, the source and drain metal layers disposed on the interlayer dielectric layer (ILD) are generally composite metal film layers made of multiple materials, and there is a difference in etching rates of different materials, which may cause that when the etching of the source and drain metal layers is about to be completed, the gradually exposed interlayer dielectric layer may reflect plasma in the reaction chamber, and the plasma may bombard the side surfaces of the source and drain, so that an undercut (undercut Cut) phenomenon is more likely to occur, resulting in poor side surface morphology of the source and drain, so that black stripes, bright and dark lines and other problems occur when the liquid crystal display panel displays a picture, which seriously affects product yield and performance, and this problem needs to be solved urgently.
Disclosure of Invention
The application provides a display panel and a manufacturing method thereof, which can greatly reduce the probability of the display panel having the problems of black-order stripes, bright and dark lines and the like, and achieve the purpose of improving the yield of the display panel.
The embodiment of the present application provides a display panel, display panel includes: the thin film transistor layer comprises an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, and the metal layer comprises a plurality of metal electrodes arranged at intervals;
the interlayer dielectric layer comprises a substrate dielectric layer and a non-insulating dielectric layer positioned on the substrate dielectric layer, the substrate dielectric layer is arranged adjacent to the metal electrodes, and the non-insulating dielectric layer is positioned in a gap area between the metal electrodes.
Optionally, the non-insulating dielectric layer is located in a region close to the edge of the metal electrode in the gap region.
Optionally, the substrate dielectric layer is a non-metal nitride film layer, and the non-insulating dielectric layer is a metal nitride film layer.
Optionally, the interlayer dielectric layer further includes a first interlayer dielectric layer and a second interlayer dielectric layer, the second interlayer dielectric layer is located on the first interlayer dielectric layer, the substrate dielectric layer is located on the second interlayer dielectric layer, and the first interlayer dielectric layer and the substrate dielectric layer are made of the same material and are made of different materials.
Optionally, the first interlayer dielectric layer and the substrate dielectric layer are silicon nitride film layers, and the second interlayer dielectric layer is a silicon oxide film layer.
Optionally, the metal layer includes a first metal layer, a second metal layer and a third metal layer sequentially stacked on the interlayer dielectric layer, and the first metal layer and the third metal layer are made of the same material and are made of different materials from the second metal layer.
Optionally, the first metal layer is a titanium metal film layer, the second metal layer is an aluminum metal film layer, and the non-insulating dielectric layer is a titanium nitride film layer.
Optionally, the thin film transistor layer includes an active layer, a gate insulating layer, a gate layer, the interlayer dielectric layer, and the metal layer, which are sequentially stacked on the substrate, and the metal electrode includes a source electrode and a drain electrode.
Optionally, the display panel includes a light shielding layer, a buffer layer, a thin film transistor layer, a planarization layer, a common electrode layer, a passivation layer, and a pixel electrode layer, which are stacked in sequence.
Correspondingly, the embodiment of the application also provides a manufacturing method of the display panel, which comprises the following steps:
providing a substrate, and sequentially forming a light shielding layer, a buffer layer, a thin film transistor layer, a flat layer, a common electrode layer, a passivation layer and a pixel electrode layer on the substrate;
the thin film transistor layer comprises an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, the metal layer comprises a plurality of metal electrodes arranged at intervals, the interlayer dielectric layer comprises a base dielectric layer and a non-insulating dielectric layer positioned on the base dielectric layer, the base dielectric layer is arranged adjacent to the metal electrodes, and the non-insulating dielectric layer is positioned in a gap area between the metal electrodes.
According to the method, the non-insulating medium layer is formed in the gap area between the interlayer medium layer and the metal electrode, so that the reflectivity of the metal layer on the interlayer medium layer in the patterning process can be reduced, the side form of the metal electrode is optimized, the probability of the display panel having the problems of black stripes, bright and dark lines and the like is greatly reduced, and the purpose of improving the yield of the display panel is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of an array substrate structure of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of an interlayer dielectric layer provided in an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a metal layer provided in an embodiment of the present application;
fig. 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials. The following are detailed below, and it should be noted that the order of description of the following examples is not intended to limit the preferred order of the examples.
In the LTPS liquid crystal display panel in the prior art, a source drain metal layer disposed on an interlayer dielectric layer is easy to undercut during an etching process, so that the side forms of a source and a drain formed by etching are poor, and the liquid crystal display panel is easy to have problems of black stripes, bright and dark lines and the like when displaying images, thereby seriously affecting the yield and performance of products.
Based on the above problems, embodiments of the present invention provide a display panel, where a metal layer of the display panel includes a plurality of metal electrodes arranged at intervals, and a non-insulating dielectric layer is formed in a gap region between interlayer dielectric layers and corresponding to the metal electrodes of the display panel, so that a reflectivity of plasma on the interlayer dielectric layers during patterning of the metal layer can be reduced, a side form of the metal electrodes is optimized, a probability of occurrence of black stripes, bright and dark lines, and the like in the display panel is greatly reduced, and a purpose of improving a yield of the display panel is achieved.
The following description will be made in detail by taking an example in which the type of the display panel is a liquid crystal display panel, but the application does not limit the type of the display panel, and the display panel may also be an Organic Light Emitting Diode (OLED) display panel or a Micro light emitting diode (Micro LED or Mini LED) display panel, and the inventive concept of the application is used as long as the display panel has an interlayer dielectric layer and a patterned metal layer structure on the interlayer dielectric layer.
In this embodiment, the display panel is a liquid crystal display panel, and the display panel includes, for example, an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. It should be noted that the color filter substrate is used to form a liquid crystal cell with the array substrate, but a color filter is not necessarily disposed on the color filter substrate, and the color filter may also be directly disposed on the array substrate.
In this embodiment, in a direction perpendicular to the array substrate, a plurality of data lines extending along a first direction and a plurality of scan lines extending along a second direction are formed on the array substrate, the second direction is, for example, perpendicular to the first direction, sub-pixel units are correspondingly formed in a grid structure defined by the data lines and the scan lines in a staggered manner, a pixel electrode is disposed in each sub-pixel unit, a thin film transistor arranged in an array is further formed on the array substrate, the thin film transistor includes a gate, a source, and a drain, the gate is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode.
The film layer structure of the thin film transistor and the respective film layer structures above and below the thin film transistor layer are further described in detail below.
Fig. 1 is a schematic structural diagram of an array substrate of a display panel provided in an embodiment of the present application, fig. 2 is a schematic structural diagram of an interlayer dielectric layer provided in the embodiment of the present application, and fig. 3 is a schematic structural diagram of a metal layer provided in the embodiment of the present application. As shown in fig. 1, 2 and 3, the array substrate includes: the substrate 10 may be a rigid substrate or a flexible substrate, and the material of the substrate 10 includes one or more of glass, plastic, silica, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide, or polyurethane.
In this embodiment, the array substrate further includes: the thin film transistor layer is arranged on the substrate 10 and comprises an interlayer dielectric layer 70 and a metal layer 80 arranged on the interlayer dielectric layer 70, and the metal layer 80 comprises a plurality of metal electrodes 810 arranged at intervals; the interlayer dielectric layer 70 includes a base dielectric layer 730 and a non-insulating dielectric layer 740 located on the base dielectric layer 730, the base dielectric layer 730 is adjacent to the metal electrodes 810, and the non-insulating dielectric layer 740 is located in a gap region between the metal electrodes 810.
Specifically, the metal layer 80 includes a plurality of metal electrodes 810 arranged at intervals, and the plurality of metal electrodes 810 arranged at intervals are formed by the metal layer 80 through a patterning process, such as an etching process, for example, dry etching. When the metal layer 80 is etched, the metal layer 80 needs to be disposed in a reaction chamber of a specific environment, and ions in plasma (plasma) in the reaction chamber are accelerated under the action of an electric field to bombard the surface of the metal layer 80. The applicant finds that a film layer on one side, close to the metal layer, of the current interlayer dielectric layer is a silicon oxide film layer, the silicon oxide film layer and metal ions in the metal layer can generate an insulating medium when the metal layer is about to be etched, the insulating medium has high reflectivity to the plasma, the plasma reflected by the insulating medium can bombard the side face of the metal layer, the side face of the metal layer is poor in shape, an edge slope (Taper) angle which cannot meet requirements is formed, and therefore poor display and yield of a display panel are reduced. In this case, when the metal layer has a multi-layer structure including a plurality of materials, the side surface morphology is further deteriorated due to the difference in etching rate between the respective layers.
In this embodiment, the non-insulating dielectric layer 740 is formed on the interlayer dielectric layer 70 in the gap region corresponding to the metal electrode 810, and the non-insulating dielectric layer 740 has a lower reflectivity to the plasma, and can well pull the plasma to the surface of the non-insulating dielectric layer, so as to reduce the bombardment on the side surface of the metal electrode 810, optimize the side surface form and the Taper angle of the metal electrode 810, and improve the display effect of the display panel.
In this embodiment, the non-insulating dielectric layer 740 is located in a region close to the edge of the metal electrode 810 in the gap region. Specifically, the metal layer 80 includes a first stage and a second stage after the first stage when the etching is about to be completed, wherein in the first stage, the area of the non-insulating dielectric layer 740 corresponding to the gap region formed between the metal electrodes 810 is larger, for example, at this time, the non-insulating dielectric layer 740 is disposed corresponding to the whole gap region, and the non-insulating dielectric layer 740 can pull the plasma to the surface of the non-insulating dielectric layer 740, thereby well preventing the side morphology of the metal electrodes 810 from deteriorating; as the etching proceeds and finally ends, i.e., at the second stage, the area of the non-insulating dielectric layer 740 gradually decreases, and finally the non-insulating dielectric layer 740 remains only in the gap region near the edge of the metal electrode 810.
In this embodiment, the interlayer dielectric layer 70 further includes a substrate dielectric layer 730, and the substrate dielectric layer 730 is adjacent to the metal layer 80. The non-insulating dielectric layer 740 is located on the surface of the substrate dielectric layer 730 and corresponds to the gap region between the metal electrodes 810, the non-insulating dielectric layer 740 is formed by compounding and converting the substrate dielectric layer 730 and metal ions in the metal layer 80, the substrate dielectric layer 730 is non-metal nitride, and the non-insulating dielectric layer 740 is metal nitride. Specifically, when the metal layer 80 is etched, the metal ions in the metal layer 80 at the bottom layer can be recombined with the base dielectric layer 730 under the action of the plasma to form the non-insulating dielectric layer 740. Preferably, the substrate dielectric layer 730 is a silicon nitride film layer, but the specific material of the substrate dielectric layer 730 is not limited in this application, and the substrate dielectric layer may also be another non-metal nitride film layer, where another non-metal is, for example, another non-metal element in the same group as silicon element.
In this embodiment, the interlayer dielectric layer 70 further includes a first interlayer dielectric layer 710 and a second interlayer dielectric layer 720 sequentially stacked on the substrate 10, and the first interlayer dielectric layer 710 and the base dielectric layer 730 are made of the same material and are made of a different material from the second interlayer dielectric layer 720. Preferably, the second interlayer dielectric layer 720 is a silicon oxide film layer, and the first interlayer dielectric layer 710 is a silicon nitride film layer. The structure of the silicon nitride film layer/the silicon oxide film layer/the silicon nitride film layer sequentially stacked on the substrate 10 can improve the electrical properties of the interlayer dielectric layer 70 while ensuring the optical properties thereof. And because the silicon nitride film layer is easier to etch and the silicon oxide film layer is relatively difficult to etch under the action of the same etching gas in the etching process, the occurrence of lateral etching can be further reduced when the metal layer 80 is to be etched. Preferably, the etching gas is, for example, BCl3 and/or Cl 2.
In this embodiment, the metal layer 80 includes a first metal layer 810, a second metal layer 820 and a third metal layer 830 sequentially stacked on the interlayer dielectric layer 70, and the first metal layer 810 and the third metal layer 830 are made of the same material and are made of a different material from the second metal layer 820. Preferably, the first metal layer 810 and the third metal layer 830 are titanium metal film layers, and the second metal layer 820 is an aluminum metal film layer. Correspondingly, when the metal layer 80 is to be etched, the first metal layer 810 at the bottom layer can be recombined with the gradually exposed base dielectric layer 730 under the action of the plasma to form the non-insulating dielectric layer 740 as the etching is continuously performed. Preferably, the non-insulating dielectric layer 740 is a titanium nitride film layer. According to the embodiment of the application, the non-insulating medium layer 740 having a traction effect on the plasma is arranged, so that the problem that the side form of the metal layer is poor can be well avoided.
In this embodiment, the thin film transistor layer includes an active layer 40, a gate insulating layer 50, a gate layer 60, the interlayer dielectric layer 70, and the metal layer 80, which are sequentially stacked on the substrate 10. The active layer 40 comprises a channel region 41, a heavily doped region 42 and a lightly doped region 43, wherein the lightly doped region 43 is located at two sides of the channel region 41, and the heavily doped region 42 is located at two sides of the lightly doped region 43 away from the channel region 41; the gate layer 60 includes a gate, and the metal electrode 810 includes a source 81 and a drain 82. Further, the metal electrode 810 further includes a binding electrode 83.
In this embodiment, the thin film transistor layer further includes a first via hole 71 disposed corresponding to the heavily doped region 42, the first via hole 71 penetrates through the gate insulating layer 50 and the interlayer dielectric layer 70, and the source 81 and the drain 82 are overlapped with the heavily doped region 42 of the active layer 40 through the first via hole 71.
In this embodiment, the thin film transistor in the thin film transistor layer is a low-temperature polysilicon thin film transistor, the forming material of the channel region 41 of the active layer 40 is low-temperature polysilicon, the high carrier mobility of the low-temperature polysilicon thin film transistor can enable the transistor to obtain a higher on-off current ratio, and under the condition of satisfying the required charging current, each thin film transistor can be smaller in size, so that the light-transmitting area of each sub-pixel unit is increased, the aperture opening ratio of the display panel is improved, the bright point and the high resolution of the display panel are improved, the power consumption of the display panel is reduced, and better visual experience is obtained.
In this embodiment, the display panel includes a light-shielding layer 20, a buffer layer 30, the thin film transistor layer, a planarization layer 90, a common electrode layer 100, a passivation layer 110, and a pixel electrode layer 120, which are sequentially stacked, wherein a vertical projection of the light-shielding layer 20 on the substrate 10 covers a vertical projection of the active layer 40 on the substrate 10, and the light-shielding layer 20 is used to prevent performance degradation of the active layer 40 due to illumination; the buffer layer 30 has a buffer function and ensures the film-forming quality of the active layer 40; the planarization layer 90 is used for planarizing the thin-film transistor layer; the common electrode layer 100 is formed with a common electrode and a touch electrode line; the passivation layer 110 is used for electrically insulating the common electrode layer 100 and the pixel electrode layer 120; the pixel electrode layer 120 is formed with a pixel electrode electrically connected to the drain electrode 82. Specifically, the display panel further includes a second via hole 91 and a third via hole 111, the second via hole 91 is formed on the flat layer 90 and is disposed corresponding to the bonding electrode 83, and the touch electrode line is overlapped with the bonding electrode 83 through the second via hole 91; the third via hole 111 is formed on the passivation layer 110 and the planarization layer 90, and is disposed corresponding to the drain electrode 82, and the pixel electrode overlaps the drain electrode 82 through the third via hole 111.
On the other hand, the present application further provides a manufacturing method of a display panel, fig. 4 is a flowchart of a manufacturing method of a display panel provided in an embodiment of the present application, and with reference to fig. 1 to 4, an embodiment of the present application provides a manufacturing method of a display panel for manufacturing the display panel in the above embodiment. Specifically, the manufacturing method of the display panel totally adopts 10 masks, and comprises the following steps:
s10: a substrate 10 is provided, and a light shielding layer 20 is formed on the substrate 10 through a first mask.
S20: a buffer layer 30 is formed on the light-shielding layer 20, and an active layer 40 on the light-shielding layer 20 is formed through a second mask.
S30: a heavily doped region 42 of N-type is formed on the active layer 40 by a third mask.
S40: a gate insulating layer 50 is formed on the active layer 40, a gate layer 60 including a gate electrode is formed on the gate insulating layer 50 through a fourth mask, and then the N-type lightly doped region 43 is formed using the gate electrode as a hard mask.
S50: an interlayer dielectric layer 70 is formed on the gate layer 60, and first via holes 71 are formed on the gate insulating layer 50 and the interlayer dielectric layer 70 through a fifth photomask, wherein the positions of the first via holes 71 respectively correspond to the N-type heavily doped regions 42.
In this embodiment, the interlayer dielectric layer 70 includes a first interlayer dielectric layer 710, a second interlayer dielectric layer 720, and a base dielectric layer 730 sequentially stacked on the substrate 10, where the first interlayer dielectric layer 710 and the base dielectric layer 730 are silicon nitride film layers, and the second interlayer dielectric layer 720 is a silicon oxide film layer.
S60: and forming a metal layer 80 comprising a plurality of metal electrodes 810 on the interlayer dielectric layer 70 through a sixth photomask, wherein the metal electrodes 810 comprise a source 81, a drain 82 and a binding electrode 83, and the source 81 and the drain 82 are respectively overlapped with the N-type heavily doped region 42 through the first via hole 71.
In this embodiment, in the etching process of the metal layer 80, when the metal layer 80 is to be etched, the metal layer 80 at the bottom layer can be recombined with the base dielectric layer 730 under the action of the plasma along with the continuous etching, so as to generate a non-insulating dielectric layer 740 on the surface of the base dielectric layer 730 corresponding to the gap region between the metal electrodes 810, and the metal layer 80 at the bottom layer is, for example, a titanium metal layer. It should be noted that as the etching progress progresses, the area of the non-insulating dielectric layer 740 formed in the gap region is also reduced, and finally, the non-insulating dielectric layer 740 is only left in the gap region near the edge of the metal electrode 810. Specifically, the metal layer 80 includes a first stage and a second stage after the first stage when the etching is about to be completed, wherein in the first stage, the area of the non-insulating dielectric layer 740 corresponding to the gap region formed between the metal electrodes 810 is larger, for example, at this time, the non-insulating dielectric layer 740 is disposed corresponding to the whole gap region, and the non-insulating dielectric layer 740 can pull the plasma to the surface of the non-insulating dielectric layer 740, thereby well preventing the side morphology of the metal electrodes 810 from deteriorating; as the etching proceeds and finally ends, i.e., at the second stage, the area of the non-insulating dielectric layer 740 gradually decreases, and finally the non-insulating dielectric layer 740 remains only in the gap region near the edge of the metal electrode 810.
In this embodiment, the metal layer 80 includes a plurality of metal electrodes 810 arranged at intervals, the metal electrodes 810 include a source electrode 81, a drain electrode 82 and a binding electrode 83, and the source electrode 81 and the drain electrode 82 are respectively overlapped with the N-type heavily doped region 42 of the active layer 40 through the first hole. The metal layer 80 includes a first metal layer 810, a second metal layer 820 and a third metal layer 830 which are sequentially stacked on the interlayer dielectric layer 70, the first metal layer 810 and the third metal layer 830 are titanium metal film layers, and the second metal layer 820 is an aluminum metal film layer.
S70: forming a flat layer 90 on the metal layer 80, and opening a second via hole 91 on the flat layer 90 through a seventh optical mask, where a position of the second via hole 91 corresponds to the drain 82.
S80: a common electrode layer 100 including a common electrode is formed on the flat layer 90 through an eighth optical mask, the common electrode layer 100 includes the common electrode and a touch signal line which are arranged at intervals, and the touch signal line is overlapped with the binding electrode 83 through the second via hole 91.
S90: a passivation layer 110 is formed on the common electrode layer 100, and a third via hole 111 is formed on the planarization layer 90 and the passivation layer 110 through a ninth photomask, where the position of the third via hole 111 corresponds to the drain electrode 82.
S100: a pixel electrode layer 120 is formed on the passivation layer 110 through a tenth mask, and the pixel electrode layer 120 is overlapped with the drain electrode 82 through the third via hole 111.
In summary, the present application provides a display panel and a method of manufacturing the same, the display panel including: the thin film transistor layer comprises an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, and the metal layer comprises a plurality of metal electrodes arranged at intervals; the interlayer dielectric layer comprises a substrate dielectric layer and a non-insulating dielectric layer positioned on the substrate dielectric layer, the substrate dielectric layer is arranged adjacent to the metal electrodes, and the non-insulating dielectric layer is positioned in a gap area between the metal electrodes. According to the method, the non-insulating medium layer is formed in the gap area between the interlayer medium layer and the metal electrode, so that the reflectivity of the metal layer on the interlayer medium layer in the patterning process can be reduced, the side form of the metal electrode is optimized, the probability of the display panel having the problems of black stripes, bright and dark lines and the like is greatly reduced, and the purpose of improving the yield of the display panel is achieved.
The display panel and the manufacturing method thereof provided by the embodiment of the present invention are described in detail above, and the principle and the embodiment of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A display panel, comprising: the thin film transistor layer comprises an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, and the metal layer comprises a plurality of metal electrodes arranged at intervals;
the interlayer dielectric layer comprises a substrate dielectric layer and a non-insulating dielectric layer positioned on the substrate dielectric layer, the substrate dielectric layer is arranged adjacent to the metal electrodes, and the non-insulating dielectric layer is positioned in a gap area between the metal electrodes.
2. The display panel according to claim 1, wherein the non-insulating dielectric layer is located in a region near an edge of the metal electrode in the gap region.
3. The display panel according to claim 2, wherein the base dielectric layer is a non-metal nitride film layer, and the non-insulating dielectric layer is a metal nitride film layer.
4. The display panel according to claim 3, wherein the interlayer dielectric layer further comprises a first interlayer dielectric layer and a second interlayer dielectric layer, the second interlayer dielectric layer is located on the first interlayer dielectric layer, the base dielectric layer is located on the second interlayer dielectric layer, and the first interlayer dielectric layer and the base dielectric layer are made of the same material and are made of different materials.
5. The display panel according to claim 4, wherein the first interlayer dielectric layer and the base dielectric layer are silicon nitride film layers, and the second interlayer dielectric layer is a silicon oxide film layer.
6. The display panel according to claim 5, wherein the metal layer comprises a first metal layer, a second metal layer and a third metal layer sequentially stacked on the interlayer dielectric layer, and the first metal layer and the third metal layer are made of the same material and are made of a different material from the second metal layer.
7. The display panel according to claim 6, wherein the first metal layer is a titanium metal film layer, the second metal layer is an aluminum metal film layer, and the non-insulating dielectric layer is a titanium nitride film layer.
8. The display panel of claim 1, wherein the thin-film transistor layer comprises an active layer, a gate insulating layer, a gate layer, the interlayer dielectric layer and the metal layer, which are sequentially stacked on the substrate, and the metal electrode comprises a source electrode and a drain electrode.
9. The display panel according to claim 8, wherein the display panel comprises a light-shielding layer, a buffer layer, the thin-film transistor layer, a planarization layer, a common electrode layer, a passivation layer, and a pixel electrode layer, which are sequentially stacked.
10. A manufacturing method of a display panel is characterized by comprising the following steps: providing a substrate, and sequentially forming a light shielding layer, a buffer layer, a thin film transistor layer, a flat layer, a common electrode layer, a passivation layer and a pixel electrode layer on the substrate;
the thin film transistor layer comprises an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, the metal layer comprises a plurality of metal electrodes arranged at intervals, the interlayer dielectric layer comprises a base dielectric layer and a non-insulating dielectric layer positioned on the base dielectric layer, the base dielectric layer is arranged adjacent to the metal electrodes, and the non-insulating dielectric layer is positioned in a gap area between the metal electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111399636.4A CN114122023A (en) | 2021-11-19 | 2021-11-19 | A display panel and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111399636.4A CN114122023A (en) | 2021-11-19 | 2021-11-19 | A display panel and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114122023A true CN114122023A (en) | 2022-03-01 |
Family
ID=80440694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111399636.4A Pending CN114122023A (en) | 2021-11-19 | 2021-11-19 | A display panel and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114122023A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101151716A (en) * | 2005-04-04 | 2008-03-26 | 先进微装置公司 | CD-reducing etching process for ARC materials |
| CN108511461A (en) * | 2018-03-29 | 2018-09-07 | 武汉华星光电技术有限公司 | Display device and its array substrate |
| WO2019000493A1 (en) * | 2017-06-28 | 2019-01-03 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor array substrate and manufacturing method thereof, and oled display device |
| CN109841575A (en) * | 2017-11-28 | 2019-06-04 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor structure |
| WO2020048020A1 (en) * | 2018-09-03 | 2020-03-12 | 深圳市华星光电技术有限公司 | Thin film transistor, display panel, and method for manufacturing thin film transistor |
| US20200091203A1 (en) * | 2018-09-17 | 2020-03-19 | Ordos Yuansheng Optoelectronics Co., Ltd. | Array substrate, method for manufacturing the same, and display device |
| CN111613664A (en) * | 2020-05-26 | 2020-09-01 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor, method for producing the same, and display panel |
-
2021
- 2021-11-19 CN CN202111399636.4A patent/CN114122023A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101151716A (en) * | 2005-04-04 | 2008-03-26 | 先进微装置公司 | CD-reducing etching process for ARC materials |
| WO2019000493A1 (en) * | 2017-06-28 | 2019-01-03 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor array substrate and manufacturing method thereof, and oled display device |
| CN109841575A (en) * | 2017-11-28 | 2019-06-04 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor structure |
| CN108511461A (en) * | 2018-03-29 | 2018-09-07 | 武汉华星光电技术有限公司 | Display device and its array substrate |
| WO2020048020A1 (en) * | 2018-09-03 | 2020-03-12 | 深圳市华星光电技术有限公司 | Thin film transistor, display panel, and method for manufacturing thin film transistor |
| US20200091203A1 (en) * | 2018-09-17 | 2020-03-19 | Ordos Yuansheng Optoelectronics Co., Ltd. | Array substrate, method for manufacturing the same, and display device |
| CN111613664A (en) * | 2020-05-26 | 2020-09-01 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor, method for producing the same, and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10964790B1 (en) | TFT substrate and manufacturing method thereof | |
| JP3980156B2 (en) | Active matrix display device | |
| CN101901787B (en) | Oxide thin film transistor and method for manufacturing the same | |
| EP3188249B1 (en) | Thin film transistor, manufacturing method therefor, display substrate and display device | |
| US9535300B2 (en) | Pixel structure and liquid crystal panel | |
| TWI532154B (en) | Display panel and display device | |
| US20170255044A1 (en) | Tft substrates and the manufacturing methods thereof | |
| WO2020056803A1 (en) | Display panel and manufacturing method therefor, and display module | |
| US9502536B2 (en) | Manufacturing method of thin film transistor display panel | |
| US10312266B2 (en) | Display substrate and manufacturing method thereof, and display device | |
| US9761615B2 (en) | Array substrate, manufacturing method thereof and display device | |
| TWI590423B (en) | Display device | |
| CN105679714A (en) | Array substrate and manufacturing method therefor | |
| TWI555183B (en) | Thin film transistor and pixel structure | |
| CN104698661A (en) | Display panel and method for manufacturing the same | |
| CN106158739A (en) | Array substrate of display and manufacturing method thereof | |
| CN105655349B (en) | Array substrate and manufacturing method thereof, display panel, display device | |
| WO2018028304A1 (en) | Display substrate and method for fabricating same, and display panel | |
| US9651843B2 (en) | Thin film transistor array substrate and manufacturing method thereof | |
| US10347662B2 (en) | Array substrate, manufacturing method thereof, and display panel | |
| CN108663862B (en) | Display panel | |
| US10749036B2 (en) | Oxide semiconductor thin film transistor having spaced channel and barrier strips and manufacturing method thereof | |
| US20250015091A1 (en) | Array substrate, method for manufacturing same, and display panel | |
| CN114122023A (en) | A display panel and its manufacturing method | |
| US7338824B2 (en) | Method for manufacturing FFS mode LCD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |