CN107769606B - Capacitive current double-frequency pulse sequence control method and device thereof - Google Patents

Abstract

The invention relates to power electronic equipment, in particular to a capacitive current double-frequency pulse sequence control method and a device thereof, which complete the control of a converter switching tube and realize the adjustment of an output branch by limiting the turn-off or turn-on time of a switching tube and the peak value or the valley value of the capacitive current. Compared with the traditional pulse sequence control switch converter, the invention has the advantages of small output voltage ripple, optimal pulse cycle period combination mode, no low-frequency oscillation phenomenon, good load transient performance and the like, and can be used for controlling various switch converters, such as: buck converters, boost converters, buck-Boost converters, flyback converters, forward converters, and the like.

Description

Capacitive current dual-frequency pulse sequence control method and device

Technical field

The invention relates to power electronic equipment, in particular to a capacitive current dual-frequency pulse sequence control method and its device.

Background technique

Compared with traditional linear regulated power supplies, switching converters are widely used due to their excellent properties such as small size, light weight and high efficiency. Currently, switching converters generally use pulse width modulation (Pulse Width Modulation, PWM) and pulse frequency modulation (Pulse Frequency Modulation, PFM) technologies to control the output voltage. PWM modulation technology realizes control of the output voltage by adjusting the width of the control pulse. It is a constant frequency control method and has the advantage of simple feedback control loop design. However, it suffers from low light load efficiency, slow dynamic response, and electromagnetic interference. (Electromagnetic Interference, EMI) and other serious shortcomings; PFM modulation technology achieves control of the output voltage by changing the frequency of the control pulse. It effectively solves the problem of low light load efficiency, but because the switching frequency changes with the change of the input voltage or load changes, thus increasing the difficulty of designing feedback control loops and EMI filters.

Pulse Train (PT) modulation is a modulation method that is completely different from PWM and PFM. It adjusts the converter by adjusting two sets of high and low control pulse combinations with the same frequency and different duty cycles. It is a A nonlinear discrete modulation method. PT modulation does not require an error amplifier and corresponding compensation network. It has the advantages of simple controller implementation and fast dynamic response to changes in input and load. It has attracted widespread attention from academia and industry. When the PT-controlled converter operates in the inductor current discontinuous conduction mode (DCM), the inductor current is always zero at the beginning of a switching cycle, so the change in inductor energy storage is zero, and the inductor does not affect the energy transfer process. , but the load capacity of the DCM switching converter is limited, the inductor current peak value is high and the output voltage ripple is large. When the PT control converter operates in the inductor current continuous conduction mode (CCM), if the inductor current is not equal at the beginning of a switching cycle, the change in the inductor energy storage is not zero, and the inductor will participate in the energy transfer process. . Therefore, the change in inductor energy storage indirectly affects the output voltage of the PT-controlled CCM switching converter, making the controller's adjustment of the output voltage hysteretic, resulting in low-frequency oscillation and slow transient response of the switching converter.

In view of the low-frequency oscillation problem of PT-controlled CCM switching converters, some scholars have proposed valley current PT control methods, capacitor current PT control methods, etc. In the steady state, the pulse sequence cycle of these control methods consists of multiple high pulses and multiple low pulses. The inductor current and output voltage ripple are large, which affects the steady-state performance of the converter.

Contents of the invention

The purpose of the present invention is to provide a control method for a switching converter, which overcomes the technical shortcomings of the existing pulse sequence control when the inductor current is in the continuous conduction mode, and has a steady-state pulse sequence cycle period of "1 high pulse + 1 low pulse" combination method, with small steady-state ripples in inductor current and output voltage, strong stability and anti-interference ability, and good load transient performance, etc., and is suitable for switching converters with various topologies.

The technical solutions adopted by the present invention to achieve its inventive purpose are:

The capacitor current dual-frequency pulse sequence control method detects the output voltage at the beginning of each switching cycle to obtain the signal V _o , detects the current of the output filter capacitor and obtains the signal i _c ; combine V _o , the switching tube pulse signal V _P and the output The voltage reference value V _ref is sent to the first pulse selector PS1 to generate pulse signals SS and SS1; the pulse signal VH1 generated by SS and the first pulse generator PGH is sent to the first controlled constant time timer CT1 to generate the signal HH ; Send i _C , HH and the first capacitor current reference value I _ref1 to the first pulse generator PGH to generate pulse signals VH and VH1 ; Send the pulse signal VL1 generated by SS1 and the second pulse generator PGL to the second The controlled constant time timer CT2 generates the signal LL; sends i _C , LL and the second capacitor current reference value I _ref2 to the second pulse generator PGL to generate the pulse signals VL and VL1; sends VH, VL, SS and SS1 The pulse signal V _P is input to the second pulse selector PS2 to control the turn-on and turn-off of the converter switch tube.

Further, the first capacitor current reference value I _ref1 is a preset capacitor current reference value, which is a directly set capacitor current peak value or a capacitor current peak value generated by the input and output feedback quantities and related to the input quantity or output quantity. .

The second capacitor current reference value I _ref2 is a preset capacitor current reference value, which is a directly set capacitor current valley value or a capacitor current valley value generated by the input and output feedback quantities and related to the input quantity or output quantity.

The invention also provides a device for the capacitive current dual-frequency pulse sequence control method, which includes a voltage detection circuit VS, a current detection circuit IS, a first pulse selector PS1, a second pulse selector PS2, and a first controlled constant time timer CT1 , the second controlled constant time timer CT2, the first pulse generator PGH, the second pulse generator PGL and the drive circuit DR; the voltage detection circuit VS is connected to the first pulse selector PS1; the first pulse selector The output signal SS of PS1 is connected to the first controlled constant time timer CT1; the output signal SS1 of the first pulse selector PS1 is connected to the second controlled constant time timer CT2; the first controlled constant time timer CT1 and the current The detection circuit IS is connected to the first pulse generator PGH respectively, and the output signal VH1 of PGH is connected to the first controlled constant time timer CTI; the second controlled constant time timer CT2 and the current detection circuit IS are connected to the second pulse generator respectively. The output signal VL1 of the second pulse generator PGL is connected to the second controlled constant time timer CT2; the output signal VH of the first pulse generator PGH, the output signal VL of the second pulse generator PGL, the first The output signals SS and SS1 of the pulse selector PS1 are respectively connected to the second pulse selector PS2; the second pulse selector PS2 is connected to the driving circuit DR and the first pulse selector PS1 respectively.

Further, the first pulse selector PS1 includes a first comparator CMP1 and a first flip-flop DFF1; the detected output voltage signal _Vo is connected to the negative polarity terminal of the first comparator CMP1, and the output voltage reference value V _ref It is connected to the positive polarity terminal of the first comparator CMP1; the first comparator CMP1 is connected to the D terminal of the first flip-flop DFF1, and the switch pulse signal _VP is connected to the C terminal of the first flip-flop DFF1.

Further, the second pulse selector PS2 includes a first AND gate AND1, a second AND gate AND2 and an OR gate OR; the pulse signal VH generated by the first pulse generator PGH, the pulse signal generated by the first pulse selector SS is connected to the input terminal of the first AND gate AND1; the pulse signal VL generated by the second pulse generator PGL and the pulse signal SS1 generated by the first pulse selector are connected to the input terminal of the second AND gate AND2; the first AND gate AND1 , the output terminal of the second AND gate AND2 is connected to the input terminal of the OR gate OR.

Further, the first pulse generator PGH includes a second comparator CMP2 and a second flip-flop RSFF2; the detected capacitor current signal iC is connected to the positive polarity terminal of the second comparator CMP2, and the first peak capacitor current reference value Iref1 is connected to the negative polarity terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the R terminal of the second flip-flop RSFF2, and the output signal HH of the first controlled constant time timer CT1 is connected to the second flip-flop RSFF2. The S end is connected.

The second pulse generator PGL includes a third comparator CMP3 and a third flip-flop RSFF3. The detected capacitor current signal i _C is connected to the positive polarity terminal of the third comparator CMP3, and the second peak capacitor current reference signal I _ref2 is connected to the positive polarity terminal of the third comparator CMP3. The negative polarity terminal of the third comparator CMP3 is connected; the output terminal of the third comparator CMP3 is connected with the R terminal of the third flip-flop RSFF3, and the output signal LL of the second controlled constant time timer CT2 is connected with the S terminal of the third flip-flop RSFF3. end connected.

Further, the first pulse generator PGH includes a second comparator CMP2 and a second flip-flop RSFF2; the detected capacitor current signal i _C is connected to the negative polarity terminal of the second comparator CMP2, and the first valley capacitor current The reference value I _ref1 is connected to the positive polarity terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the S terminal of the second flip-flop RSFF2, and the output signal HH of the first controlled constant time timer CT1 is connected to the second The R terminal of flip-flop RSFF2 is connected.

The second pulse generator PGL includes a third comparator CMP3 and a third flip-flop RSFF3. The detected capacitor current signal i _C is connected to the negative polarity terminal of the third comparator CMP3, and the second valley capacitor current reference signal I _ref2 Connected to the positive polarity terminal of the third comparator CMP3; the output terminal of the third comparator CMP3 is connected to the S terminal of the third flip-flop RSFF3, and the output signal LL of the second controlled constant time timer CT2 is connected to the S terminal of the third flip-flop RSFF3. The R end is connected.

The invention has the advantages of small output voltage ripple, optimal combination of pulse cycle periods, no low-frequency oscillation phenomenon, and good load transient performance. It can be used to control a variety of switching converters, such as: Buck converters, Boost converters, Buck-boost converter, Flyback converter, Forward converter, etc.

Compared with the prior art, the beneficial effects of the present invention are:

1. The present invention provides a simple and reliable pulse sequence control method for the continuous conduction mode switching converter, which overcomes the shortcomings of low-frequency oscillation in the traditional pulse sequence control continuous conduction mode switching converter, and has better stability and reliability. high.

2. The pulse sequence control method provided by the present invention can quickly adjust the on and off of the switching tube when the load changes, and the change in the output voltage is small.

3. In the continuous conduction mode switching converter pulse sequence control method provided by the present invention, the combination of the pulse sequence cycle period is always "1 high pulse + 1 low pulse", and the ripples of the inductor current and output voltage are small.

Description of the drawings

Figure 1 is a circuit structural block diagram of a control method according to Embodiment 1 of the present invention.

FIG. 2 is a circuit structural block diagram of the first pulse selector PS1 in Embodiment 1 of the present invention.

FIG. 3 is a circuit structural block diagram of the second pulse selector PS2 in Embodiment 1 of the present invention.

FIG. 4 is a circuit structural block diagram of the first pulse generator PGH according to Embodiment 1 of the present invention.

FIG. 5 is a circuit structural block diagram of the second pulse generator PGL according to Embodiment 1 of the present invention.

Figure 6 is a circuit structural block diagram of Embodiment 1 of the present invention.

FIG. 7 is a schematic diagram of main waveforms of the Buck converter during steady-state operation according to Embodiment 1 of the present invention.

Figure 8(a) shows the transient time domain simulation waveform of the capacitor current PT-controlled Buck converter in Embodiment 1 of the present invention when the load suddenly increases from 3A to 8A;

Figure 8(b) shows the transient time domain simulation waveform of the capacitor current PT-controlled Buck converter in Embodiment 1 of the present invention when the load suddenly increases from 3A to 8A.

Figure 9(a) shows the transient time domain simulation waveform of the capacitor current PT-controlled Buck converter in Embodiment 1 of the present invention when the load is suddenly reduced from 8A to 3A;

Figure 9(b) shows the transient time domain simulation waveform of the capacitor current PT-controlled Buck converter in Embodiment 1 of the present invention when the load suddenly decreases from 8A to 3A.

FIG. 10 is a circuit structural block diagram of the first pulse generator PGH according to Embodiment 2 of the present invention.

Figure 11 is a circuit structural block diagram of the second pulse generator PGL in Embodiment 2 of the present invention.

Figure 12 is a schematic diagram of the main waveforms of the Buck converter during steady state operation in Embodiment 2 of the present invention.

Figure 13 is a circuit structural block diagram of Embodiment 3 of the present invention.

Detailed ways

The present invention will be described in further detail below through specific examples and in conjunction with the accompanying drawings.

Example 1:

Figure 1 shows that a specific implementation mode of the present invention is: a dual-frequency capacitor current pulse sequence control method and its device. The device mainly consists of a voltage detection circuit VS, a current detection circuit IS, a first pulse selector PS1, a first Composed of pulse selector PS2, first controlled constant time timer CT1, second controlled constant time timer CT2, first pulse generator PGH, second pulse generator PGL and drive circuit DR; at the beginning of each switching cycle moment, detect the output voltage of the output branch and obtain the signal V _o , detect the filter capacitor current of the output branch and obtain the signal i _c ; send V _o , switch tube pulse signal V _P and output voltage reference value V _ref to the third A pulse selector PS1 generates pulse signals SS and SS1; sends SS and the pulse signal VH1 generated by the first pulse generator PGH to the first controlled constant time timer CT1 to generate the signal HH; connects i _C , HH and the first The capacitor current reference value I _ref1 is sent to the first pulse generator PGH to generate pulse signals VH and VH1; the pulse signal VL1 generated by SS1 and the second pulse generator is sent to the second controlled constant time timer CT2 to generate the signal LL. ;Send i _C , LL and the second capacitor current reference value I _ref2 to the second pulse generator PGL to generate pulse signals VL and VL1; send VH, VL, SS and SS1 to the second pulse selector PS2 to generate pulses Signal _VP is used to control the turn-on and turn-off of the converter switch tube.

Figure 2 shows that the specific composition of the first pulse selector PS1 in this example is: composed of the first comparator CMP1 and the first flip-flop DFF1; the detected output voltage signal V _o is connected to the negative polarity terminal of the first comparator CMP1 connected, the output voltage reference value V _ref is connected to the positive terminal of the first comparator CMP1; the output terminal of the first comparator CMP1 is connected to the D terminal of the first flip-flop DFF1, and the switching tube pulse signal V _p is connected to the first flip-flop DFF1 The C terminal is connected.

Figure 3 shows that the specific composition of the second pulse selector PS2 in this example is: composed of the first AND gate AND1, the second AND gate AND2 and the OR gate OR; the pulse signal VH generated by the first pulse generator PGH, the The pulse signal SS generated by a pulse selector is connected to the input end of the first AND gate AND1; the pulse signal VL generated by the second pulse generator PGL, the pulse signal SS1 generated by the first pulse selector and the input of the second AND gate AND2 terminals are connected; the output terminal of the first AND gate AND1 and the output terminal of the second AND gate AND2 are connected with the input terminal of the OR gate OR.

Figure 4 shows that the specific composition of the first pulse generator PGH in this example is: composed of the second comparator CMP2 and the second flip-flop RSFF2; the detected capacitor current signal i _C and the positive polarity terminal of the second comparator CMP2 connected, the first peak capacitance current reference value I _ref1 is connected to the negative polarity terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the R terminal of the second flip-flop RSFF2, and the first controlled constant time timer CT1 The output signal HH is connected to the S terminal of the second flip-flop RSFF2.

Figure 5 shows that the specific composition of the second pulse generator PGL in this example is: composed of the third comparator CMP3 and the third flip-flop RSFF3; the detected capacitor current signal i _C is connected to the positive polarity terminal of the third comparator CMP3 connected, the second peak capacitance current reference value I _ref2 is connected to the negative polarity terminal of the third comparator CMP3; the output terminal of the third comparator CMP3 is connected to the R terminal of the third flip-flop RSFF3, and the second controlled constant time timer CT2 The output signal LL is connected to the S terminal of the third flip-flop RSFF3.

This example uses the device in Figure 6 to implement the above control method conveniently and quickly. Figure 6 shows that the device of the dual-frequency capacitor current pulse sequence control method in this example is composed of a control device of the converter TD and the switch tube S.

The working process and principle of the device in this example are:

The working process and principle of the control device using dual-frequency capacitor current pulse sequence control is: Figure 1-7 shows that at the beginning of the switching cycle, the sampled output voltage _Vo is compared with the output voltage reference value V _ref . If the output voltage V _o is less than the output voltage reference value V _ref , then the output signal SS of the first pulse selector PS1 is high level, the first controlled constant time timer CT1 starts timing, and at the same time, the output signal VH of the first pulse generator PGH is low level, the output signal V _p of the second pulse selector PS2 is low level, the switch S is turned off, and the capacitor current i _C decreases; after a fixed time interval T _H , the first controlled constant time timer CT1 outputs a signal HH becomes high level, the output signal VH of the first pulse generator PGH is high level, the output signal V _p of the second pulse selector PS2 is high level, the switch S is turned on, and the capacitor current i _C rises; When i _C rises to the first peak capacitor current reference value I _ref1 , the output signal VH of the first pulse generator PGH changes from high level to low level, and at the same time, the output signal SS of the first pulse selector PS1 changes from high level to low level. level to low level, the switching cycle ends; during this switching cycle, the second controlled constant time timer CT2 does not count, and the output signal VL of the second pulse generator PGL remains low level; if the output voltage V _o is greater than the output voltage reference value V _ref , then the output signal SS of the first pulse selector PS1 is low level, SS1 is high level, the second constant time timer CT2 starts timing, and the output signal of the second pulse generator PGL VL is low level, the output signal V _p of the second pulse selector PS2 is low level, the switch S is turned off, the capacitor current i _C decreases, and after a fixed time interval _TL , the second controlled constant time timer The output signal LL of CT2 changes to high level, the output signal VL of the second pulse generator PGL changes from low level to high level, the switch S is turned on, and the capacitor current i _C rises; when i _C rises to the second peak value When the capacitor current reference value I _ref2 , VL changes from high level to low level, SS changes from low level to high level, and the switching cycle ends; during this switching cycle, the first controlled constant time timer CT1 does not Timing, the output signal VH of the first pulse generator PGH remains low level. In a switching cycle, when the signal SS is high level, the duration of the high and low levels of the output signal _VP of the second pulse selector PS2 is consistent with the pulse signal VH, otherwise it is consistent with the pulse signal VL.

The first pulse selector PS1 completes the generation and output of the signals SS, SS1: Figure 2 shows that the first comparator CMP1 compares the output voltage _Vo with the output voltage reference value V _ref . When the output voltage _{Vo is} less than the output voltage reference When the value V _ref is, the output of the first comparator CMP1 is high level, otherwise, the output of the first comparator CMP1 is low level; when the falling edge _{of VP} comes, the C terminal of the first flip-flop DFF1 inputs a falling edge , according to the working principle of the D flip-flop: the Q-terminal output signal SS of the first flip-flop DFF1 remains consistent with the state of the D-terminal input signal. The signal SS remains unchanged until the next falling edge of _VP . The first flip-flop The level of the output signal SS1 at the Q1 terminal of DFF1 is always opposite to the signal SS.

The second pulse selector PS2 completes the selection and output of the signal _VP : Figure 3 shows that when the input signal SS of the first AND gate AND1 is high level and the input signal SS1 of the second AND gate AND2 is low level, the The output signal of the first AND gate AND1 remains consistent with the input signal VH of the first AND gate AND1, the output signal of the second AND gate AND2 remains low, and the signal _VP at the output end of the OR gate OR is consistent with the output signal of the first AND gate AND1. Be consistent, that is, _VP is consistent with the signal VH; otherwise, _VP is consistent with the signal VL

The first pulse generator PGH completes the generation and output of signals VH and VH1: Figure 4 shows that when the rising edge of signal HH comes, the S terminal of the second flip-flop RSFF2 inputs a high level. According to the working principle of the RS flip-flop: The Q terminal output signal VH of the second flip-flop RSFF2 is high level; the second comparator CMP2 compares the capacitor current i _C with the first capacitor current reference signal I _ref1 . When the capacitor current i _C is higher than I _ref1 , the The output signal R1 of the second comparator CMP2 is high level, that is, the R terminal of the second flip-flop RSFF2 inputs a high level, then the Q terminal output signal VH of the second flip-flop RSFF2 changes from high level to low level. The level of the Q1 terminal output signal VH1 of the second flip-flop RSFF2 is always opposite to the signal VH.

The second pulse generator PGL completes the generation and output of the signals VL and VL1: Figure 5 shows that its working process is similar to the above-mentioned PGH, except that the S terminal of the third flip-flop RSFF3 is connected to the signal LL, and the third comparator The negative polarity terminal of CMP3 is connected to the second capacitor current reference signal I _ref2 , and the level of the Q1 terminal output signal VL1 of the third flip-flop RSFF3 is always opposite to the signal VL.

The converter TD in this example is a Buck converter.

Use PSIM simulation software to perform time domain simulation analysis on the method in this example. The results are as follows.

Figure 7 shows the output voltage signal V _o , the output voltage reference signal V _ref , the capacitor current signal i _C , the first capacitor current reference signal I _ref1 and the second capacitor current reference signal when the Buck converter of the present invention is operating in a steady state. Schematic diagram of the relationship between I _ref2 , pulse signal SS, pulse signal HH, pulse signal LL, pulse signal VH, pulse signal VL and drive signal _VP . It can be seen from the figure that there is no low-frequency oscillation phenomenon when the Buck converter using the present invention operates in the inductor current continuous conduction mode. Simulation conditions: input voltage V _in =14V, voltage reference value V _ref =6V, first capacitor current reference value I _ref1 =1.875A, second capacitor current reference value I _ref2 =2A, inductor L =10μH, capacitor C _o = 470μF (its equivalent series resistance is 1nΩ), load resistance R _o =2Ω.

Figure 8 (a) and Figure 8 (b) show the transient time domain simulation waveforms of the Buck converter using Embodiment 1 of the present invention and capacitor current PT control when the load increases (I _o = 3A → 8A), Figure 8 ( a) and Figure 8(b) correspond to Embodiment 1 of the invention and capacitor current PT control respectively. At 4ms, the load increases and the load current changes stepwise from 3A to 8A. It can be seen from Figure 8(a) and Figure 8(b) that when the present invention is adopted, the output voltage re-enters the steady state after 7 switching cycles, and the maximum voltage fluctuation during the adjustment process is 0.07V; in the steady state , the output voltage ripple is 0.02V, and the combination of pulse sequence cycle periods is always "1 high + 1 low". For the CCM Buck converter controlled by capacitor current PT, when the output branch load is loaded, the output voltage also re-enters the steady state after 7 switching cycles. However, the maximum voltage fluctuation of the output voltage during the adjustment process is 0.357V; steady state When, the output voltage ripple is 0.12V, and the combination of pulse sequence cycle periods is "3 high + 4 low".

Figure 9(a) and Figure 9(b) are the transient time domain simulation waveforms of the Buck converter using Embodiment 1 of the present invention and capacitor current PT control when the load is reduced (I _o = 8A → 3A), Figure 9 ( a) and Figure 9(b) respectively correspond to Embodiment 1 of the invention and capacitor current PT control. At 8ms, the load decreases and the load current changes stepwise from 8A to 3A. It can be seen from Figure 9(a) and Figure 9(b) that when the present invention is adopted, the output voltage re-enters the steady state after 6 switching cycles, and the maximum voltage fluctuation during the adjustment process is 0.06V; in the steady state , the output voltage ripple is 0.02V, and the combination of the pulse sequence cycle period is always "1 high + 1 low". For the CCM Buck converter controlled by capacitor current PT, when the output branch load is reduced, the output voltage re-enters the steady state after 5 switching cycles. However, the maximum voltage fluctuation of the output voltage during the adjustment process is 0.234V; steady state When, the output voltage ripple is 0.12V, and the pulse sequence cycle combination is "3 high + 4 low", and during the working process, the pulse sequence does not strictly follow the cycle combination, and there is a pulse adjustment period. The simulation conditions are consistent with Figure 8(a) and Figure 8(b).

It can be seen from Figure 8(a), Figure 8(b) and Figure 9(a), Figure 9(b) that the switching converter of the present invention has a small output voltage ripple in the steady state, and the pulse sequence cycle period combination mode Optimal; when the load changes suddenly, the change in output voltage is small. The CCM Buck converter controlled by capacitor current PT has a large output voltage ripple in the steady state. The pulse sequence cycle consists of multiple high pulses and multiple low pulses. The combination method is not optimal; when the load changes suddenly, the output The voltage changes greatly.

Embodiment 2

The signal flow chart of the method of the second embodiment of the present invention is also shown in Figure 1. The implementation is basically the same as that of the first embodiment. The difference is that the capacitor current reference value in this embodiment is the valley capacitor current reference value.

Figure 10 shows: The specific composition of the first pulse generator PGH in this example is: composed of the second comparator CMP2 and the second flip-flop RSFF2; the detected capacitor current signal i _C and the negative polarity terminal of the second comparator CMP2 connected, the first valley capacitor current reference value I _ref1 is connected to the positive polarity terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the S terminal of the second flip-flop RSFF2, and the first controlled constant time timer The output signal HH of CT1 is connected to the R terminal of the second flip-flop RSFF2.

Figure 11 shows that the working process of the second pulse generator PGL in this example is similar to the above-mentioned PGH. The difference is that: the R terminal of the third flip-flop RSFF3 is connected to the signal LL, and the positive polarity terminal of the third comparator CMP3 is connected to the signal LL. The level of the second capacitor current reference signal I _ref2 and the Q1 terminal output signal VL1 of the third flip-flop RSFF3 is always opposite to the signal VL.

Figure 12 shows a schematic diagram of the main waveforms of the Buck converter in steady state operation according to Embodiment 2 of the invention.

Embodiment 3

As shown in Figure 13, the third embodiment of the present invention is basically the same as the first embodiment, except that the converter TD controlled in this example is a Boost converter.

In addition to being used in the switching converters in the above embodiments, the present invention can also be used in various circuit topologies such as Buck-Boost converters, Flyback converters, and Forward converters.

Claims (6)

1. Capacitive current dual-frequency pulse sequence control device, characterized by: including a voltage detection circuit VS, a current detection circuit IS, a first pulse selector PS1, a second pulse selector PS2, a first controlled constant time timer CT1, The second controlled constant time timer CT2, the first pulse generator PGH, the second pulse generator PGL and the driving circuit DR; the voltage detection circuit VS is connected to the first pulse selector PS1; the first pulse selector PS1 The output signal SS is connected to the first controlled constant time timer CT1; the output signal SS1 of the first pulse selector PS1 is connected to the second controlled constant time timer CT2; the first controlled constant time timer CT1 and current detection The circuit IS is connected to the first pulse generator PGH respectively, and the output signal VH1 of the PGH is connected to the first controlled constant time timer CTI; the second controlled constant time timer CT2 and the current detection circuit IS are connected to the second pulse generator respectively. PGL is connected, the output signal VL1 of the second pulse generator PGL is connected to the second controlled constant time timer CT2; the output signal VH of the first pulse generator PGH, the output signal VL of the second pulse generator PGL, the first pulse The output signals SS and SS1 of the selector PS1 are respectively connected to the second pulse selector PS2; the second pulse selector PS2 is connected to the driving circuit DR and the first pulse selector PS1 respectively; The first pulse selector PS1 includes a first comparator CMP1 and a first flip-flop DFF1; the detected output voltage signal V _o is connected to the negative polarity terminal of the first comparator CMP1, and the output voltage reference value V _ref is connected to the first comparator CMP1. The positive polarity terminal of the comparator CMP1 is connected; the first comparator CMP1 is connected to the D terminal of the first flip-flop DFF1, and the switch pulse signal _VP is connected to the C terminal of the first flip-flop DFF1; The second pulse selector PS2 includes a first AND gate AND1, a second AND gate AND2 and an OR gate OR; the pulse signal VH generated by the first pulse generator PGH, the pulse signal SS generated by the first pulse selector and the The input terminal of an AND gate AND1 is connected; the pulse signal VL generated by the second pulse generator PGL and the pulse signal SS1 generated by the first pulse selector are connected with the input terminal of the second AND gate AND2; the first AND gate AND1, the second The output terminal of the AND gate AND2 is connected to the input terminal of the OR gate OR. 2. The capacitor current dual-frequency pulse sequence control device according to claim 1, characterized in that: the first pulse generator PGH includes a second comparator CMP2 and a second flip-flop RSFF2; the detected capacitor current signal i _C is connected to the positive terminal of the second comparator CMP2, the first peak capacitor current reference value I _ref1 is connected to the negative terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the R terminal of the second flip-flop RSFF2 connected, the output signal HH of the first controlled constant time timer CT1 is connected to the S terminal of the second flip-flop RSFF2; The second pulse generator PGL includes a third comparator CMP3 and a third flip-flop RSFF3. The detected capacitor current signal i _C is connected to the positive polarity terminal of the third comparator CMP3, and the second peak capacitor current reference signal I _ref2 is connected to the positive polarity terminal of the third comparator CMP3. The negative polarity terminal of the third comparator CMP3 is connected; the output terminal of the third comparator CMP3 is connected with the R terminal of the third flip-flop RSFF3, and the output signal LL of the second controlled constant time timer CT2 is connected with the S terminal of the third flip-flop RSFF3. end connected. 3. The capacitor current dual-frequency pulse sequence control device according to claim 1, characterized in that: the first pulse generator PGH includes a second comparator CMP2 and a second flip-flop RSFF2; the detected capacitor current signal i _C is connected to the negative polarity terminal of the second comparator CMP2, the first valley capacitor current reference value I _ref1 is connected to the positive polarity terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the S of the second flip-flop RSFF2 The output signal HH of the first controlled constant time timer CT1 is connected to the R terminal of the second flip-flop RSFF2; The second pulse generator PGL includes a third comparator CMP3 and a third flip-flop RSFF3. The detected capacitor current signal i _C is connected to the negative polarity terminal of the third comparator CMP3, and the second valley capacitor current reference signal I _ref2 Connected to the positive polarity terminal of the third comparator CMP3; the output terminal of the third comparator CMP3 is connected to the S terminal of the third flip-flop RSFF3, and the output signal LL of the second controlled constant time timer CT2 is connected to the S terminal of the third flip-flop RSFF3. The R end is connected. 4. The control method of the capacitive current dual-frequency pulse sequence control device according to any one of claims 1 to 3, characterized in that: at the beginning of each switching cycle, the output voltage is detected to obtain the signal _Vo , and the output filter capacitance is detected. current to obtain the signal i _c ; send _Vo , switch pulse signal _VP and output voltage reference value V _ref to the first pulse selector PS1 to generate pulse signals SS and SS1; connect SS and the first pulse generator PGH The generated pulse signal VH1 is sent to the first controlled constant time timer CT1 to generate the signal HH; i _C , HH and the first capacitor current reference value I _ref1 are sent to the first pulse generator PGH to generate the pulse signals VH and VH1 ; Send the pulse signal VL1 generated by SS1 and the second pulse generator PGL to the second controlled constant time timer CT2 to generate the signal LL; Send i _C , LL and the second capacitor current reference value I _ref2 to the second controlled constant time timer CT2 The pulse generator PGL generates pulse signals VL and VL1; VH, VL, SS and SS1 are sent to the second pulse selector PS2 to generate a pulse signal _VP to control the on and off of the converter switch tube. 5. The control method of the capacitor current dual-frequency pulse sequence control device according to claim 4, characterized in that: the first capacitor current reference value I _ref1 and the second capacitor current reference value I _ref2 are preset capacitor currents. The reference value is the directly set capacitor current peak value or the capacitor current peak value generated by the input or output feedback quantity and related to the input quantity or output quantity. 6. The control method of the capacitor current dual-frequency pulse sequence control device according to claim 4, characterized in that: the first capacitor current reference value I _ref1 and the second capacitor current reference value I _ref2 are preset capacitor currents. The reference value is the directly set capacitor current valley value or the capacitor current valley value generated by the input or output feedback quantity and related to the input quantity or output quantity.