CN207475427U - Capacitance current bifrequency pulse-sequence control device - Google Patents

Abstract

The utility model relates to power electronic equipment, in particular to a capacitive current dual-frequency pulse sequence control device, which completes the control of the converter switching tube by limiting the off or on time of the switching tube and the peak or valley value of the capacitive current. Control to realize the adjustment of the output branch. Compared with the traditional pulse sequence control switching converter, the utility model has the advantages of small output voltage ripple, optimal combination of pulse cycles, no low-frequency oscillation phenomenon and good load transient performance, etc., and can be used to control various switches Converters, such as: Buck converter, Boost converter, Buck-boost converter, Flyback converter, Forward converter, etc.

Description

Capacitor-current dual-frequency pulse sequence control device

technical field

The utility model relates to power electronic equipment, in particular to a capacitor current dual-frequency pulse sequence control device.

Background technique

Compared with traditional linear regulated power supplies, switching converters are widely used due to their excellent performance such as small size, light weight and high efficiency. Currently, switching converters generally use Pulse Width Modulation (Pulse Width Modulation, PWM) and Pulse Frequency Modulation (Pulse Frequency Modulation, PFM) technologies to control the output voltage. PWM modulation technology controls the output voltage by adjusting the width of the control pulse. It is a constant frequency control method and has the advantage of simple feedback control loop design, but it has low light load efficiency, slow dynamic response, and electromagnetic interference. (Electromagnetic Interference, EMI) and other serious shortcomings; PFM modulation technology controls the output voltage by changing the frequency of the control pulse, which effectively solves the problem of low light-load efficiency, but because the switching frequency changes with the input voltage or load Changes, thus increasing the design difficulty of the feedback control loop and EMI filter.

Pulse Train (PT) modulation is a modulation method completely different from PWM and PFM. It realizes the adjustment of the converter by adjusting the combination of two sets of high and low control pulses with the same frequency and different duty ratios. A nonlinear discrete modulation method. PT modulation does not require error amplifiers and corresponding compensation networks. It has the advantages of simple controller implementation and fast dynamic response to input and load changes. It has attracted widespread attention from academia and industry. When the PT control converter works in the inductor current discontinuous conduction mode (Discontinuous conduction mode, DCM), the inductor current is always zero at the beginning of a switching cycle, so the amount of energy stored in the inductor is zero, and the inductor does not affect the energy transfer process , but the load capacity of the DCM switching converter is limited, the peak value of the inductor current is high and the output voltage ripple is large. When the PT control converter works in the continuous conduction mode (Continuous conduction mode, CCM), if the inductor current is not equal at the beginning of a switching cycle, the amount of energy stored in the inductor will not be zero, and the inductor will participate in the energy transfer process . Therefore, the amount of energy stored in the inductor indirectly affects the output voltage of the PT-controlled CCM switching converter, causing the controller to adjust the output voltage with hysteresis, resulting in low-frequency oscillation and slow transient response of the switching converter.

In view of the low-frequency oscillation problem of PT-controlled CCM switching converters, scholars have proposed valley current PT control methods, capacitive current PT control methods, etc. In the steady state, the pulse sequence cycle of these control methods is composed of multiple high pulses and multiple low pulses, and the inductor current and output voltage ripple are large, which affects the steady-state performance of the converter.

Utility model content

The purpose of this utility model is to provide a control method for switching converters, so that it overcomes the technical shortcomings of the existing pulse sequence control work in the continuous conduction mode of the inductance current, and has the pulse sequence cycle in a steady state. +1 low pulse" combination mode, small steady-state ripple of inductor current and output voltage, strong stability and anti-interference ability, good load transient performance, etc., suitable for switching converters with various topologies.

The technical scheme that the utility model realizes that its utility model purpose adopts is:

Capacitor current dual-frequency pulse sequence control method, at the beginning of each switching cycle, detect the output voltage to obtain the signal V _o , detect the current of the output filter capacitor, and obtain the signal _ic ; combine V _o , the switch tube pulse signal V _P and the output The voltage reference value V _ref is sent to the first pulse selector PS1 to generate pulse signals SS and SS1; the pulse signal VH1 generated by SS and the first pulse generator PGH is sent to the first controlled constant time timer CT1 to generate signal HH ; Send i _C , HH and the first capacitor current reference value I _ref1 to the first pulse generator PGH to generate pulse signals VH and VH1; send the pulse signal VL1 generated by SS1 and the second pulse generator PGL to the second The controlled constant time timer CT2 generates signal LL; sends i _C , LL and the second capacitor current reference value I _ref2 to the second pulse generator PGL to generate pulse signals VL and VL1; sends VH, VL, SS and SS1 to input to the second pulse selector PS2 to generate a pulse signal V _P for controlling the switching on and off of the switching tube of the converter.

Further, the first capacitive current reference value I _ref1 is a preset capacitive current reference value, which is a directly set capacitive current peak value or a capacitive current peak value related to input or output generated by input and output feedback .

The second capacitive current reference value I _ref2 is a preset capacitive current reference value, which is a directly set capacitive current valley value or a capacitive current valley value related to input or output generated by input and output feedback.

The utility model also provides the capacitive current dual-frequency pulse sequence control device, including a voltage detection circuit VS, a current detection circuit IS, a first pulse selector PS1, a second pulse selector PS2, a first controlled constant time timer CT1, The second controlled constant time timer CT2, the first pulse generator PGH, the second pulse generator PGL and the drive circuit DR; the voltage detection circuit VS is connected with the first pulse selector PS1; the first pulse selector PS1 The output signal SS of the first controlled constant time timer CT1 is connected; the output signal SS1 of the first pulse selector PS1 is connected with the second controlled constant time timer CT2; the first controlled constant time timer CT1 and the current detection The circuit IS is respectively connected with the first pulse generator PGH, and the output signal VH1 of PGH is connected with the first controlled constant time timer CTI; the second controlled constant time timer CT2 and the current detection circuit IS are respectively connected with the second pulse generator PGL is connected, the output signal VL1 of the second pulse generator PGL is connected with the second controlled constant time timer CT2; the output signal VH of the first pulse generator PGH, the output signal VL of the second pulse generator PGL, the first pulse The output signals SS and SS1 of the selector PS1 are respectively connected to the second pulse selector PS2; the second pulse selector PS2 is respectively connected to the driving circuit DR and the first pulse selector PS1.

Further, the first pulse selector PS1 includes a first comparator CMP1 and a first flip-flop DFF1; the detected output voltage signal V _o is connected to the negative terminal of the first comparator CMP1, and the output voltage reference value V _ref It is connected to the positive terminal of the first comparator CMP1; the first comparator CMP1 is connected to the D terminal of the first flip-flop DFF1, and the switch tube pulse signal V _P is connected to the C terminal of the first flip-flop DFF1.

Further, the second pulse selector PS2 includes a first AND gate AND1, a second AND gate AND2 and an OR gate OR; the pulse signal VH generated by the first pulse generator PGH, the pulse signal generated by the first pulse selector SS is connected to the input terminal of the first AND gate AND1; the pulse signal VL generated by the second pulse generator PGL and the pulse signal SS1 generated by the first pulse selector are connected to the input terminal of the second AND gate AND2; the first AND gate AND1 , The output terminal of the second AND gate AND2 is connected with the input terminal of the OR gate OR.

Further, the first pulse generator PGH includes a second comparator CMP2 and a second flip-flop RSFF2; the detected capacitive current signal iC is connected to the positive terminal of the second comparator CMP2, and the first peak capacitive current reference value Iref1 is connected to the negative terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the R terminal of the second flip-flop RSFF2, and the output signal HH of the first controlled constant time timer CT1 is connected to the second flip-flop RSFF2 The S terminal is connected.

The second pulse generator PGL includes a third comparator CMP3 and a third flip-flop RSFF3, the detected capacitive current signal i _C is connected to the positive terminal of the third comparator CMP3, and the second peak capacitive current reference signal I _ref2 is connected to the positive terminal of the third comparator CMP3. The negative terminal of the third comparator CMP3 is connected; the output terminal of the third comparator CMP3 is connected with the R terminal of the third flip-flop RSFF3, the output signal LL of the second controlled constant time timer CT2 is connected with the S of the third flip-flop RSFF3 end connected.

Further, the first pulse generator PGH includes a second comparator CMP2 and a second flip-flop RSFF2; the detected capacitive current signal i _C is connected to the negative terminal of the second comparator CMP2, and the first valley capacitive current The reference value I _ref1 is connected with the positive terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected with the S terminal of the second flip-flop RSFF2, and the output signal HH of the first controlled constant time timer CT1 is connected with the second The R terminal of flip-flop RSFF2 is connected.

The second pulse generator PGL includes a third comparator CMP3 and a third flip-flop RSFF3, the detected capacitive current signal i _C is connected to the negative terminal of the third comparator CMP3, and the second valley capacitive current reference signal I _ref2 It is connected with the positive terminal of the third comparator CMP3; the output terminal of the third comparator CMP3 is connected with the S terminal of the third flip-flop RSFF3, and the output signal LL of the second controlled constant time timer CT2 is connected with the output signal of the third flip-flop RSFF3 The R terminal is connected.

The utility model has the advantages of small output voltage ripple, optimal combination of pulse cycles, no low-frequency oscillation phenomenon and good load transient performance, and can be used to control various switching converters, such as Buck converters and Boost converters , Buck-boost converter, Flyback converter, Forward converter, etc.

Compared with the prior art, the beneficial effects of the utility model are:

1. The utility model provides a simple and reliable pulse sequence control method for the continuous conduction mode switching converter, which overcomes the disadvantage of low-frequency oscillation in the traditional pulse sequence control continuous conduction mode switching converter, and has better stability and reliability. higher.

2. The pulse sequence control method provided by the utility model can quickly adjust the turn-on and turn-off of the switch tube when the load changes, and the change of the output voltage is small.

3. In the pulse sequence control method of the continuous conduction mode switching converter provided by the utility model, the combination mode of the pulse sequence cycle is always "1 high pulse + 1 low pulse", and the ripple of the inductor current and the output voltage is small.

Description of drawings

Fig. 1 is a structural block diagram of a control circuit of Embodiment 1 of the utility model.

FIG. 2 is a block diagram of the circuit structure of the first pulse selector PS1 according to Embodiment 1 of the present invention.

FIG. 3 is a block diagram of the circuit structure of the second pulse selector PS2 according to Embodiment 1 of the present invention.

FIG. 4 is a block diagram of the circuit structure of the first pulse generator PGH in Embodiment 1 of the present invention.

FIG. 5 is a block diagram of the circuit structure of the second pulse generator PGL according to Embodiment 1 of the present invention.

Fig. 6 is a block diagram of the circuit structure of Embodiment 1 of the present utility model.

FIG. 7 is a schematic diagram of main waveforms of the Buck converter in steady state operation according to Embodiment 1 of the present invention.

Fig. 8 (a) is the transient time-domain simulation waveform of the Buck converter controlled by the capacitive current PT in the first embodiment of the present invention when the load suddenly increases from 3A to 8A;

Fig. 8(b) is the transient time-domain simulation waveform of the capacitor current PT-controlled Buck converter in the first embodiment of the present invention when the load suddenly increases from 3A to 8A.

Fig. 9 (a) is the transient time domain simulation waveform of the Buck converter controlled by the capacitive current PT in the first embodiment of the present invention when the load is suddenly reduced from 8A to 3A;

Fig. 9(b) is the transient time-domain simulation waveform of the capacitor current PT-controlled Buck converter in the first embodiment of the present invention when the load suddenly decreases from 8A to 3A.

Fig. 10 is a block diagram of the circuit structure of the first pulse generator PGH in the second embodiment of the present invention.

FIG. 11 is a block diagram of the circuit structure of the second pulse generator PGL according to the second embodiment of the present invention.

Fig. 12 is a schematic diagram of main waveforms of the Buck converter in the second embodiment of the present invention when it works in a steady state.

Fig. 13 is a block diagram of the circuit structure of the third embodiment of the utility model.

Detailed ways

The utility model is described in further detail below through specific examples in conjunction with the accompanying drawings.

Embodiment one:

Fig. 1 shows, a kind of embodiment of the present utility model is: dual-frequency capacitive current pulse sequence control device, its device is mainly composed of voltage detection circuit VS, current detection circuit IS, first pulse selector PS1, first pulse selection PS2, the first controlled constant time timer CT1, the second controlled constant time timer CT2, the first pulse generator PGH, the second pulse generator PGL and the drive circuit DR; at the beginning of each switching cycle, Detect the output voltage of the output branch to obtain the signal V _o , detect the filter capacitor current of the output branch to obtain the signal _ic ; send V _o , the switch tube pulse signal V _P and the output voltage reference value V _ref to the first pulse The selector PS1 generates pulse signals SS and SS1; the pulse signal VH1 generated by SS and the first pulse generator PGH is sent to the first controlled constant time timer CT1 to generate the signal HH; the i _C , HH and the first capacitor current The reference value I _ref1 is sent to the first pulse generator PGH to generate pulse signals VH and VH1; the pulse signal VL1 generated by SS1 and the second pulse generator is sent to the second controlled constant time timer CT2 to generate signal LL; i _C , LL and the second capacitor current reference value I _ref2 are sent to the second pulse generator PGL to generate pulse signals VL and VL1; VH, VL, SS and SS1 are sent to the second pulse selector PS2 to generate the pulse signal V _P is used to control the turn-on and turn-off of the switch tube of the converter.

Fig. 2 shows that the specific composition of the first pulse selector PS1 of this example is as follows: it is composed of the first comparator CMP1 _and the first flip-flop DFF1; connected, the output voltage reference value V _ref is connected to the positive terminal of the first comparator CMP1; the output terminal of the first comparator CMP1 is connected to the D terminal of the first flip-flop DFF1, and the switch tube pulse signal V _p is connected to the first flip-flop DFF1 The C-terminus is connected.

Figure 3 shows that the specific composition of the second pulse selector PS2 in this example is as follows: it is composed of the first AND gate AND1, the second AND gate AND2 and the OR gate OR; the pulse signal VH generated by the first pulse generator PGH, the second The pulse signal SS generated by a pulse selector is connected to the input terminal of the first AND gate AND1; the pulse signal VL generated by the second pulse generator PGL, the pulse signal SS1 generated by the first pulse selector and the input of the second AND gate AND2 The output terminal of the first AND gate AND1, the output terminal of the second AND gate AND2 are connected with the input terminal of the OR gate OR.

Fig. 4 shows that the specific composition of the first pulse generator PGH of this example is: it is made up of the second comparator _CMP2 and the second flip-flop RSFF2; connected, the first peak capacitance current reference value I _ref1 is connected to the negative terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the R terminal of the second flip-flop RSFF2, and the first controlled constant time timer CT1 The output signal HH of is connected to the S terminal of the second flip-flop RSFF2.

Fig. 5 shows that the specific composition of the second pulse generator PGL of this example is: it is made up of the third comparator _CMP3 and the third flip-flop RSFF3; connected, the second peak capacitor current reference value I _ref2 is connected with the negative terminal of the third comparator CMP3; the output terminal of the third comparator CMP3 is connected with the R terminal of the third flip-flop RSFF3, and the second controlled constant time timer CT2 The output signal LL of is connected to the S terminal of the third flip-flop RSFF3.

This example adopts the device in Figure 6, which can realize the above-mentioned control method conveniently and quickly. FIG. 6 shows that the dual-frequency capacitive current pulse sequence control device in this example is composed of a converter TD and a switching tube S control device.

Its work process and principle of the device of this example are:

The working process and principle of the control device adopting dual-frequency capacitive current pulse sequence control are as follows: Figure 1-7 shows that at the beginning of the switching cycle, the sampled output voltage V _o is compared with the output voltage reference value V _ref , if the output voltage V _o is less than the output voltage reference value V _ref , the output signal SS of the first pulse selector PS1 is high level, the first controlled constant time timer CT1 starts counting, and at the same time the output signal VH of the first pulse generator PGH is low Level, the output signal V _p of the second pulse selector PS2 is low level, the switch tube S is turned off, and the capacitor current i _C drops; after a fixed time interval T _H , the first controlled constant time timer CT1 outputs the signal HH becomes high level, the output signal VH of the first pulse generator PGH is high level, the output signal V _p of the second pulse selector PS2 is high level, the switch tube S is turned on, and the capacitive current i _C rises; When i _C rises to the first peak capacitor current reference value I _ref1 , the output signal VH of the first pulse generator PGH changes from high level to low level, and at the same time the output signal SS of the first pulse selector PS1 changes from high level to level becomes low, and the switching cycle ends; in this switching cycle, the second controlled constant time timer CT2 does not count, and the output signal VL of the second pulse generator PGL remains low; if the output voltage V _o is greater than the output voltage reference value V _ref , the output signal SS of the first pulse selector PS1 is low level, SS1 is high level, the second constant time timer CT2 starts timing, and the output signal of the second pulse generator PGL VL is low level, the output signal V _p of the second pulse selector PS2 is low level, the switch tube S is turned off, the capacitor current i _C drops, after a fixed time interval T _L , the second controlled constant time timer The output signal LL of CT2 becomes high level, the output signal VL of the second pulse generator PGL changes from low level to high level, the switch tube S is turned on, and the capacitor current i _C rises; when i _C rises to the second peak value When the capacitor current reference value I _ref2 , VL changes from high level to low level, SS changes from low level to high level, and the switching cycle ends; in this switching cycle, the first controlled constant-time timer CT1 does not Timing, the output signal VH of the first pulse generator PGH remains low. In one switching cycle, when the signal SS is at a high level, the duration of the high and low levels of the output signal _VP of the second pulse selector PS2 is consistent with the pulse signal VH, otherwise it is consistent with the pulse signal VL.

The first pulse selector PS1 completes the generation and output of signals SS and SS1: Fig. 2 shows that the first comparator CMP1 compares the output voltage V _o with the output voltage reference value V _ref , when the output voltage V _o is less than the output voltage reference When V _ref is high, the output of the first comparator CMP1 is high level, otherwise, the output of the first comparator CMP1 is low level; when the falling edge of V _P comes, the C terminal of the first flip-flop DFF1 inputs a falling edge , according to the working principle of the D flip-flop: the output signal SS of the Q terminal of the first flip-flop DFF1 is consistent with the state of the input signal of the D terminal, and the signal SS remains unchanged until the next falling edge of V _P comes, the first flip-flop The level of the output signal SS1 at the Q1 terminal of DFF1 is always opposite to that of the signal SS.

The second pulse selector PS2 completes the selection and output of the signal _VP : Fig. 3 shows that when the input signal SS of the first AND gate AND1 is high level and the input signal SS1 of the second AND gate AND2 is low level, the second The output signal of an AND gate AND1 is consistent with the input signal VH of the first AND gate AND1, the output signal of the second AND gate AND2 is kept low, and the signal _VP at the output end of the OR gate OR is consistent with the output signal of the first AND gate AND1. Keep consistent, that is, _VP is consistent with signal VH; otherwise, _VP is consistent with signal VL

The first pulse generator PGH completes the generation and output of the signals VH and VH1: Figure 4 shows that when the rising edge of the signal HH comes, the S terminal of the second flip-flop RSFF2 inputs a high level, according to the working principle of the RS flip-flop: The output signal VH of the Q terminal of the second flip-flop RSFF2 is high level; the second comparator CMP2 compares the capacitor current i _C with the first capacitor current reference signal I _ref1 , when the capacitor current i _C is higher than I _ref1 , the second The output signal R1 of the second comparator CMP2 is high level, that is, the R terminal of the second flip-flop RSFF2 inputs a high level, then the output signal VH of the Q terminal of the second flip-flop RSFF2 changes from high level to low level, and the second The level of the output signal VH1 of the Q1 terminal of the second flip-flop RSFF2 is always opposite to that of the signal VH.

The second pulse generator PGL completes the generation and output of signals VL and VL1: as shown in Figure 5, its working process is similar to the above-mentioned PGH, the difference is: the S terminal of the third flip-flop RSFF3 is connected to the signal LL, and the third comparator The negative terminal of CMP3 is connected to the second capacitor current reference signal I _ref2 , and the level of the output signal VL1 at the Q1 terminal of the third flip-flop RSFF3 is always opposite to that of the signal VL.

The converter TD in this example is a Buck converter.

Use PSIM simulation software to carry on time domain simulation analysis to the method of this example, the result is as follows.

Fig. 7 shows the output voltage signal V _o , the output voltage reference signal V _ref , the capacitance current signal i _C , the first capacitance current reference signal I _ref1 , and the second capacitance current reference A schematic diagram of the relationship among the signal I _ref2 , the pulse signal SS, the pulse signal HH, the pulse signal LL, the pulse signal VH, the pulse signal VL and the driving signal _VP . It can be seen from the figure that there is no low-frequency oscillation phenomenon in the Buck converter of the present invention working in the continuous conduction mode of the inductor current. Simulation conditions: input voltage V _in =14V, voltage reference value V _ref =6V, first capacitor current reference value I _ref1 =1.875A, second capacitor current reference value I _ref2 =2A, inductance L=10μH, capacitance C _o = 470μF (its equivalent series resistance is 1nΩ), load resistance R _o =2Ω.

Fig. 8(a) and Fig. 8(b) are the transient time-domain simulation waveforms of the Buck converter adopting the first embodiment and capacitive current PT control when the load increases (I _o = 3A → 8A), Fig. 8(a) , FIG. 8(b) respectively correspond to the first embodiment of the utility model and the capacitive current PT control. At 4ms, the load increases, and the load current changes step by step from 3A to 8A. It can be seen from Fig. 8(a) and Fig. 8(b): when the utility model is adopted, the output voltage re-enters the steady state after 7 switching cycles, and the maximum voltage fluctuation in the adjustment process is 0.07V; the steady state , the output voltage ripple is 0.02V, and the combination of the pulse sequence cycle is always "1 high + 1 low". In the CCM Buck converter controlled by capacitor current PT, when the output branch load is loaded, the output voltage also enters the steady state after 7 switching cycles, but the maximum voltage fluctuation of the output voltage during the adjustment process is 0.357V; the steady state , the output voltage ripple is 0.12V, and the combination of the pulse sequence cycle is "3 high + 4 low".

Fig. 9(a) and Fig. 9(b) are the transient time-domain simulation waveforms of the buck converter adopting the first embodiment of the present invention and capacitive current PT control when the load decreases (I _o = 8A → 3A), Fig. 9 (a) and FIG. 9(b) respectively correspond to Embodiment 1 of the utility model and capacitive current PT control. At 8ms, the load decreases, and the load current changes stepwise from 8A to 3A. It can be seen from Fig. 9(a) and Fig. 9(b): when the utility model is adopted, the output voltage re-enters the steady state after 6 switching cycles, and the maximum voltage fluctuation in the adjustment process is 0.06V; the steady state , the output voltage ripple is 0.02V, and the combination of the pulse sequence cycle is always "1 high + 1 low". In the CCM Buck converter controlled by capacitor current PT, when the output branch load is shedding, the output voltage re-enters the steady state after 5 switching cycles, but the maximum voltage fluctuation of the output voltage during the adjustment process is 0.234V; the steady state , the output voltage ripple is 0.12V, and the combination of the pulse sequence cycle is "3 high + 4 low", and the pulse sequence does not work strictly according to the combination of the cycle during the working process, and there is a pulse adjustment cycle. The simulation conditions are consistent with those shown in Figure 8(a) and Figure 8(b).

It can be seen from Fig. 8(a), Fig. 8(b) and Fig. 9(a), Fig. 9(b), the output voltage ripple of the switching converter of the present invention is small in the steady state, and the combination of pulse train cycle period The mode is optimal; when the load changes suddenly, the output voltage changes little. The output voltage ripple of the CCM Buck converter controlled by capacitor current PT is large in the steady state, and the pulse sequence cycle is composed of multiple high pulses and multiple low pulses, and the combination method is not optimal; when the load changes suddenly, the output The amount of change in voltage is large.

Embodiment two

The signal flow chart of the second embodiment of the present invention is also shown in FIG. 1 , the implementation is basically the same as that of the first embodiment, the difference is that the reference value of the capacitive current in this embodiment is the valley value capacitive current reference value.

Fig. 10 shows: the specific composition of the first pulse generator PGH of this example is: by the second comparator _CMP2 and the second flip-flop RSFF2; connected, the first valley capacitor current reference value I _ref1 is connected to the positive terminal of the second comparator CMP2; the output terminal of the second comparator CMP2 is connected to the S terminal of the second flip-flop RSFF2, and the first controlled constant time timer The output signal HH of CT1 is connected to the R terminal of the second flip-flop RSFF2.

Figure 11 shows that the working process of the second pulse generator PGL in this example is similar to the above-mentioned PGH, the difference is that: the R terminal of the third flip-flop RSFF3 is connected to the signal LL, and the positive polarity terminal of the third comparator CMP3 is connected to the first For the second capacitor current reference signal I _ref2 , the level of the output signal VL1 at the Q1 terminal of the third flip-flop RSFF3 is always opposite to that of the signal VL.

FIG. 12 shows a schematic diagram of the main waveforms of the Buck converter in the second embodiment of the utility model when it works in a steady state.

Embodiment Three

As shown in Fig. 13, Embodiment 3 of the present utility model is basically the same as Embodiment 1, except that the converter TD controlled in this example is a Boost converter.

The utility model can be used in various circuit topologies such as Buck-Boost converter, Flyback converter, Forward converter, etc. besides the switching converter in the above embodiments.

Claims (5)

1. capacitance current bifrequency pulse-sequence control device, it is characterised in that：Including voltage detecting circuit VS, current detecting electricity Road IS, the first pulse selector PS1, the second pulse selector PS2, the first controlled constant time timer CT1, the second controlled perseverance Fix time timer CT2, the first pulse generator PGH, the second pulse generator PGL and driving circuit DR；The voltage inspection Slowdown monitoring circuit VS is connected with the first pulse selector PS1；When the output signal SS and the first controlled constant of the first pulse selector PS1 Between timer CT1 be connected；The output signal SS1 of first pulse selector PS1 and the second controlled constant time timer CT2 phases Even；First controlled constant time timer CT1 and current detection circuit IS is connected respectively with the first pulse generator PGH, PGH's Output signal VH1 is connected with the first controlled constant time timer CTI；Second controlled constant time timer CT2 and electric current inspection Slowdown monitoring circuit IS is connected respectively with the second pulse generator PGL, and the output signal VL1 of the second pulse generator PGL and second is controlled Time constant timer CT2 is connected；The output letter of the output signal VH of first pulse generator PGH, the second pulse generator PGL Number VL, the first pulse selector PS1 output signal SS, SS1 be connected respectively with the second pulse selector PS2；Second pulse is selected Device PS2 is selected respectively with driving circuit DR, the first pulse selector PS1 to be connected.

2. capacitance current bifrequency pulse-sequence control device according to claim 1, it is characterised in that：Described first Pulse selector PS1 includes first comparator CMP1 and the first trigger DFF1；The output voltage signal V detected_oWith first Comparator CMP1 negative polarity end is connected, output voltage a reference value V_refIt is connected with first comparator CMP1 positive ends；First compares Device CMP1 is connected with the D ends of the first trigger DFF1, switching tube pulse signal V_PIt is connected with the C-terminal of the first trigger DFF1.

3. capacitance current bifrequency pulse-sequence control device according to claim 1, it is characterised in that：Described second Pulse selector PS2 includes first and door AND1, second and door AND2 and/or door OR；The arteries and veins that first pulse generator PGH is generated Rush signal VH, the pulse signal SS that the first pulse selector generates is connected with first with the input terminal of door AND1；Second pulse is produced The input terminal of pulse signal SS1 and second and door AND2 that pulse signal VL, the first pulse selector that raw device PGL is generated generate It is connected；First with the output terminal of door AND1, second and door AND2 with or the input terminal of door OR be connected.

4. capacitance current bifrequency pulse-sequence control device according to claim 1, it is characterised in that：Described first Pulse generator PGH includes the second comparator CMP2 and the second trigger RSFF2；The capacitance current signal i detected_CWith second Comparator CMP2 positive ends are connected, the first peak capacitor current reference value I_ref1With the second comparator CMP2 negative polarity end phase Even；The output terminal of second comparator CMP2 is connected with the R ends of the second trigger RSFF2, the first controlled constant time timer CT1 Output signal HH be connected with the S ends of the second trigger RSFF2；

The second pulse generator PGL includes third comparator CMP3 and third trigger RSFF3, the capacitance current detected Signal i_CIt is connected with third comparator CMP3 positive ends, the second peak capacitor current reference signal I_ref2With third comparator CMP3 negative polarity end is connected；The output terminal of third comparator CMP3 is connected with the R ends of third trigger RSFF3, the second controlled perseverance The output signal LL of timer CT2 of fixing time is connected with the S ends of third trigger RSFF3.

5. capacitance current bifrequency pulse-sequence control device according to claim 1, it is characterised in that：Described first Pulse generator PGH includes the second comparator CMP2 and the second trigger RSFF2；The capacitance current signal i detected_CWith second Comparator CMP2 negative polarity end is connected, the first terminal valley point capacitance current reference value I_ref1With the second comparator CMP2 positive ends phases Even；The output terminal of second comparator CMP2 is connected with the S ends of the second trigger RSFF2, the first controlled constant time timer CT1 Output signal HH be connected with the R ends of the second trigger RSFF2；

The second pulse generator PGL includes third comparator CMP3 and third trigger RSFF3, the capacitance current detected Signal i_CIt is connected with third comparator CMP3 negative polarity end, the second terminal valley point capacitance current reference signal I_ref2With third comparator CMP3 positive ends are connected；The output terminal of third comparator CMP3 is connected with the S ends of third trigger RSFF3, the second controlled perseverance The output signal LL of timer CT2 of fixing time is connected with the R ends of third trigger RSFF3.