CN106253666B - Single-inductance double-output switch converters method for controlling frequency conversion and its control device - Google Patents

Abstract

The invention discloses a kind of single-inductance double-output switch converters method for controlling frequency conversion and its control devices, with reference to output voltage and inductive current information, switch converters main switch is controlled using conversion method, inductive current information is used as slope compensation, and ensureing being capable of steady operation when output capacitance equivalent series resistance is smaller；By the way that in each switch periods, the turn-off time of fixed main switch carrys out the turn-on and turn-off of indirect control continued flow switch pipe, realizes the dynamic afterflow of inductive current, so as to fulfill the separately adjustable of each output branch.Hybrid conductive pattern single-inductance double-output switch converters using the present invention have the advantages that stability is good, and the cross influence between output branch is small, and input, load transient response speed are fast, efficient.

Description

Single-inductance dual-output switching converter frequency conversion control method and control device

technical field

The invention relates to a control method and a device for a multi-channel output switch converter, belonging to the field of power electronic equipment, and in particular to a frequency conversion control method and a control device for a single-inductance double-output switch converter.

Background technique

The development of portable electronic products has put forward higher and higher requirements for multi-voltage output switching power supplies, making multi-output switching converters a focus of attention. Traditional multi-output switching converters have many magnetic components and are bulky, while single-inductor multi-output switching converters have the advantages of small system size, low cost, and independent adjustment of output branches. They are widely used in tablet computers, portable Information equipment, LED drive and other fields.

Similar to the single-output switching converter, the single-inductor dual-output switching converter can work in the inductor current continuous conduction mode (continuous conduction mode, CCM), critical conduction mode (boundary conduction mode, BCM) and intermittent conduction mode by selecting different circuit parameters. Conduction mode (discontinuous conduction mode, DCM) and pseudo-continuous conduction mode (pseudo-continuous conduction mode, PCCM).

The single-inductor dual-output switching converter has its own advantages and disadvantages in the four operating modes. Among them, the CCM-CCM single-inductor dual-output switching converter has the advantages of strong load capacity and small output voltage ripple, but the difference between different output branches There is cross-effect; DCM-DCM single-inductance dual-output switching converter can avoid cross-effect between output branches, but it has large current ripple and EMI noise in high-power occasions, and is only suitable for low-power occasions. Narrow; PCCM-PCCM single-inductance dual-output switching converter basically does not have cross-effects between the output branches, and can improve the load capacity of the converter by increasing the freewheeling reference value, but due to the addition of the freewheeling switch tube, reduce the efficiency of the converter. All the output branches of the above-mentioned single-inductance dual-output switching converter work in the same conduction mode, however, when the loads of the output branches vary greatly, the output branch with a lighter load has the characteristics of large ripple and low efficiency; and The requirements of each output branch of a single-inductor dual-output switching converter may be different. Therefore, different output branches can select corresponding working modes according to needs, that is, adopt a mixed conduction mode to improve the overall performance of the single-inductor dual-output switching converter.

The control technology of the switching converter greatly affects the performance of the switching power supply. According to the realization of the duty cycle, it can be divided into two categories: constant frequency control and variable frequency control. Constant frequency control means that the switching cycle is constant, and the output voltage is adjusted by adjusting the conduction time of the power device within a switching cycle; variable frequency control adjusts the output voltage by changing the switching frequency, such as constant on-time control and constant off-time control and hysteresis control. Compared with constant frequency control, variable frequency control has the advantages of good transient performance and high light load efficiency. On the other hand, the control of the freewheeling switching tube also has a great influence on the characteristics of the PCCM switching converter. The freewheeling control of the traditional PCCM switching converter adopts the constant-reference-current control (constant-reference-current, CRC) method, and the efficiency of the converter under this control method is low under light load conditions. In order to improve the efficiency of the converter, the freewheeling current value can be adjusted under different load conditions.

Contents of the invention

The purpose of the present invention is to provide a control method for a mixed conduction mode single-inductance dual-output switching converter, so that it can overcome the technical shortcomings of the existing single-inductance dual-output switching converter, and has good stability and transient performance, relatively The invention has small cross influence and high converter efficiency, and can be applied to single-inductance dual-output switching converters of various topological structures.

The technical scheme adopted in the present invention is:

The frequency conversion control method of the single-inductance dual-output switching converter, the main switching tube adopts the frequency conversion control of the output voltage combined with the inductor current, and realizes the dynamic freewheeling of the inductor current by fixing the off time of the main switching tube in each switching cycle; During the switching cycle, detect the inductor current to obtain the signal I _L , detect the output voltages of the two output branches to obtain the signals V _oa and V _ob ; send V _oa and the voltage reference value V _ref1 to the first error amplifier EA1 to generate the signal V _e1 , send V _ob and voltage reference value V _ref2 to the second error amplifier EA2 to generate signal V _e2 ; send _IL to the first pulse signal generator PGS to generate signal SS; send _IL , V _oa , V _ob , V _e1 and V _e2 , as well as V _pa and V _pb are sent to the second pulse signal generator PGR to generate signals RR and V _b ; connect the Q1 end of the first flip-flop RS1 to the input end of the first on-timer TON1, Then send the output signal V _ton1 and the signal SS of the first on-timer TON1 to the first flip-flop RS1 to generate pulse signals V _pa and V _pb to control the switching on and off of the switch tube of the converter branch; The signal V _ton1 and the signal V _pb are sent to the second flip-flop RS2 to generate the pulse signal V _p1 through the signal and signal RR generated by the first OR gate OR1 to control the on and off of the main switching tube of the converter; the signal V _b The signal V _pa is generated through the second OR gate OR2 to generate the signal V _or ; the signal V _{or is} generated through the second conduction timer TON2 to generate the signal V _ton2 ; the signal V _p1 is generated through the NOT gate NOT and the signal V _ton2 is generated through the AND gate AND The pulse signal V _p2 is used for the converter to control the turn-on and turn-off of the freewheel switch.

The control device for the frequency conversion control method of the single-inductance dual-output switching converter includes a first voltage detection circuit VS1, a second voltage detection circuit VS2, a current detection circuit IS, a first error amplifier EA1, a second error amplifier EA2, a first pulse Signal generator PGS, second pulse signal generator PGR, first flip-flop RS1, second flip-flop RS2, first OR gate OR1, second OR gate OR2, first conduction timer TON1, second conduction timing device TON2, NOT gate, AND gate AND, first drive circuit DR1, second drive circuit DR2, third drive circuit DR3 and fourth drive circuit DR4; the first voltage detection circuit VS1 and the first error amplifier EA1 connected, the second voltage detection circuit VS2 is connected with the second error amplifier EA2; the Q1 terminal of the current detection circuit IS and the first flip-flop is respectively connected with the first pulse signal generator PGS; the first voltage detection circuit VS1, the second voltage detection circuit The circuit VS2, the first error amplifier EA1, the second error amplifier EA2, the current detection circuit IS, the Q1 terminal and the Q terminal of the first flip-flop RS1 are respectively connected with the second pulse signal generator PGR; the first pulse signal generator PGS The SS end is connected to the S end of the first flip-flop RS1; the Q1 end of the first flip-flop RS1 is connected to the first on-timer TON1; the output end of the first on-timer TON1 is connected to the R end of the first flip-flop RS1 connected; the output terminal of the first on-timer TON1 and the Q terminal of the first flip-flop RS1 are respectively connected with the first OR gate OR1, and the output terminal of the first OR gate OR1 is connected with the S terminal of the second flip-flop RS2; The RR end of the second pulse signal generator PGR is connected with the R end of the second flip-flop RS2; the V _b output end of the second pulse signal generator PGR and the Q1 end of the first flip-flop RS1 are connected with the second OR gate OR2 respectively; The output terminal of the second OR gate OR2 is connected with the second conduction timer TON2; the Q terminal of the second flip-flop RS2 is connected with the NOT gate NOT; the output terminals of the NOT gate and the second OR gate OR2 are respectively connected with the AND gate AND The Q end of the first flip-flop RS1 is connected to the first drive circuit DR1, the Q1 end of the first flip-flop RS1 is connected to the second drive circuit DR2, the Q end of the second flip-flop RS2 is connected to the third drive circuit DR3, and the AND gate AND The output terminal is connected to the fourth driving circuit DR4.

The first pulse signal generator PGS includes a multiplier MULT, a sample-and-hold device S/H and a first comparator CMP1; the Q1 terminal of the current detection circuit IS and the first flip-flop RS1 is connected to the multiplier MULT; the current detection The circuit IS is connected to the sample-and-hold device S/H; the outputs of the multiplier MULT and the sample-and-hold device S/H are respectively connected to the first comparator CMP1.

The second pulse signal generator PGR includes a first adder ADD1, a second adder ADD2, a second comparator CMP2, a third comparator CMP3, a first NAND gate NAND1, a second NAND gate NAND2, a second Three NAND gates NAND3; the output terminal of the first voltage detection circuit VS1 and the output terminal of the current detection circuit IS are respectively connected to the first adder ADD1, and the output signal V _oa of the first voltage detection circuit VS1 and the output signal of the current detection circuit IS The output signal I _L is multiplied by the coefficient k1 and sent to the first adder ADD1; the output terminal of the second voltage detection circuit VS2 is connected to the second adder ADD2, and the output signal V _ob and signal I _L of the second voltage detection circuit VS2 are After being multiplied by the coefficient k2, it is sent to the second adder ADD2; the output terminals of the first error amplifier EA1 and the first adder ADD1 are connected with the second comparator CMP2, and the output terminals of the second error amplifier EA2 and the second adder ADD2 are respectively It is connected with the third comparator CMP3; the output terminal of the second comparator CMP2 and the Q1 terminal of the first flip-flop RS1 are respectively connected with the first NAND gate NAND1; the output terminal of the third comparator CMP3 is connected with the Q1 terminal of the first flip-flop RS1 The terminals are respectively connected to the second NAND gate NAND2; the first NAND gate NAND1 and the second NAND gate NAND2 are respectively connected to the third NAND gate NAND3, the output signal of the second NAND gate NAND2 is V _b , and the third NAND gate NAND2 The output signal of gate NAND3 is RR.

Compared with prior art, the beneficial effect of the present invention is:

One, compared with the PCCM-PCCM single-inductance dual-output switching converter with the main switching tube adopting voltage type control and the freewheeling switching tube adopting CRC control (referred to as V-CRC control), the single-inductance dual-output switching converter of the present invention When the input voltage changes, it can quickly adjust the turn-on and turn-off of the main switch tube and the branch switch tube, the output voltage overshoot is small, the adjustment time is short, and the input transient performance is good.

Two, compared with the PCCM-PCCM inductance dual output switching converter controlled by V-CRC, the single inductance dual output switching converter of the present invention has a fast transient response speed when the load changes, and the overshoot of the output voltage is small, The cross influence between branches is small.

3. Compared with the PCCM-PCCM inductance dual output switching converter controlled by V-CRC, the present invention indirectly controls the turn-on and turn-off of the freewheeling switch tube by fixing the off time of the main switch tube in each switching cycle , the dynamic freewheeling of the inductor current is realized, and the light-load efficiency of the converter is improved.

Description of drawings

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 is a block diagram of a circuit structure of a control method according to an embodiment of the present invention.

FIG. 2 is a block diagram of the circuit structure of the first pulse signal generator PGS according to the first embodiment of the present invention.

FIG. 3 is a block diagram of the circuit structure of the second pulse signal generator PGR according to the first embodiment of the present invention.

FIG. 4 is a block diagram of the circuit structure of Embodiment 1 of the present invention.

FIG. 5 is a schematic diagram of main waveforms of the mixed-mode single-inductor dual-output switching converter in a steady state according to Embodiment 1 of the present invention.

FIG. 6 is a transient time-domain simulation waveform of the converter TD and the PCCM-PCCM converter controlled by V-CRC in the first embodiment of the present invention when the input voltage changes suddenly.

FIG. 7 is a transient time-domain simulation waveform diagram of the output voltage of the converter TD and the PCCM-PCCM converter controlled by V-CRC when the load of branch a changes suddenly.

FIG. 8 is a transient time-domain simulation waveform diagram of the output voltage of the converter TD and the PCCM-PCCM converter controlled by V-CRC when the load of the b branch changes suddenly.

Fig. 9(a) is a graph of the efficiency of the PCCM-PCCM converter controlled by the converter TD and V-CRC of the present invention when the load of the a output branch changes.

Fig. 9(b) is a graph of the efficiency of the PCCM-PCCM converter controlled by the converter TD and V-CRC of the present invention when the load of the b output branch changes.

FIG. 10 is a transient time-domain simulation waveform diagram of the output voltage when the branch load changes suddenly after the circuit parameters of the converter TD controlled by Embodiment 1 of the present invention are changed.

FIG. 11 is a block diagram of the circuit structure of Embodiment 2 of the present invention.

Detailed ways

The present invention will be further described in detail through specific examples and in conjunction with the accompanying drawings.

Embodiment one

Figure 1 shows that a specific embodiment of the present invention is: a mixed conduction mode single-inductance dual-output switching converter frequency conversion control device, mainly composed of a first voltage detection circuit VS1, a second voltage detection circuit VS2, a current detection circuit IS, The first error amplifier EA1, the second error amplifier EA2, the first pulse signal generator PGS, the second pulse signal generator PGR, the first flip-flop RS1, the second flip-flop RS2, the first OR gate OR1, the second OR gate OR2, the first on-timer TON1, the second on-timer TON2, the NOT gate, the AND gate AND, the first drive circuit DR1, the second drive circuit DR2, the third drive circuit DR3 and the fourth drive circuit DR4 ;In each switching cycle, detect the inductor current to obtain the signal I _L , detect the output voltages of the two output branches to obtain the signals V _oa and V _ob ; send V _oa and the voltage reference value V _ref1 to the first error amplifier EA1 generates signal V _e1 , sends V _ob and voltage reference value V _ref2 to the second error amplifier EA2 to generate signal V _e2 ; sends _IL to first pulse signal generator PGS to generate signal SS; sends _IL , V _oa , V _ob , V _e1 and V _e2 are sent to the second pulse signal generator PGR to generate signals RR and V _b ; the output signal V _ton1 and signal SS of the first on-timer TON1 are sent to the first flip-flop RS1 to generate pulses The signals V _pa and V _pb are used to control the on and off of the switch tube of the converter branch; the signal V _ton1 and the signal V _pb are sent to the second flip-flop RS2 through the signal and the signal RR generated by the first OR gate OR1 Generate pulse signal V _p1 to control the turn-on and turn-off of the main switching tube of the converter; signal V _b and signal V _pa pass through the second OR gate OR2 to generate signal V _or ; signal V _or passes through the second conduction timer TON2 The signal V _ton2 is generated; the signal V _ton2 and the signal V _p1 are generated through the NOT gate NOT to generate the pulse signal V _p2 through the AND gate AND, which is used for the converter to control the turn-on and turn-off of the freewheeling switch tube.

Figure 2 shows that the specific composition of the first pulse generator PGS in this example is as follows: it is composed of a multiplier MULT, a sample-and-hold device S/H and a first comparator CMP1; the output terminal of the current detection circuit IS, the a output branch The switch tube control signal V _pa is connected to the input terminal of the multiplier MULT; the output terminal of the multiplier MULT is connected to the negative polarity terminal of the first comparator CMP1; the inductor current signal I _L is connected to the first comparator CMP1 by the sample holder S/H connected to the positive terminal.

Fig. 3 shows that the specific composition of the second pulse generator PGR of this example is: by the first adder ADD1, the second adder ADD2, the second comparator CMP2, the third comparator CMP3, the first NAND gate NAND1 , the second NAND gate NAND2, and the third NAND gate NAND3; the output signal V _oa of the first voltage detection circuit VS1 and the output signal I _L of the current detection circuit IS are multiplied by the coefficient k1 and sent to the first adder ADD1 ; The output signal V _ob and the signal _IL of the second voltage detection circuit VS2 are multiplied by the coefficient k2 and then sent to the second adder ADD2; the output end of the first adder ADD1 is connected to the positive polarity end of the second comparator CMP2, The output end of an error amplifier EA1 is connected to the negative polarity end of the second comparator CMP2; the output end of the second adder ADD2 is connected to the positive polarity end of the third comparator CMP3, and the output end of the second error amplifier EA2 is connected to the third comparator The negative terminal of CMP3; the output terminal of the second comparator CMP2 and the switching tube control signal V _pa of the a output branch are connected to the first NAND gate NAND1; the output terminal of the third comparator CMP3 and the switching tube of the b output branch The control signal V _pb is connected to the second NAND gate NAND2; the output ends of the first NAND gate NAND1 and the second NAND gate NAND2 are connected to the third NAND gate NAND3.

This example adopts the device in Figure 4, which can realize the above-mentioned control method conveniently and quickly. Figure 4 shows that the frequency conversion control device of the mixed conduction mode single-inductance dual-output switching converter in this example consists of the switching converter TD and the main switching tube S ₁ , the branch switching tubes S _a and S _b , and the freewheeling switching tube S ₂ Composition of the control device.

Its work process and principle of the device of this example are:

The control device adopts the working process and principle of the frequency conversion control of the single-inductance dual-output switching converter in the mixed conduction mode: as shown in Figure 4 and Figure 5, when the inductance current signal I _L and the switching tube control signal V _pa of the a output branch When the product signal drops to the signal obtained by the inductance current I _L through the sample-and-hold device S/H, the output signal SS of the first pulse signal generator PGS is at a high level, that is, the S terminal of the first flip-flop RS1 inputs a high level, and the first The Q terminal control pulse signal V _pb of trigger RS1 is high level, the Q1 terminal control pulse signal V _pa is low level, the converter branch switch S _b is turned on, the b branch works, and the first conduction timing The timer TON1 starts timing; the output terminal of the first OR gate OR1 is at a high level, that is, the S terminal of the second flip-flop RS2 inputs a high level, the pulse signal V _p1 of the Q terminal of the second flip-flop RS2 is at a high level, and the main The switch tube S ₁ is turned on, the freewheeling switch tube S ₂ is turned off, the inductor current _IL rises, and the output voltage V _ob rises; when the superimposed signal of the output voltage V _ob and the inductor current _IL multiplied by k2 rises to the control signal V _e2 , the output signal V _b of the second pulse signal generator PGR is high level, the output signal RR is high level, the second on-timer TON2 starts timing, and the input signal of the R terminal of the second flip-flop RS2 is high level level, the Q terminal pulse signal V _p1 of the second flip-flop RS2 is low level, S ₁ is disconnected, the inductor current I _L drops, and the output voltage V _ob drops; after the switch tube S1 is turned off for a fixed time TOFF, the second conduction The signal V _ton2 at the output terminal of the timer TON2 is at a high level, and the signal V _p1 is still at a low level at this time, then the control pulse signal V _p2 at the output terminal of the AND gate AND is at a high level, and the freewheeling switch _S2 is turned on; until The timing of the first on-timer TON1 ends, the signal V _ton1 is at a high level, the R terminal of the first flip-flop RS1 inputs a high level, and the Q1 terminal of the first flip-flop RS1 controls the pulse signal V _pa at a high level, converting The switching tube S _a of the device branch is turned on, and the a branch works; at the same time, the first OR gate OR1 outputs a high level, that is, the S terminal of the second flip-flop RS2 inputs a high level, and the Q terminal of the second flip-flop RS2 controls the pulse The signal V _p1 is high level, the main switch S ₁ is turned on, the freewheeling switch S ₂ is turned off, the inductor current I _L rises, and the output voltage V _oa rises; when the output voltage V _oa and the inductor current I _L are multiplied by k1 When the superimposed signal rises to the control signal V _e1 , the output signal RR of the second pulse signal generator PGR is high level, the R terminal of the second flip-flop RS2 inputs high level, and the Q terminal of the second flip-flop RS2 controls the pulse The signal V _p1 becomes low level, the main switching tube S ₁ is turned off, the inductor current I _L drops, and the output voltage V _oa drops until entering the next switching cycle.

The first pulse signal generator PGS completes the generation and output of the signal SS: Figure 2 shows that when the product of the inductor current I _L and V _pa is lower than the signal obtained by the inductor current I _L through the sample-and-hold device S/H, the first comparison The output signal of the device CMP1 is high level, otherwise it is low level.

The second pulse signal generator PGR completes the generation and output of signals RR and V _b : Figure 3 shows that when the superimposed signal of the output voltage V _oa and the inductor current _IL multiplied by the coefficient k1 is higher than the control signal V _e1 , the second comparison The output signal of the comparator CMP2 is high level, otherwise, it is low level; when the superposition signal of the output voltage V _ob and the inductor current I _L multiplied by the coefficient k2 is higher than the control signal V _e2 , the output signal of the third comparator CMP3 is High level, otherwise, it is low level; when the output signal of the second comparator CMP2 and the pulse signal V _pa are high level at the same time, the first NAND gate NAND1 outputs low level, and the second NAND gate NAND2 outputs high level level, the third NAND gate NAND3 output signal RR is high level, and the signal V _b is high level; when the output signal of the third comparator CMP3 and the pulse signal V _pb are high level at the same time, the second NAND Gate NAND2 outputs low level, the first NAND gate NAND1 outputs high level, then the third NAND gate NAND3 outputs signal RR is high level, and signal _Vb is low level.

The switching converter TD in this example is a mixed conduction mode single-inductance dual-output Buck converter.

Use PSIM simulation software to carry on time domain simulation analysis to the method of this example, the result is as follows.

Fig. 5 shows the inductor current signal I _L , the drive signals V _pa , V _pb , V _p1 , V _p2 , the pulse signals RR, SS and the on-timer output signal V _ton1 when the converter is working in a steady state according to the embodiment of the present invention. , V _ton2 relationship diagram. It can be seen from the figure that the single-inductance dual-output switching converter of the present invention can work in the CCM-PCCM hybrid mode.

The simulation conditions in Fig. 5 are: input voltage V _in = 20V, voltage reference value V _{ref1 of} branch a = 7V, voltage reference value V _ref2 of branch b = 5V, inductance L = 150μH (its equivalent series resistance is 50mΩ), Capacitance C _oa ＝C _ob ＝470μF, capacitance equivalent series resistance R _ca ＝R _cb ＝100mΩ, load resistance R _oa ＝7Ω, R _ob ＝5Ω, the fixed time of on-timer 1 is 60μs, on-timer 2 The fixed time is 35μs, the equivalent parasitic resistance of the switch tubes S ₁ , S ₂ , S _a , S _b is 50mΩ, the conduction voltage drop of the diodes D1 and D2 is 0.4V, and the coefficients k1 and k2 of the inductor current _IL are both is 0.

Fig. 6 adopts the converter TD of the present invention and V-CRC control PCCM-PCCM single inductance dual output Buck converter when the input voltage changes suddenly (input voltage _Vin changes from 20V→40V), the output voltage of the two output branches Transient time domain simulation waveform. The simulation conditions are consistent with those in Figure 5. It can be seen from the figure that the output voltages V _oa and V _ob of the a and b output branches of the converter TD of the present invention re-enter the steady state with almost no adjustment process after a sudden change in the input voltage; it can be seen that, The converter TD of the invention has good input transient performance, short adjustment time, small output voltage transient variation and strong input fluctuation resistance.

Fig. 7, Fig. 8 respectively adopt the converter TD of the present invention and V-CRC control PCCM-PCCM single inductance double output Buck converter in output branch a load sudden change (the output current I _oa of output branch a changes from 1A to 0.5A change), output branch b load sudden change (the output current I _ob of output branch b changes from 0.5A→1A), the time-domain simulation waveform diagram of the output voltage of the two output branches. The simulation conditions of Fig. 7 and Fig. 8 are consistent with Fig. 5. It can be seen from the figure that the output voltage transient change of the converter TD of the present invention is small after the load mutation, the adjustment time is very short, the load transient performance is good, and the load mutation of one output branch has a negative impact on the other output branch. Road crossings are less affected.

Fig. 9 (a) is the efficiency curve diagram when the load of a output branch of the PCCM-PCCM single-inductance double-output Buck converter controlled by the converter TD and V-CRC of the present invention is changed, and Fig. 9 (b) is a graph using the present invention Efficiency curves of the inventive converter TD and V-CRC controlled PCCM-PCCM single-inductance dual-output Buck converter when the load of the b output branch changes. From Figure 9(a) and Figure 9(b), it can be seen that when the load power is large, the efficiency of the down-converter in both methods is high; as the load decreases, the V-CRC controlled PCCM-PCCM The efficiency of the single-inductance dual-output converter decreases gradually; while the efficiency of the converter of the present invention maintains a relatively high value and improves to some extent when the load power decreases.

FIG. 10 is a time-domain simulation waveform diagram of the output voltages of the two output branches of the converter TD of the present invention when the load of the output branch a changes suddenly. The difference from the simulation conditions in Figure 6 is that the weighting coefficients k1 and k2 of the inductor current I _L are both 0.03, and the equivalent series resistances of the output capacitors C _oa and C _ob are both 20mΩ. It can be seen from the figure that after the inductor current compensation is added, the converter TD can still work stably when the equivalent series resistance of the output capacitor is small, and the load transient response speed of the converter is basically not affected when the compensation coefficient is small. The cross effect between the output branches is very small, and it has good stability.

Embodiment two

As shown in FIG. 11 , this example is basically the same as the first example, except that the converter TD controlled in this example is a mixed conduction mode single-inductance dual-output single-ended forward converter.

In addition to the single-inductance dual-output switching converters in the above embodiments, the present invention can also be used for multiple multi-output converters such as mixed conduction mode single-inductance dual-output half-bridge converters, mixed conduction mode single-inductance dual-output full-bridge converters, etc. in the circuit topology.

Claims (4)

1. single-inductance double-output switch converters method for controlling frequency conversion, it is characterised in that：Main switch is combined using output voltage The frequency control of inductive current realizes the dynamic of inductive current by the turn-off time that main switch is fixed in each switch periods State afterflow；In each switch periods, inductive current is detected, obtains signal I_L, detection two output branches output voltage obtain To signal V_oaAnd V_ob；By V_oaWith voltage reference value V_ref1It is sent to the first error amplifier EA1 and generates signal V_e1, by V_obAnd electricity Press a reference value V_ref2It is sent to the second error amplifier EA2 and generates signal V_e2；By I_LIt is sent into the first pulse signal producer PGS productions Raw signal SS；By I_L、V_oa、V_ob、V_e1And V_e2And V_pa、V_pbIt is sent into the second pulse signal producer PGR generation signals RR and V_b； The Q1 of first trigger RS1 is terminated into the input terminal into the first conducting timer TON1, then by the first conducting timer TON1's Output signal V_ton1The first trigger RS1, which is sent into, with signal SS generates pulse signal V_paAnd V_pb, converter branch to be controlled to open Close the turn-on and turn-off of pipe；By signal V_ton1With signal V_pbThe signal and signal RR generated through first or door OR1 is sent into second and is touched It sends out device RS2 and generates pulse signal V_p1, to control the turn-on and turn-off of converter main switch；Signal V_bWith signal V_paBy Two or door OR2 generates signal V_or；Signal V_orSignal V is generated through the second conducting timer TON2_ton2；Signal V_p1It is produced through NOT gate NOT Raw signal and signal V_ton2By generating pulse signal V with door AND_p2, to convertor controls continued flow switch pipe conducting and Shutdown.

2. the control device of single-inductance double-output switch converters method for controlling frequency conversion according to claim 1, feature It is：Including first voltage detection circuit VS1, second voltage detection circuit VS2, current detection circuit IS, the amplification of the first error Device EA1, the second error amplifier EA2, the first pulse signal producer PGS, the second pulse signal producer PGR, the first triggering Device RS1, the second trigger RS2, first or door OR1, second or door OR2, the first conducting timer TON1, the second conducting timer TON2, NOT gate NOT and door AND, the first driving circuit DR1, the second driving circuit DR2, third driving circuit DR3 and 4 wheel driven Dynamic circuit DR4；The first voltage detection circuit VS1 is connected with the first error amplifier EA1, second voltage detection circuit VS2 is connected with the second error amplifier EA2；The Q1 ends of current detection circuit IS and the first trigger respectively with the first pulse signal Generator PGS is connected；First voltage detection circuit VS1, second voltage detection circuit VS2, the first error amplifier EA1, second Error amplifier EA2, current detection circuit IS, the Q1 ends of the first trigger RS1 and Q ends respectively with the second pulse signal producer PGR is connected；The SS ends of first pulse signal producer PGS are connected with the S ends of the first trigger RS1；The Q1 of first trigger RS1 End is connected with the first conducting timer TON1；The R ends phase of the output terminal and the first trigger RS1 of first conducting timer TON1 Even；The output terminal of first conducting timer TON1, the Q ends of the first trigger RS1 are connected respectively with first or door OR1, first or The output terminal of door OR1 is connected with the S ends of the second trigger RS2；The RR ends of second pulse signal producer PGR and the second trigger The R ends of RS2 are connected；The V of second pulse signal producer PGR_bThe Q1 ends of output terminal and the first trigger RS1 respectively with second or Door OR2 is connected；The output terminal of second or door OR2 is connected with the second conducting timer TON2；The Q ends of second trigger RS2 and non- Door NOT is connected；The output terminal of NOT gate NOT and second or door OR2 are connected respectively and with door AND；The Q ends of first trigger RS1 connect The Q1 ends for meeting the first driving circuit DR1, the first trigger RS1 connect the Q ends company of the second driving circuit DR2, the second trigger RS2 Third driving circuit DR3 is met, the 4th driving circuit DR4 is connect with the output terminal of door AND.

3. the control device of single-inductance double-output switch converters method for controlling frequency conversion according to claim 2, feature It is：The first pulse signal producer PGS includes multiplier MULT, sampling holder S/H and first comparator CMP1； The Q1 ends of current detection circuit IS, the first trigger RS1 are connected with multiplier MULT；Current detection circuit IS is kept with sampling Device S/H is connected；The output terminal of multiplier MULT and sampling holder S/H are connected respectively with first comparator CMP1.

4. the control device of single-inductance double-output switch converters method for controlling frequency conversion according to claim 2, feature It is：The second pulse signal producer PGR includes first adder ADD1, second adder ADD2, the second comparator CMP2, third comparator CMP3, the first NAND gate NAND1, the second NAND gate NAND2, third NAND gate NAND3；First voltage The output terminal of detection circuit VS1, the output terminal of current detection circuit IS are connect respectively with first adder ADD1, by first voltage The output signal V of detection circuit VS1_oa, current detection circuit IS output signal I_LFirst adder is sent into after being multiplied by coefficient k 1 ADD1；The output terminal of second voltage detection circuit VS2 is connect with second adder ADD2, by second voltage detection circuit VS2's Output signal V_ob, signal I_LSecond adder ADD2 is sent into after being multiplied by coefficient k 2；First error amplifier EA1, first adder The output terminal of ADD1 is connected with the second comparator CMP2, the second error amplifier EA2, second adder ADD2 output terminal difference It is connected with third comparator CMP3；The Q1 ends of the output terminal of second comparator CMP2 and the first trigger RS1 connect first respectively NAND gate NAND1；The Q ends of the output terminal of third comparator CMP3 and the first trigger RS1 connect the second NAND gate respectively NAND2；First NAND gate NAND1, the second NAND gate NAND2 are connected respectively with third NAND gate NAND3, the second NAND gate The output signal of NAND2 is V_b, the output signal of third NAND gate NAND3 is RR.