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CN107230671A - 半导体集成电路芯片以及半导体集成电路晶片 - Google Patents

半导体集成电路芯片以及半导体集成电路晶片 Download PDF

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Publication number
CN107230671A
CN107230671A CN201710177252.5A CN201710177252A CN107230671A CN 107230671 A CN107230671 A CN 107230671A CN 201710177252 A CN201710177252 A CN 201710177252A CN 107230671 A CN107230671 A CN 107230671A
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wiring
protection ring
electric conductivity
external connection
connection terminals
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CN201710177252.5A
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CN107230671B (zh
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大渕笃
米冈卓
加贺博史
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Synaptics Inc
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Sin Knapp Dick J Japan Contract Society
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Abstract

即便到达半导体电路的内部的导电性切片从切割端面露出，也不会使保护环的防湿性能恶化。一种半导体集成电路芯片，在半导体基板的上方具有多层布线结构的半导体电路、包围半导体电路的保护环、连接于所述多层布线结构的最上层布线并在表面露出的外部连接端子，其中，规定的外部连接端子（17_i）在保护环的内侧经由导电性的通孔（18）与规定的布线导通，在保护环的外侧经由导电性的通孔（19）与导电性切片（6）导通。导电性切片是测试用引出布线的切片，由于切割而使其切断面露出。在跨过保护环的外部连接端子的一方连接有导电性切片，在另一方连接有保护环内的最上层布线，因此在保护环中在中途不需要切口。

Description

半导体集成电路芯片以及半导体集成电路晶片
技术领域
本发明涉及半导体集成电路芯片中防止来自切割切断面的污染的结构，进而涉及搭载有多个这样的半导体集成电路芯片的半导体集成电路晶片，涉及对例如显示驱动器IC应用而有效的技术。
背景技术
在硅晶片这样的晶片上经过CMOS集成电路制造技术等的规定的半导体集成电路制造工艺形成有多个芯片形成区域，在介于各个芯片形成区域之间的切割区域被切断的芯片形成区域的单片成为半导体集成电路芯片。
以往在切割为单片之前的半导体集成电路晶片的状态下进行半导体集成电路芯片的检查。为了检查的效率化，在切割区域设置有测试布线，该测试布线在芯片形成区域间将各个芯片形成区域的具有同一功能的外部端子彼此共同连接。在切割区域，测试布线与每个信号或电源的测试焊盘连接，将测试探针的端子推压到测试焊盘，能够以晶片为单位进行芯片形成区域的半导体集成电路的检查。作为记载了这样的测试布线以及测试焊盘的文献的例子，有专利文献1。
当切割半导体集成电路晶片时，存在应力集中在芯片形成区域的周围而产生裂隙的担忧。若在半导体集成电路芯片的周边部产生裂隙，那么水分容易从外部浸入。因此，如在专利文献2中也记载的那样，在芯片形成区域的外周设置保护环（耐湿环），能够防止水分的浸入。
现有技术文献
专利文献
专利文献1 国际公开第2010/110233号小册子
专利文献2 日本特开2012-89668号公报。
发明内容
发明要解决的课题
本发明人对防止来自因切割产生的切断面的水分等的进入进行了讨论。专利文献2的观点是，在保护环（guard ring）的外侧的切割区域形成应力吸收图案，裂隙难以进入。本发明人的着眼点是，水分难以从端面等浸入，其中所述端面是指到达在切割区域形成的测试焊盘的测试布线因切割而被切断并露出的端面。被切断的测试布线的切片与在切割后的半导体集成电路芯片上形成的半导体电路导通。即使采用以保护环包围半导体电路的周围的结构，为了使测试布线的切片与半导体电路的内部导通而实现晶片状态下的检查，必须切掉保护环的一部分使切片在此处通过。
但是，若切掉保护环的一部分，那么该部分的防湿性能恶化，水或离子引起的集成电路的污染成为问题。
本发明的目的在于提供一种即便使到达半导体电路的内部的导电性切片从切割端面等露出也不会使保护环的防湿性能恶化的半导体集成电路芯片以及适于这样的半导体集成电路芯片的取得的半导体集成电路晶片。
本发明的所述以及其他目的和新的特征根据本说明书的记述以及添附的附图是明确的。
用于解决课题的方案
若简单地对在本申请中公开的发明中的代表性的发明的概要进行说明，则如下述所示。此外，在本项中记载在括号中的附图标记等是为了使理解容易化的一例。
[1]<将保护环内的最上层布线从外部的测试用引出布线用保护环分断>
半导体集成电路芯片（1）具有：半导体基板（10）；半导体电路（11），形成于所述半导体基板的上方，在上下具有多层布线结构；金属制的保护环（14），形成于所述半导体基板的上方，包围所述半导体电路；多个外部连接端子（17_1～17_n），与所述半导体电路具有的所述多层布线结构的规定的布线（15）连接并在表面露出。所述多个外部连接端子内的规定的外部连接端子（17_1）在所述保护环的内侧经由导电性的通孔（18）与所述规定的布线导通，在所述保护环的外侧经由导电性的通孔（19）与导电性切片（6）导通。所述导电性切片是测试用引出布线（6）的切片，是通过切割而使得其切断面露出的布线。
由此，在跨过保护环的外部连接端子的一方连接有导电性切片，在另一方连接有保护环内的布线，因此不需要在保护环的中途形成切口。因此，即便使到达半导体电路的内部的导电性切片从切割端面等露出，也不会使保护环的防湿性能恶化。导电性切片被利用于在切割前在晶片状态下多个半导体电路的统一检查。
[2]<由贵金属布线材料构成的外部连接端子、由铝布线材料构成的导电性切片>
在项1中，所述外部连接端子由贵金属布线材料构成，所述导电性切片以及所述保护环由铝布线材料构成。
由此，即便污染行进到位于保护环的外侧的导电性切片以及通孔，由贵金属布线材料构成的外部连接端子也不受其影响，防湿性能是完全的。
[3]<切片进入从保护环的外侧向内侧凹陷的凹陷部>
在项2中，所述导电性切片进入从所述保护环的外侧向内侧凹陷的凹陷部并在上下方向与外部连接端子重叠的位置经由导电性的通孔连接于外部连接端子。
由此，不需要在俯视图中将外部连接端子扩大到保护环的外侧。
[4]<导电性切片是从切割区域的测试焊盘延伸的布线的一部分>
在项2中，所述导电性切片是从在被切割的切割区域形成的测试焊盘（4）延伸的布线。
由此，与测试焊盘连接的导电性切片使在切割前在晶片状态下进行半导体电路的统一检查成为可能。
[5]<在相邻布线层间利用围绕导电通孔将包围半导体电路的闭路布线彼此连接的保护环>
在项2中，所述保护环由在所述多层布线结构的各布线层以围绕所述半导体电路的外侧的方式分别在上下方向重叠地配置的形成闭路的闭路布线（12_1～12_6）和将在上下方向相邻的布线层的所述闭路布线彼此在该上下方向连接的导电性的围绕通孔构成（13_1～13_5）构成。
由此，能够利用各布线层的闭路布线以及围绕通孔在半导体基板上将保护环形成为壁状。
[6]<将保护环内的最上层布线从外部的测试用引出布线用保护环分断>
半导体集成电路晶片（9）在半导体晶片（7）上隔开配置有多个芯片形成区域（1w），所述芯片形成区域之间为切割区域（8）。各个所述芯片形成区域具有：半导体电路（11），形成于所述半导体晶片的上方，在上下具有多层布线结构；金属制的保护环（14），形成于所述半导体晶片的上方，包围所述半导体电路；以及多个外部连接端子（17_1～17_n），与所述半导体电路具有的所述多层布线结构的规定的布线（15）连接并在表面露出。所述切割区域具有多个测试焊盘（4）。在各个芯片形成区域所述多个外部连接端子内的具有同一功能的规定的多个外部连接端子（17_1）在所述保护环的内侧经由导电性的通孔（18）与所述规定的布线导通，在所述保护环的外侧经由导电性的通孔（19）与从所述测试焊盘引出的测试用引出布线（6）连接。
由此，在跨过保护环的外部连接端子的一方连接有导电性切片，在另一方连接有保护环内的布线，因此不需要在在保护环的中途形成切口。因此，即便在晶片状态下的检查后利用切割使测试用引出布线的切断面露出，也不会使保护环的防湿性能恶化。
[7] <由贵金属布线材料构成的外部连接端子、由铝布线材料构成的导电性切片>
在项6中，所述外部连接端子由贵金属布线材料构成，所述导电性切片以及所述保护环由铝布线材料构成。
由此，即便污染行进到位于保护环的外侧的导电性切片以及通孔，由贵金属布线材料构成的外部连接端子也不受其影响，防湿性能是完全的。
[8] <从一个测试焊盘共同地向并列的多个芯片形成区域供给信号等>
在项7中，具有所述同一功能的规定的多个外部连接端子在该芯片形成区域导通（Lvdd、Lvss）。在所述半导体晶片上夹着所述切割区域配置有在一个方向排列的3个以上的所述芯片形成区域，从在所述切割区域形成的所述测试用焊盘朝向两侧的芯片形成区域引出测试用引出布线，引出的所述测试用引出布线连接于在其两侧的芯片形成区域的每一个形成的彼此具有同一功能的所述规定的外部连接端子。
由此，具有所述同一功能的规定的多个外部连接端子在该芯片形成区域导通，因此能够有助于在切割区域内配置的测试布线的条数和长度的缩小。进而，能够从一个测试焊盘共同地对夹着切割区域并列的多个芯片形成区域的规定的外部连接端子供给信号或电源，所以，能够削减在切割前在晶片状态下推压到测试焊盘的测试探针的端子数，或者相对于1个芯片形成区域的外部端子数的增大，能够抑制测试探针的端子数的增大。
[9] <分配给电源或者接地的规定的外部连接端子>
在项8中，所述规定的外部连接端子是电源端子或者接地端子。
由此，关于电源或接地的供给，得到项8的作用效果。
[10] <切片进入从保护环的外侧向内侧凹陷的凹陷部>
在项7中，所述测试用引出布线进入从所述保护环的外侧向内侧凹陷的凹陷部并在上下方向与外部连接端子重叠的位置经由导电性的通孔连接于外部连接端子。
由此，不需要在俯视图中将外部连接端子扩大到保护环的外侧。
[11] <在相邻布线层间利用围绕通孔将包围半导体电路的闭路布线彼此连接的保护环>
在项7中，所述保护环由在所述多层布线结构的各布线层以围绕所述半导体电路的外侧的方式分别在上下方向重叠地配置的形成闭路的闭路布线（12_1～12_6）和将在上下方向相邻的布线层的所述闭路布线彼此在该上下方向连接的导电性的围绕通孔（13_1～13_5）构成。
由此，能够利用各布线层的闭路布线以及围绕通孔在半导体基板上将保护环形成为壁状。
发明的效果
若简单地对由在本申请中公开的发明中的代表性的发明得到的效果进行说明，则如下述那样。
即，即便使到达半导体电路的内部的导电性切片从切割端面露出，也不会使保护环的防湿性能恶化。
附图说明
图1是示出用保护环完全将保护环内的最上层布线和保护环外部的测试用引出布线分断的状态的俯视图。
图2是图1的A1-A1剖面图。
图3是示出从图1的状态利用切割使测试用引出布线在芯片侧面露出的状态的俯视图。
图4是图3的A2-A2剖面图。
图5是概略地示出半导体集成电路晶片的一部分的俯视图。
图6是例示出保护环的构图的立体图。
图7是图6的CDEF面的剖面图。
图8是示出金凸点（bump）形成前的半导体集成电路晶片的一部分的纵剖面图。
图9是示出相对于图8的状态在表面进行UBM溅射的状态的纵剖面图。
图10是相对于图9的状态在表面涂敷光致抗蚀剂的状态的纵剖面图。
图11是示出针对图10的状态的曝光工序的纵剖面图。
图12是示出相对于图11的状态进行显影的状态的纵剖面图。
图13是示出相对于图12的状态进行镀金的状态的纵剖面图。
图14是示出相对于图13的状态除去光致抗蚀剂的状态的纵剖面图。
图15是示出相对于图14的状态除去UBM的状态的纵剖面图。
图16是示出通过保护环的切口将保护环外部的测试用引出布线连接于保护环内的最上层布线的比较例的状态的俯视图。
图17是图16的B1-B1剖面图。
图18是示出从图16的状态利用切割使测试用引出布线在芯片侧面露出的状态的俯视图。
图19是图18的B2-B2剖面图。
具体实施方式
本发明的半导体集成电路晶片9如在图5中示出其一部分那样，在半导体晶片7上以矩阵状隔开地配置有多个芯片形成区域1w，芯片形成区域1w之间为切割区域8。芯片形成区域1w是在半导体集成电路晶片9完成后通过切割而成为半导体集成电路芯片1的区域。半导体晶片7实际上为圆形，例如由单晶硅构成。如图6所示，在半导体集成电路芯片1中也将半导体晶片7的部分称作半导体基板10。此处，芯片形成区域1w没有特别限制，但是，被做成在液晶面板的显示驱动中使用的显示驱动器IC，具有长条状，沿着其长边排列有多个外部连接端子16_1～16_m、17_1～17_n。沿着一个长边的外部连接端子17_1～17_n为液晶面板的源极驱动端子、栅极控制信号端子、显示同步信号端子、电源端子以及接地端子等。沿着另一个长边的外部连接端子16_1～16_m为主接口用的端子。
各个芯片形成区域1w如图6所例示那样，在半导体晶片7的上方具备半导体电路11，该半导体电路11具有MOS晶体管或电容元件等的所希望的电路元件和上下的多层布线结构，同样地在半导体晶片7的上方形成有包围半导体电路11的金属制的保护环14。
半导体电路11按照所希望那样利用多层布线将在半导体晶片7的主面形成的电路元件进行连接而具有所需要的电路功能例如显示驱动器IC所需要的显示控制功能。多层布线结构没有特别限制，但是被做成在电路元件的上方层叠的布线层L1至布线层L5的5层布线层结构，各布线层具有构成用于连接电路元件的布线的所希望的布线图案，布线例如为铝布线，各层的布线被层间绝缘膜绝缘。关于与半导体电路11中的电路元件以及L1至L5的布线层相关的器件结构、制造方法，应用公知的CMOS集成电路制造技术等即可，此处省略其详细的说明。
保护环14如图6所例示那样由在多层布线结构的各布线层L1～L5以围绕半导体电路11的外侧的方式分别在上下方向重叠地配置的形成闭路的闭路布线12_1～12_6和将在上下方向相邻的布线层的所述闭路布线12_1～12_6彼此在该上下方向连接的导电性的围绕通孔13_1～13_5构成。保护环14形成包围半导体电路11的壁。闭路布线12_1～12_6例如由与其他的布线相同的铝布线材料构成。围绕通孔13_1～13_5例如由与其他的通孔相同的铝布线材料构成。保护环14的纵剖面结构如示出图6中的CDEF面的剖面的图7那样。保护环14的制造方法采用专利文献2等记载的公知的制造方法即可。
切割区域8如图5所例示那样具有多个测试焊盘4。虽然没有特别限制，但是测试焊盘4配置在芯片形成区域1w的短边的旁边的切割区域8。从测试焊盘4起在其左右测试用引出布线6延伸到芯片形成区域1w。虽然没有特别限制，但是测试用引出布线6连接于图5的右侧的芯片形成区域1w的外部连接端子17_1，并且连接于图5的左侧的芯片形成区域1w的外部连接端子17_n。芯片形成区域1w的外部连接端子17_1、17_n在芯片形成区域1w的内部利用电源布线Lvdd或者接地布线Lvss导通。因此，如根据图5明确的那样，对配置成左右一列的多个芯片形成区域能够从配置于同列的任意一个测试焊盘4供给电源或接地。不需要按每个芯片形成区域1w从测试焊盘4单独地供给电源或接地。即，为了统一检查多个芯片形成区域1w的半导体电路11，测试焊盘4是有用的。
本实施方式的特征的结构是在不将保护环14在中途分断的情况下将测试焊盘4连接于规定的外部连接端子17_1的结构。如示出其连接部的平面结构的图1以及示出图1的A1-A1剖面的图2那样，外部连接端子17_1在保护环14的内侧经由导电性的通孔18与规定的最上层布线15导通，在保护环的外侧经由导电性的通孔19连接于从所述测试焊盘4引出的测试用引出布线6。规定的最上层布线15、测试焊盘4以及测试用引出布线6例如使用铝布线材料分别形成于最上层的布线层。在俯视图中通孔19位于保护环14之外。即，测试用引出布线6进入从保护环14的外侧向内侧凹陷的凹陷部14A，在上下方向与外部连接端子17_1重叠的位置，测试用引出布线6经由通孔19连接于外部连接端子17_1。在图1以及图2中，切断线D的左侧通过切割而被切断。测试用引出布线6在中途被切断，从半导体集成电路芯片1的侧面露出。在图3中示出从图1的状态利用切割而使测试用引出布线在芯片侧面露出的状态，在图4中示出其A2-A2剖面。此外，除了测试焊盘4、外部连接端子17之外，覆盖半导体集成电路晶片的钝化膜在图1以及图3中省略图示。
外部连接端子17由贵金属布线材料构成，例如作为金凸点而实现。在图8中例示出金凸点形成前的半导体集成电路晶片的一部分。最上层布线15形成为铝焊盘。21是L4布线层的铝布线。20是在铝布线21的表面背面形成的由TiN构成的势垒金属，防止由铝的侵蚀引起的恶化。对于图8的状态在表面溅射凸点下金属（UBM）23（图9），在其上涂敷光致抗蚀剂30（图10），使用光掩模31对表面进行曝光（图11）。曝光后进行显影，由此，在未曝光部形成有开口32（图12）。接着，将剩余的光致抗蚀剂30作为掩模在开口32进行镀金（图13），然后，将光致抗蚀剂30除去（图14），将露出的UBM除去（图15）。由此，能够由金凸点构成外部连接端子17。由金凸点构成的外部连接端子17的厚度为10～12μm，其下的最上层布线15或闭路布线12_1～12_6等的布线的厚度为数千埃。如根据上述明确的那样可知通孔18、19也作为金凸点的制造的一环而形成即可。
如上述那样构成的半导体集成电路晶片7能够从一个测试焊盘4共同地对并列的多个芯片形成区域1w供给信号或电源等。即，具有同一功能的规定的多个外部连接端子17_1、17_n如图5所例示那样在该芯片形成区域1w导通，因此，能够从一个测试焊盘4共同地对夹着切割区域8并列的多个芯片形成区域1w的规定的外部连接端子17_1、17_n供给信号或电源。因此，能够削减在切割前在晶片状态下推压到测试焊盘的测试探针的端子数，或者相对于1个芯片形成区域1w的外部端子数的增大，能够抑制测试探针的端子数的增大。进而，外部连接端子17_1、17_n如图5那样在芯片形成区域1w导通发挥将在切割区域内配置的测试布线的条数和长度缩小的作用。
此外，如上述那样构成的半导体集成电路晶片将保护环14的内侧的最上层布线15从保护环14的外侧的测试用引出布线6用保护环分断。即，在跨过保护环14的外部连接端子17_1的一方连接有测试用引出布线6，在另一方连接有保护环14的内侧的最上层布线15，因此不需要在保护环14中在中途形成切口。因此，即便在切割后的半导体集成电路芯片1中使到达半导体电路11的内部的测试用引出布线的导电性切片6从切割端面等露出，也不会使保护环14的防湿性能恶化。如图3所例示那样，沿着露出的导电性切片6进入的水分、氯离子被保护环14阻挡，阻止侵入其内部。由于与导电性切片6连接的通孔19、外部连接端子17_1由金凸点形成，所以，其自身难以被腐蚀，即便污染行进到了位于保护环的外侧的导电性切片6，由贵金属布线材料构成的导电性通孔19以及外部连接端子17_1也不受其影响，防湿性能是完全的。
相对于此，如图16以及图17的比较例那样，在通过保护环43的切口43A将保护环43的外侧的测试用引出布线42连接于保护环43的内侧的最上层布线40的情况下，如图18以及图19那样，沿着切割后露出的导电性切片42进入的水分、氯离子通过切口43A侵入到保护环43的内部。由此，即便通孔18、外部连接端子17_1由金凸点形成，如果污染行进到了构成其根基的最上层布线40，那么外部连接端子17_1和最上层布线40的导通变得不稳定，进而，如果腐蚀扩展，那么在其他部分也产生不良。
如图1所例示那样，测试用引出布线（导电性切片）6进入从保护环14的外侧向内侧凹陷的凹陷部14A，因此，即便形成导电性通孔19，也不需要在俯视图中将外部连接端子17_1扩大到保护环14的外侧。
以上基于实施方式具体地对本发明人的发明进行了说明，但是，本发明并不限于此，当然能够在不脱离其宗旨的范围内进行各种变更。
例如，在上述说明中将在与长条状的芯片形成区域的短边对置的位置的切割区域配置测试焊盘的情况作为一例，但是，本发明并不限于此，在将在与芯片形成区域的长边对置的位置的切割区域配置的测试焊盘连接于芯片形成区域内的保护环内部的情况下，进而在这二者的情况下当然都能够应用。此外，应用本发明的外部连接端子不限于电源以及接地用，也可以是数据、地址、控制信号以及参考电压等无论哪种信号或电压用的外部连接端子。
贵金属布线材料不限于金，也可以是铂等。关于铝布线材料，能够使用铜布线材料或硅化物等各种布线材料。多个布线结构不限于5层，能够采用其以外的布线层数。
此外，导电性通孔18、19不需要是贵金属。也可以使用铝布线材料形成。
附图标记说明
1 半导体集成电路芯片
1w 芯片形成区域
4 测试焊盘
6 测试用引出布线（导电性切片）
7 半导体晶片
8 切割区域
9 半导体集成电路晶片
11 半导体电路
L1～L5 布线层
12_1～12_6 闭路布线
13_1～13_5 围绕通孔
14 保护环
14A 凹陷部
15 规定的最上层布线
16_1～16_m、17_1～17_n 外部连接端子
Lvdd电源布线
Lvss接地布线
18 导电性的通孔
19 导电性的通孔
20 由TiN构成的势垒金属
21 L4布线层的铝布线
23 凸点下金属（UBM）
30 光致抗蚀剂
31 光掩模
32 开口
40 最上层布线
42 测试用引出布线
43 保护环
43A 切口。

Claims (11)

1.一种半导体集成电路芯片，具有：半导体基板；半导体电路，形成于所述半导体基板的上方，在上下具有多层布线结构；金属制的保护环，形成于所述半导体基板的上方，包围所述半导体电路；以及多个外部连接端子，与所述半导体电路具有的所述多层布线结构的规定的布线连接并在表面露出，其中，
所述多个外部连接端子内的规定的外部连接端子在所述保护环的内侧经由导电性的通孔与所述规定的布线导通，在所述保护环的外侧经由导电性的通孔与导电性切片导通，
所述导电性切片是测试用引出布线的切片，是通过切割使其切断面露出的布线。
2.如权利要求1所述的半导体集成电路芯片，其中，
所述外部连接端子由贵金属布线材料构成，所述导电性切片以及所述保护环由铝布线材料构成。
3.如权利要求2所述的半导体集成电路芯片，其中，
所述导电性切片进入从所述保护环的外侧向内侧凹陷的凹陷部并在上下方向与外部连接端子重叠的位置经由导电性的通孔连接于外部连接端子。
4.如权利要求2所述的半导体集成电路芯片，其中，
所述导电性切片是从在被切割的切割区域形成的测试焊盘延伸的布线。
5.如权利要求2所述的半导体集成电路芯片，其中，
所述保护环由在所述多层布线结构的各布线层以围绕所述半导体电路的外侧的方式分别在上下方向重叠地配置的形成闭路的闭路布线和将在上下方向相邻的布线层的所述闭路布线彼此在该上下方向连接的导电性的围绕通孔构成。
6.一种半导体集成电路晶片，在半导体晶片上多个芯片形成区域隔开配置，所述芯片形成区域之间为切割区域，其中，
各个所述芯片形成区域具有：半导体电路，形成于所述半导体晶片的上方，在上下具有多层布线结构；金属制的保护环，形成于所述半导体晶片的上方，包围所述半导体电路；以及多个外部连接端子，与所述半导体电路具有的所述多层布线结构的规定的布线连接并在表面露出，
所述切割区域具有多个测试焊盘，
在各个芯片形成区域所述多个外部连接端子内的具有同一功能的规定的多个外部连接端子在所述保护环的内侧经由导电性的通孔与所述规定的布线导通，在所述保护环的外侧经由导电性的通孔与从所述测试焊盘引出的测试用引出布线连接。
7.如权利要求6所述的半导体集成电路晶片，其中，
所述外部连接端子由贵金属布线材料构成，所述导电性切片以及所述保护环由铝布线材料构成。
8.如权利要求7所述的半导体集成电路晶片，其中，
所述具有同一功能的规定的多个外部连接端子在该芯片形成区域导通，
在所述半导体晶片上夹着所述切割区域配置有在一个方向排列的3个以上的所述芯片形成区域，从在所述切割区域形成的所述测试用焊盘朝向两侧的芯片形成区域引出测试用引出布线，引出的所述测试用引出布线连接于在其两侧的芯片形成区域的每一个形成的彼此具有同一功能的所述规定的外部连接端子。
9.如权利要求8所述的半导体集成电路晶片，其中，
所述规定的外部连接端子是电源端子或者接地端子。
10.如权利要求7所述的半导体集成电路晶片，其中，
所述测试用引出布线进入从所述保护环的外侧向内侧凹陷的凹陷部并在上下方向与外部连接端子重叠的位置经由导电性的通孔连接于外部连接端子。
11.如权利要求7所述的半导体集成电路晶片，其中，
所述保护环由在所述多层布线结构的各布线层以围绕所述半导体电路的外侧的方式分别在上下方向重叠地配置的形成闭路的闭路布线和将在上下方向相邻的布线层的所述闭路布线彼此在该上下方向连接的导电性的围绕通孔构成。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399883A (en) * 1977-02-14 1978-08-31 Hitachi Ltd Manufacture of semiconductor device
JP2002208618A (ja) * 2001-01-10 2002-07-26 Rohm Co Ltd 半導体装置およびその製造方法
US20050127395A1 (en) * 2003-12-11 2005-06-16 Fujitsu Limited Semiconductor device and fabrication method thereof
US20050258853A1 (en) * 2003-05-15 2005-11-24 Haruo Sorimachi Semiconductor device and interposer
JP2006041236A (ja) * 2004-07-28 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
US20120007211A1 (en) * 2010-07-06 2012-01-12 Aleksandar Aleksov In-street die-to-die interconnects
US20120018726A1 (en) * 2009-03-24 2012-01-26 Nec Corporation And Renesas Electronics Corporation Semiconductor wafer and method for manufacturing semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4472650B2 (ja) * 2006-02-27 2010-06-02 シャープ株式会社 半導体ウェハ、半導体チップ、半導体装置、ならびにウェハテスト方法
JP5324822B2 (ja) * 2008-05-26 2013-10-23 ラピスセミコンダクタ株式会社 半導体装置
JP5443827B2 (ja) * 2009-05-20 2014-03-19 ルネサスエレクトロニクス株式会社 半導体装置
JP2012089668A (ja) 2010-10-19 2012-05-10 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399883A (en) * 1977-02-14 1978-08-31 Hitachi Ltd Manufacture of semiconductor device
JP2002208618A (ja) * 2001-01-10 2002-07-26 Rohm Co Ltd 半導体装置およびその製造方法
US20050258853A1 (en) * 2003-05-15 2005-11-24 Haruo Sorimachi Semiconductor device and interposer
US20050127395A1 (en) * 2003-12-11 2005-06-16 Fujitsu Limited Semiconductor device and fabrication method thereof
JP2006041236A (ja) * 2004-07-28 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
US20120018726A1 (en) * 2009-03-24 2012-01-26 Nec Corporation And Renesas Electronics Corporation Semiconductor wafer and method for manufacturing semiconductor device
US20120007211A1 (en) * 2010-07-06 2012-01-12 Aleksandar Aleksov In-street die-to-die interconnects

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