The application is the entitled " wafer scale for the applying date submitted to China State Intellectual Property Office being on September 5th, 2011
The divisional application of No. 201180046150.0 application of light emission diode package member and its manufacturing method ".
Specific embodiment
It is described more fully the present invention hereinafter with reference to attached drawing, exemplary reality the invention is shown in the accompanying drawings
Apply example.However, the present invention can be embodied in many different forms and should not be construed as being limited to set forth herein show
Example property embodiment.On the contrary, provide these exemplary embodiments make the disclosure completely and will be to those skilled in the art fully
Convey the scope of the present invention.In the accompanying drawings, for clarity, the size and relative size of layer and region can be exaggerated.In the accompanying drawings
Same label indicates same element.
It will be appreciated that it can when another element "upper" of the element of such as layer, film, region or substrate referred to as " "
With directly on another element or there may also be intermediary elements.On the contrary, when element is referred to as " directly existing " another element
When "upper", then exist without intermediary element.
Fig. 1 is the schematic cross sectional views of the LED encapsulation piece 100 of the first exemplary embodiment according to the present invention.
Referring to Fig.1, LED encapsulation piece 100 may include semiconductor stack overlapping piece 30, the first contact layer 35, the second contact layer 31,
First insulating layer 33, second insulating layer 37, first electrode pad 39a, second electrode pad 39b, the first convex block 45a and second are convex
Block 45b.LED encapsulation piece 100 can also include insulating layer 43, mute convex block 45c and wavelength shifter 51.
Semiconductor stack overlapping piece 30 includes the first conductive type upper semiconductor layer 25, active layer 27 and the second conductive type lower semiconductor
Layer 29.Active layer 27 is arranged between upper semiconductor layer 25 and lower semiconductor layer 29.
Active layer 27, upper semiconductor layer 25 and lower semiconductor layer 29 can be by the III-N of such as (Al, Ga, In) N semiconductor
Based compound semiconductor is constituted.Each of upper semiconductor layer 25 and lower semiconductor layer 29 can be single-layer or multi-layer.For example, removing
Except contact layer and coating, upper semiconductor layer 25 and/or lower semiconductor layer 29 may include superlattice layer.Active layer 27 can have
There are single quantum or multi-quantum pit structure.The first conductive type can be N-shaped, and the second conductive type can be p-type.It may be selected
, the first conductive type can be p-type, and the second conductive type can be N-shaped.Since upper semiconductor layer 25 can be by having relatively low ratio
The n-type semiconductor layer of resistance is formed, so upper semiconductor layer 25 can have relatively thick thickness.It therefore, can be in semiconductor-on-insulator
Coarse surface R is formed on the upper surface of layer 25, wherein coarse surface R increases the extraction of the light generated in active layer 27
Efficiency.
Semiconductor stack overlapping piece 30 has conductive with exposure first across the second conductive type lower semiconductor layer 29 and active layer 27
Multiple contact hole 30a (referring to (b) in Fig. 5) of type upper semiconductor layer, the contact of the first contact layer 35 are exposed to multiple contact holes
In the first conductive type upper semiconductor layer 25.
Second contact layer 31 contacts the second conductive type lower semiconductor layer 29.Second contact layer 31 includes that reflective metal layer is anti-
Penetrate the light generated in active layer 27.In addition, the second contact layer 31 can form the Europe with the second conductive type lower semiconductor layer 29
Nurse contact.
First insulating layer 33 covers the second contact layer 31.In addition, the first insulating layer 33 covering semiconductor stack overlapping piece 30 is sudden and violent
The side wall being exposed in multiple contact hole 30a.In addition, the first insulating layer 33 can cover the side surface of semiconductor stack overlapping piece 30.The
One insulating layer 33 makes the first contact layer 35 and the second contact layer 31 insulate, while making be exposed in multiple contact hole 30a second
Conductivity type lower semiconductor layer 29 and active layer 27 and the first contact layer 35 insulate.First insulating layer 33 can be by single-layer or multi-layer
(for example, silicon oxide film or silicon nitride film) composition.Selectively, the first insulating layer 33 can be by having not by being alternately stacked
With such as SiO of refractive index2/TiO2Or SiO2/Nb2O5Insulating layer formed distributed Bragg reflector composition.
First contact layer 35 is located at 33 lower section of the first insulating layer and passes through the first insulating layer 33 in multiple contact hole 30a
To contact the first conductive type upper semiconductor layer 25.First contact layer 35 includes the contact of contact the first conductive type upper semiconductor layer 25
The part 35a and coupling part 35b that contact portion 35a is connected to each other.Therefore, by coupling part 35b by contact portion 35a
It is electrically connected to each other.First contact layer 35 is formed in below some regions of the first insulating layer 33 and can be by reflective metal layer group
At.
Second insulating layer 37 covers the first contact layer 35 below the first contact layer 35.In addition, second insulating layer 37 is being covered
The side surface of semiconductor stack overlapping piece 30 is covered while the first insulating layer of lid 33.Second insulating layer 37 can be by single-layer or multi-layer group
At.In addition, second insulating layer 37 can be distributed Bragg reflector.
First electrode pad 39a and second electrode pad 39b is located at 37 lower section of second insulating layer.First electrode pad 39a
It may pass through second insulating layer 37 and be connected to the first contact layer 35.In addition, second electrode pad 39b may pass through 37 He of second insulating layer
First insulating layer 33 is connected to the second contact layer 31.
First convex block 45a and the second convex block 45b is located at below first electrode pad 39a and second electrode pad 39b with quilt
It is connected respectively to first electrode pad 39a and second electrode pad 39b.First convex block 45a and the second convex block 45b can pass through painting
It covers to be formed.First convex block 45a and the second convex block 45b is electrically connected to the terminal of the circuit board of such as MC-PCB and has coplanar
End.In addition, first electrode pad 39a can be formed at horizontal plane identical with the horizontal plane of second electrode pad 39b, from
And the first convex block 45a and the second convex block 45b also may be formed on same plane.Therefore, the first convex block 45a and the second convex block 45b
It can height having the same.
Meanwhile mute convex block 45c can be between the first convex block 45a and the second convex block 45b.Mute convex block 45c can be with
One convex block 45a and the second convex block 45b is formed together to provide the passage of heat for the heat from semiconductor stack part 30 to be discharged.
Insulating layer 43 can cover the side surface of the first convex block 45a and the second convex block 45b.Insulating layer 43 can also cover mute convex
The side surface of block 45c.In addition, insulating layer 43 fill the space between the first convex block 45a, the second convex block 45b and mute convex block 45c with
Moisture is prevented to be externally entering semiconductor stack overlapping piece 30.Insulating layer 43 also covers first electrode pad 39a and second electrode pad
The side surface of 39b is to avoid first electrode pad 39a and second electrode pad 39b from the external environmental factor of such as moisture
It influences.Although insulating layer 43 can be configured to whole side surfaces of covering the first convex block 45a and the second convex block 45b, this hair
It is bright to be not limited to this.Selectively, insulating layer 43 can be covered except the side surface close to the end of the first convex block and the second convex block
Some regions other than the first convex block 45a and the second convex block 45b side surface.
In the present example embodiment, insulating layer 43 is shown as covering first electrode pad 39a and second electrode pad
The side surface of 39b, but the invention is not restricted to this.Selectively, another insulating layer can be used for covering first electrode pad 39a and
Second electrode pad 39b, insulating layer 43 may be formed at below another insulating layer.In this case, the first convex block 45a and
Second convex block 45b can pass through another insulating layer and be connected to first electrode pad 39a and second electrode pad 39b.
Wavelength shifter 51 can be located at the first conductive type upper semiconductor layer 25 with remaining 30 phase of semiconductor stack overlapping piece
Anti- top.Wavelength shifter 51 can contact the upper surface of the first conductive type upper semiconductor layer 25.Wavelength shifter 51 is not having
It can be phosphor sheet with a uniform thickness in conditional situation.Selectively, wavelength shifter 51 can be doped with
The substrate of impurity for wavelength convert, for example, sapphire substrates or silicon base.
In the present example embodiment, the side surface of semiconductor stack overlapping piece 30 is covered by protection insulating layer.Protect insulating layer
It may include for example, the first insulating layer 33 and/or second insulating layer 37.In addition, the first contact layer 35 can be by second insulating layer 37
It covers to be protected against the influence of external environment, the second contact layer 31 can be covered by the first insulating layer 33 and second insulating layer 37
To be protected against the influence of external environment.First electrode pad 39a and second electrode pad 39b are also protected by such as insulating layer 43
Shield.Therefore, it can prevent from deteriorating semiconductor stack overlapping piece 30 due to moisture.
Wavelength shifter 51 may be affixed to the first conductive type upper semiconductor layer 25 of wafer scale, then in chip separation process
It is separated together with protection insulating layer in the process.Therefore, the side surface of wavelength shifter 51 can be with protection insulating layer at one
On line.I.e., it is possible to flush the side surface of wavelength shifter 51 along straight line with the side surface of insulating layer is protected.In addition, wavelength
It the side surface of converter 51 can be with the side surface of insulating layer 43 on one wire.Therefore, the side of wavelength shifter 51 can be made
The side surface on surface, the side surface for protecting insulating layer and insulating layer 43 is flushed all along straight line.
Fig. 2 is the schematic cross sectional views of the light emission diode package member 200 of the second exemplary embodiment according to the present invention.
Referring to Fig. 2, LED encapsulation piece 200 is similar to according to the LED encapsulation piece 100 of exemplary embodiment above.But
In the present exemplary embodiment, the first convex block 65a and the second convex block 65b are formed in substrate 61.
Specifically, substrate 61 includes the through-hole formed therein that for having the first convex block 65a and the second convex block 65b respectively.Base
Bottom 61 is dielectric base, for example, sapphire substrates or silicon base, but not limited to this.With the first convex block 65a and the second convex block
The substrate 61 of 65b can be attached to first electrode pad 39a and second electrode pad 39b.In this case, in order to prevent
One electrode pad 39a and second electrode pad 39b is exposed to outside, insulating layer 49 can cover first electrode pad 39a and
The side surface of second electrode pad 39b and bottom surface.In addition, insulating layer 49 can have exposed first electrode pad 39a and
The opening of two electrode pad 39b, then other metal layer 67a, 67b are formed in the opening.Other metal layer 67a, 67b can be by connecing
Alloy, which belongs to, to be constituted.
Fig. 3 be include cross-sectional view according to the light-emitting diode (LED) module of the LED encapsulation piece 100 of the first exemplary embodiment.
Referring to Fig. 3, LED module includes circuit board 71 (for example, MC-PCB), LED encapsulation piece 100 and lens 81.Circuit board
71 (for example, MC-PCB) have for connection pad 73a, 73b that LED encapsulation piece 100 is mounted thereto.LED encapsulation piece 100
The first convex block 45a and the second convex block 45b (referring to Fig. 1) be connected respectively to connection pad 73a, 73b.
Multiple LED encapsulation pieces 100 may be mounted on circuit board 71, lens 81 can be set in LED encapsulation piece 100 with
Adjust the deflection of the light emitted from LED encapsulation piece 100.
According to the second exemplary embodiment, light emission diode package member 200 can replace LED encapsulation piece 100 and be mounted on electricity
On the plate of road.
Fig. 4 to Figure 12 shows manufacture according to the method for the LED encapsulation piece 100 of the first exemplary embodiment.In Fig. 5 to figure
In 10, (a) is plan view, is (b) cross-sectional view intercepted along the line A-A of (a).
Referring to Fig. 4, being formed in growth substrate 21 includes that the first conductive type semiconductor layer 25, active layer 27 and second are conductive
The semiconductor stack overlapping piece 30 of type semiconductor layer 29.Growth substrate 21 can be sapphire substrates, but not limited to this.Selectively,
Growth substrate 21 can be other kinds of hetero-substrates (heterogeneous substrate), for example, silicon base.First
Each of conductive-type semiconductor layer 25 and the second conductive type semiconductor layer 29 can be made of single-layer or multi-layer.In addition, active
Layer 27 can have single quantum or multi-quantum pit structure.
Compound semiconductor layer can pass through Organometallic Chemistry gas by III-N based compound semiconductor in growth substrate 21
Mutually deposition (MOCVD) or molecular beam epitaxy (MBE) formation.
Buffer layer (not shown) can be formed before forming compound semiconductor layer.Buffer layer is formed to mitigate growth substrate
Lattice mismatch between 21 and compound semiconductor layer, buffer layer can be by the GaN base material layers of such as gallium nitride or aluminium nitride
It is formed.
Referring to (a) and (b) of Fig. 5, semiconductor stack overlapping piece 30 is patterned to form chip (stack) separated region 30b
Pattern the second conductive type semiconductor layer 29 and active layer 27 to form the more of exposed the first conductive type semiconductor layer 25
A contact hole 30a.Semiconductor stack overlapping piece 30 can be made to pattern by photoetching process and etch process.
Chip separation region 30b is the region for LED encapsulation structure to be divided into single led packaging part, the first conductive type
The side surface of the side surface of semiconductor layer 25, the side surface of active layer 27 and the second conductive type semiconductor layer 29 is in chip Disengagement zone
Exposure on the 30b of domain.Advantageously, chip separation region 30b can be configured to expose substrate 21, without being restricted to this.
Multiple contact hole 30a can be circle, but not limited to this.Contact hole 30a can have various shapes.The second conductive type
Semiconductor layer 29 and active layer 27 are exposed to the side wall of multiple contact hole 30a.As indicated, contact hole 30a can have inclined side
Wall.
Referring to (a) and (b) of Fig. 6, the second contact layer 31 is formed on the second conductive type semiconductor layer 29.Second contact layer
31 are formed on the semiconductor stack overlapping piece 30 in addition to corresponding to the region of multiple contact hole 30a.
Second contact layer 31 may include transparent conductive oxide film (for example, tin indium oxide (ITO)) or reflective metal layer
(for example, silver-colored (Ag) or aluminium (Al)).Second contact layer 31 can be made of single-layer or multi-layer.Second contact layer 31 can also be constructed
It is shaped to and 29 Ohmic contact of the second conductive type semiconductor layer.
The second contact layer 31 can be formed before or after forming multiple contact hole 30a.
Referring to (a) and (b) of Fig. 7, the first insulating layer 33 is formed to cover the second contact layer 31.First insulating layer 33 can cover
Lid semiconductor stack overlapping piece 30 is exposed to the side surface of chip separation region 30b, while covering the side wall of multiple contact hole 30a.
Here, the first insulating layer 33 can have the opening 33a of the exposure the first conductive type semiconductor layer 25 in multiple contact hole 30a.
First insulating layer 33 can be made of single-layer or multi-layer (for example, silicon oxide film or silicon nitride film).Selectively, first
Insulating layer 33 can be by being formed by being alternately stacked the distributed Bragg reflector that the insulating layer with different refractivity is formed.
For example, the first insulating layer 33 can be by being alternately stacked SiO2/TiO2Or SiO2/Nb2O5It is formed.In addition, the first insulation can be formed
Layer 33 has high reflectivity to provide the thickness by adjusting each insulating layer to the wide wave-length coverage of blue and green light and feux rouges
Distributed Bragg reflector.
Referring to (a) and (b) of Fig. 8, the first contact layer 35 is formed on the first insulating layer 33.First contact layer 35 includes connecing
It touches the contact portion 35a for the first conductive type upper semiconductor layer 25 being exposed in contact hole 30a and connects contact portion 35a each other
The coupling part 35b connect.First contact layer 35 can be made of reflective metal layer, but not limited to this.
First contact layer 35 is formed on some regions of semiconductor stack overlapping piece 30, so that the first insulating layer 33 is exposed to half
On other regions without the first contact layer 35 of formation of conductor stack part 30.
Referring to (a) and (b) of Fig. 9, second insulating layer 37 is formed on the first contact layer 35.Second insulating layer 37 can be by list
Layer or multilayer (silicon oxide film or silicon nitride film) composition.In addition, second insulating layer 37 can be by having difference by being alternately stacked
The distributed Bragg reflector composition that the insulating layer of refractive index is formed.
Second insulating layer 37 can cover the first contact layer 35 while cover the first insulating layer 33.Second insulating layer 37 can also be covered
The side surface in the 30b of chip separation region of lid semiconductor stack overlapping piece 30.
Second insulating layer 37 has the opening 37a of the first contact layer 35 of exposure.In addition, second insulating layer 37 and the first insulation
Layer 33 is formed with the opening 37b of the second contact layer 31 of exposure.
0 (a) and (b) referring to Fig.1 forms first electrode pad 39a and second electrode pad in second insulating layer 37
39b.First electrode pad 39a passes through opening 37a and is connected to the first contact layer 35, and second electrode pad 39b passes through opening 37b and connects
It is connected to the second contact layer 31.
First electrode pad 39a is separated with second electrode pad 39b, in terms of top perspective first electrode pad 39a and
Each of second electrode pad 39b can have relatively large area, for example, 1/3 face of the area of no less than LED encapsulation piece
Product.
Referring to Fig.1 1, insulating layer 43 is formed on first electrode pad 39a and second electrode pad 39b.Insulating layer 43 covers
Lid first electrode pad 39a and second electrode pad 39b, and there is the groove of the upper surface of exposure electrode pad 39a and 39b.
In addition, insulating layer 43 can have the second insulating layer 37 being exposed between first electrode pad 39a and second electrode pad 39b
Groove.
Then, the first convex block 45a and the second convex block 45b are formed in the groove of insulating layer 43, it can be in the first convex block and
Mute convex block 45c is formed between two convex blocks.
Convex block can be formed by using metal material plating (for example, plating).If necessary, can also be formed for plating
The seed layer covered.
After forming the first convex block 45a and the second convex block 45b, insulating layer 43 can remove.For example, insulating layer 43 can be by such as
The polymer of photoresist is formed, and can be removed after forming convex block.Selectively, insulating layer 43 can be left to protect
The side surface of first convex block 45a and the second convex block 45b.
In the present example embodiment, insulating layer 43 is shown as being formed directly into the first pad electrode 39a and the second pad
On electrode 39b.In a further exemplary embodiment, another insulating layer can be formed to cover the electricity of first electrode pad 39a and second
Pole pad 39b.Another insulating layer can be configured to the opening with exposure first electrode pad 39a and second electrode pad 39b.
Then, the technique for forming insulating layer 43 and convex block can be performed.
Referring to Fig.1 2, growth substrate 21 is removed, wavelength shifter 51 is attached to the first conductive type semiconductor layer 25.It can lead to
Cross optical technology (for example, laser lift-off (LLO)), mechanical polishing or chemical etching removal growth substrate 21.
Then, anisotropic etching is carried out (for example, optical electro-chemistry to the surface of the exposure of the first conductive type semiconductor layer 25
(PEC) etch) to form coarse surface on exposed the first conductive type semiconductor layer 25.
Meanwhile the wavelength shifter of the phosphor sheet such as comprising phosphor can be attached to the first conductive type semiconductor layer
25。
Selectively, growth substrate 21 may include the impurity for converting the wavelength of the light generated in active layer 27.?
In this case, growth substrate 21 can be used as wavelength shifter 51.
Then, LED encapsulation structure is divided into single packaging part along chip separation region 30b, to provide completion
LED encapsulation piece 100.At this point, second insulating layer 37 is cut together with wavelength shifter 51, so that can be by 37 He of second insulating layer
The cutting planes of wavelength shifter 51 are formed on one wire.
Figure 13 is to show the cross-sectional view for manufacturing the method for the LED encapsulation piece 200 of the second exemplary embodiment according to the present invention.
Referring to Fig.1 3, in the method for the LED encapsulation piece 200 of manufacture according to the present exemplary embodiment, technique and above-mentioned system
The technique for making the method for LED encapsulation piece 100 is identical, until forming first electrode pad 39a and second electrode pad 39b (Figure 10
(a) and (b)).
After forming first electrode pad 39a and second electrode pad 39b, insulating layer 49 is formed to cover first electrode
Pad 39a and second electrode pad 39b.Insulating layer 49 can cover the side table of first electrode pad 39a and second electrode pad 39b
Face is to protect first electrode pad 39a and second electrode pad 39b.Insulating layer 49 has exposure first electrode pad 39a and the
The opening of two electrode pad 39b.Then other metal layers 67a, 67b are formed in the opening.Other metal layers 67a, 67b can be by connecing
Alloy, which belongs to, to be constituted.
Substrate 61 is joined to first electrode pad 39a and second electrode pad 39b.Substrate 61, which can have, could be formed with
The through-hole of one convex block 65a and the second convex block 65b.In addition, the first convex block and the second convex block can be formed as to have weldering at its end
Disk 69a, 69b.Substrate 61 with the first convex block 65a, the second convex block 65b, pad 69a and pad 69b can be prepared separately, and connect
Close the chip with first electrode pad 39a and second electrode pad 39b.
Then, it as described in referring to Fig.1 2, removes growth substrate 21 and wavelength shifter 51 can be attached to the first conduction
LED encapsulation structure is then divided into single LED encapsulation piece by type semiconductor layer 25.Therefore it provides completion as shown in Figure 2
LED encapsulation piece 200.
Figure 14 is the cross-sectional view of the LED encapsulation piece 300 of third exemplary embodiment according to the present invention.
Referring to Fig.1 4, LED encapsulation piece 300 may include be divided into multiple luminescence units (illustrate only here two shine it is single
First S1, S2) semiconductor stack overlapping piece 130, the first contact layer 135, the second contact layer 131, the first insulating layer 133, second insulation
Layer 137, the connector for first electrode pad 139a, second electrode pad 139b, being serially connected neighbouring luminescence unit
139c, the first convex block 145a and the second convex block 145b.In addition, LED encapsulation piece 300 may include third insulating layer 141, insulating layer
143, mute convex block 145c, wavelength shifter 151 and other metal layers 140a, 140b.
Semiconductor stack overlapping piece 130 includes the first conductive type upper semiconductor layer 125, active layer 127 and the second conductive type lower half
Conductor layer 129.The semiconductor stack overlapping piece 130 of the present exemplary embodiment is similar to the semiconductor stack overlapping piece 30 described in Fig. 1, this
In will omit detailed description thereof.
Each of luminescence unit S1, S2 have extend through the second conductive type lower semiconductor layer 129 and active layer 127 with
Multiple contact hole 130a (referring to (b) of Figure 18) of exposure the first conductive type upper semiconductor layer, the contact exposure of the first contact layer 135
The first conductive type upper semiconductor layer 125 in multiple contact holes.Luminescence unit S1, S2 pass through unit separated region 130b (ginseng
See (b) of Figure 18) it is separated from each other.
Second contact layer 131 contacts the second conductive type lower semiconductor layer 129 of each luminescence unit S1, S2.Second contact
Layer 131 includes reflective metal layer to reflect the light generated in active layer 127.In addition, the second contact layer 131 can be formed and second
The Ohmic contact of conductivity type lower semiconductor layer 129.
First insulating layer 133 covers the second contact layer 131.In addition, the first insulating layer 133 covers semiconductor stack overlapping piece 130
The side wall being exposed in multiple contact hole 130a.In addition, the first insulating layer 133 can cover the side of each luminescence unit S1, S2
Surface.First insulating layer 133 makes the first contact layer 135 and the second contact layer 131 insulate, while making to be exposed to multiple contact holes
The second conductive type lower semiconductor layer 129 and active layer 127 and the first contact layer 135 in 130a insulate.First insulating layer 133 can
It is made of single-layer or multi-layer (for example, silicon oxide film or silicon nitride film).In addition, the first insulating layer 133 can be by passing through alternately heap
The folded insulating layer with different refractivity is (for example, SiO2/TiO2Or SiO2/Nb2O5) formed distributed Bragg reflector group
At.
First contact layer 135 is located at the lower section of the first insulating layer 133, and pass through in each luminescence unit S1, S2 multiple connects
The first insulating layer 133 in contact hole 130a contacts the first conductive type upper semiconductor layer 125.First contact layer 135 includes contact
The contact portion 135a of the first conductive type upper semiconductor layer 125 and coupling part 135b that contact portion 135a is connected to each other.
Therefore, contact portion 135a is electrically connected to each other by coupling part 135b.First below each luminescence unit S1, S2 connects
Contact layer 135 is separated from each other and is formed in the lower section in some regions of the first insulating layer 133.First contact layer 135 can be by reflection gold
Belong to layer composition.
Second insulating layer 137 covers the first contact layer 135 below the first contact layer 135.In addition, second insulating layer 137
The first insulating layer 133 can be covered while covering the side surface of each luminescence unit S1, S2.Second insulating layer 137 can by single layer or
Multilayer composition.Selectively, second insulating layer 137 can be made of distributed Bragg reflector.
First electrode pad 139a and second electrode pad 139b is located at 137 lower section of second insulating layer.First electrode pad
139a may pass through the first contact layer 135 that second insulating layer 137 is connected to the first luminescence unit S1.In addition, second electrode pad
139b may pass through second insulating layer 137 and the first insulating layer 133 is connected to the second contact layer 131 of the second luminescence unit S2.
Connector 139c, which is located at 137 lower section of second insulating layer and passes through second insulating layer 137, makes two neighbouring luminous lists
First S1, S2 are electrically connected to each other.It is adjacent that connector 139c can be such that the second contact layer 131 of a luminescence unit S1 is connected to
Another luminescence unit S2 the first contact layer 135 so that two luminescence units S1, S2 are serially connected.
In the present example embodiment, two luminescence units S1, S2 are shown.It should be understood, however, that two or more
Multiple luminescence units can be serially connected by multiple connector 139c.Here, first electrode pad 139a, 139b can be with
It is connected in series to positioned at the opposite end of such serial array.
Meanwhile third insulating layer 141 can be at first electrode pad 139a, second electrode pad 139b and connector 139c
Side's covering first electrode pad 139a, second electrode pad 139b and connector 139c.Third insulating layer 141 can have exposure the
The opening of one electrode pad 139a and second electrode pad 139b.Third insulating layer 141 can be by silicon oxide film or silicon nitride film shape
At.
First convex block 145a and the second convex block 145b are located at first electrode pad 139a and second electrode pad 139b
Lower section.First convex block 145a and the second convex block 145b can be formed by plating.First convex block 145a and the second convex block 145b is electricity
It is connected to the terminal of circuit board (for example, MC-PCB), and there is end coplanar with each other.In addition, first electrode pad 139a can
To be formed on horizontal plane identical with the horizontal plane of second electrode pad 139b, so that the first convex block 145a and the second convex block
145b is additionally formed on same plane.Therefore, the first convex block 145a and the second convex block 145b can height having the same.
Other metal layers 140a, 140b can be set between the first convex block 145a and first electrode pad 139a and
Between two convex block 145b and second electrode pad 139b.Here, other metal layers 140a, 140b is set so that first electrode pad
139a and second electrode pad 139b are formed as higher than connector 139c, and other metal layers 140a, 140b can be located at the
The open interior of three insulating layers 141.First electrode pad 139a, second electrode pad 139b and other metal layers 140a, 140b
Constitute final electrode pad.
Meanwhile mute convex block 145c can be between the first convex block 145a and the second convex block 145b.Mute convex block 145c can be with
One convex block 145a and the second convex block 145b is formed together to provide the passage of heat for ejecting selfluminous cell S1, S2.It is mute convex
Block 145c is separated by third insulating layer 141 with connector 139c.
Insulating layer 143 can cover the side surface of the first convex block 145a and the second convex block 145b.Insulating layer 143 can also cover mute
The side surface of convex block 145c.In addition, insulating layer 143 fill the first convex block 145a, the second convex block 145b and third convex block 145c it
Between space to prevent moisture to be externally entering semiconductor package part 130.Although it is convex that insulating layer 143 can be configured to covering first
The entire side surface of block 145a and the second convex block 145b, but the invention is not restricted to this.Selectively, insulating layer 143 can cover
First convex block 145a's and the second convex block 145b removes some regions close to the side surface of the end of the first convex block and the second convex block
Side surface in addition.
Wavelength shifter 151 can be located on luminescence unit S1, S2.Wavelength shifter 151 can contact the first conductive type upper half
The upper surface of conductor layer 125.Wavelength shifter 151 goes back capping unit separated region 130b and chip separation region.Wavelength convert
Device 151 can be phosphor sheet with a uniform thickness, without limited to this.Selectively, wavelength shifter 151, which can be, mixes
The miscellaneous substrate for having the impurity for wavelength convert, for example, sapphire substrates or silicon base.
In the present embodiment, the side surface of luminescence unit S1, S2 can be covered by protection insulating layer.Protection insulating layer may include
For example, the first insulating layer 133 and/or second insulating layer 137.In addition, the first contact layer 135 can be covered by second insulating layer 137
To be protected against the influence of external environment, the second contact layer 131 can be covered by the first insulating layer 133 and second insulating layer 137
To be protected against the influence of external environment.In addition, first electrode pad 139a and second electrode pad 139b are also by such as
The protection of three insulating layers 141.Accordingly it is possible to prevent deteriorating luminescence unit S1, S2 due to moisture.
Wavelength shifter 151 may be affixed to the first conductive type upper semiconductor layer 125 of wafer scale, then separate work in chip
It is separated together with protection insulating layer during skill (or packaging part separating technology).Therefore, the side surface of wavelength shifter 151
It can be with protection insulating layer on one wire.In addition, the side surface of wavelength shifter 151 can be with the side surface of insulating layer 143
On one wire.
Figure 15 is the schematic cross sectional views of the light emission diode package member 400 of the 4th exemplary embodiment according to the present invention.
Referring to Fig.1 5, LED encapsulation piece 400 is similar to according to the LED encapsulation piece 300 of exemplary embodiment above.But
In the present exemplary embodiment, the first convex block 165a and the second convex block 165b are formed in substrate 161.
Specifically, substrate 161 includes being respectively provided with the first convex block 165a's and the second convex block 165b being formed in it
Through-hole.Substrate 161 is dielectric base, for example, sapphire substrates or silicon base, but it is not limited to this.
Substrate 161 with the first convex block 165a and the second convex block 165b can be attached to third insulating layer 141, the first convex block
165a and the second convex block 165b can be connected respectively to first electrode pad 139a and second electrode pad 139b.Here, first is convex
Block 165a and the second convex block 165b can be joined respectively to other metal layers 140a, 140b.
Figure 16 be on circuit boards include LED die according to the LED encapsulation piece 300 of third exemplary embodiment
The cross-sectional view of block.
Referring to Fig.1 6, LED module includes circuit board 171, LED encapsulation piece 300 and lens 181 for example, MC-PCB.Circuit
Plate 171 (for example, MC-PCB) has for connection pad 173a, 173b that LED encapsulation piece 300 is mounted thereto.LED encapsulation
First convex block 145a of part 300 and the second convex block 145b (referring to Figure 14) is connected respectively to connection pad 173a, 173b.
Multiple LED encapsulation pieces 300 are mountable on circuit board 171, and lens 181 may be provided in LED encapsulation piece 300 to adjust
Save the deflection of the light emitted from LED encapsulation piece 300.
In other exemplary embodiments of the invention, light emission diode package member 400 can replace LED encapsulation piece 300 to be mounted on circuit
On plate.
Figure 17 to Figure 25 shows manufacture according to the method for the LED encapsulation piece 300 of third exemplary embodiment.Figure 18 extremely
In Figure 23, (a) is plan view, is (b) cross-sectional view intercepted along the line A-A of (a).
Referring to Fig.1 7, being formed in growth substrate 121 includes the first conductive type semiconductor layer 125, active layer 127 and second
The semiconductor stack overlapping piece 130 of conductive-type semiconductor layer 129.Growth substrate 121 and semiconductor stack overlapping piece 130 are described with referring to Fig. 4
Substrate 21 and semiconductor stack overlapping piece 30 it is similar, therefore thereof will be omitted detailed description thereofs.
8 (a) and (b) referring to Fig.1 makes the patterning of semiconductor stack overlapping piece 130 to form chip (packaging part) separated region
130c and unit separated region 130b, while it is luminous to be formed to pattern the second conductive type semiconductor layer 129 and active layer 127
Cell S 1, S2, each luminescence unit S1, S2 have multiple contact hole 130a of exposure the first conductive type semiconductor layer 125.It can lead to
Crossing photoetching process and etch process patterns semiconductor stack overlapping piece 130.
Chip separation region 130c is the region for LED encapsulation structure to be divided into single LED encapsulation piece, and first is conductive
The side surface exposure of the side surface of type semiconductor layer 125, the side surface of active layer 127 and the second conductive type layer semiconductor layer 129
At the 130c of chip separation region.Advantageously, chip separation region 130c and unit separated region 130b can be configured to expose
Substrate 121, and it is without being limited thereto.
Multiple contact hole 130a can have circle, but be not limited to this.Contact hole 130 can have various shape.Second leads
Electric type semiconductor layer 129 and active layer 127 are exposed to the side wall of multiple contact hole 130a.Contact hole 130a can have inclined side
Wall.
9 (a) and (b) referring to Fig.1 forms the second contact layer 131 on the second conductive type semiconductor layer 129.Each
Second is formed on the semiconductor stack overlapping piece 130 other than corresponding to the region of multiple contact hole 130a of luminescence unit S1, S2
Contact layer 131.
Second contact layer 131 may include such as the transparent conductive oxide film of tin indium oxide (ITO) or such as silver-colored (Ag) or aluminium
(Al) reflective metal layer.Second contact layer 131 can be made of single-layer or multi-layer.Second contact layer 131 be also configured to
The second conductive type semiconductor layer 129 forms Ohmic contact.
The second contact layer 131 can be formed before or after forming multiple contact hole 130a.
Referring to (a) and (b) of Figure 20, the first insulating layer 133 is formed to cover the second contact layer 131.First insulating layer 133
The side surface of each luminescence unit S1, S2 can be covered while covering the side wall of multiple contact hole 130a.Here, the first insulating layer
133 can have the opening 133a of the exposure the first conductive type semiconductor layer 125 in multiple contact hole 130a.
The first insulating layer 133 can be made of the single-layer or multi-layer of such as silicon oxide film or silicon nitride film.In addition, can be by passing through
It is alternately stacked the distributed Bragg reflector that the insulating layer with different refractivity is formed and forms the first insulating layer 133.Example
It such as, can be by being alternately stacked SiO2/TiO2Or SiO2/Nb2O5To form the first insulating layer 133.In addition, the first insulation can be formed
Layer 133 has high reflectivity to provide the thickness by adjusting each insulating layer to the wide wave-length coverage of blue and green light and feux rouges
Distributed Bragg reflector.
Referring to (a) and (b) of Figure 21, the first contact layer 135 is formed on the first insulating layer 133.In each luminescence unit
The first contact layer 135 is formed on S1, S2, the first contact layer 135 includes the contact the first conductive type being exposed in contact hole 130a
The contact portion 135a of the upper semiconductor layer 125 and coupling part 135b that contact portion 135a is connected to each other.First contact layer
135 can be made of reflective metal layer, but not limited to this.
The first contact layer 135 is formed on some regions of each transmitting unit S1, S2, so that in semiconductor stack overlapping piece
The first insulating layer 133 of exposure at 130 other regions without forming the first contact layer 135.
Referring to (a) and (b) of Figure 22, second insulating layer 137 is formed on the first contact layer 135.It can be by such as silica
The single-layer or multi-layer of film or silicon nitride film forms second insulating layer 137.It selectively, can be by there is difference by being alternately stacked
The distributed Bragg reflector that the insulating layer of refractive index is formed forms second insulating layer 137.
Second insulating layer 137 can cover the first contact layer 135 while cover the first insulating layer 133.Second insulating layer 137 is also
The side surface of each luminescence unit S1, S2 can be covered.In addition, can be in chip separation region 130c and unit separated region 130b
Fill second insulating layer 137.
Second insulating layer 137 has the opening 137a of the first contact layer 135 of exposure each luminescence unit S1, S2.In addition,
Second insulating layer 137 and the first insulating layer 133 are formed with the opening 137b of the second contact layer 131 of exposure.
Referring to Figure 23 (a) and (b), in second insulating layer 137 formation connector 139c, first electrode pad 139a and
Second electrode pad 139b.First electrode pad 139a is connected to the first contact of the first luminescence unit S1 by the 137a that is open
Second electrode pad 139b is connected to the second contact layer 131 of the second luminescence unit S2 by layer 135 by the 137b that is open.In addition,
Connector 139c will be adjacent to the first contact layer 135 and the second contact layer 131 of luminescence unit S1, S2 by opening 137a, 137b
It is serially connected.
Referring to Figure 24, it is exhausted that third is formed on first electrode pad 139a, second electrode pad 139b and connector 139c
Edge layer 141.Third insulating layer 141 covers first electrode pad 139a, second electrode pad 139b and connector 139c, and has
The groove of the upper surface of exposure electrode pad 139a, 139b.Meanwhile third insulating layer 141 can have and be formed in its groove
Other metal layers 140a, 140b.Other metal layers 140a, 140b increase the height of electrode pad 139a, 139b, so that finally
Electrode pad can have height more higher than connector 139c.Other metal layers can be formed before forming third insulating layer 141
140a,140b.It the upper surface of other metal layers 140a, 140b can be substantially coplanar with the upper surface of third insulating layer 141.
Referring to Figure 25, patterned insulating layer 143 is formed on third insulating layer 141.Patterned insulating layer 143 has
Exposure first electrode pad 139a and second electrode pad 139b upside for example, other metal layers 140a, 140b groove.Separately
Outside, patterned insulating layer 143 can have the insulating layer between exposed first electrode pad 139a and second electrode pad 139b
141 groove.
Then, the first convex block 145a and the second convex block 145b are formed in the groove of insulating layer 143, can in the first convex block and
Mute convex block 145c is formed between second convex block.
Convex block can be formed for example, by the plating of plating.As needed, the seed layer for plating can also be formed.
After forming the first convex block 145a and the second convex block 145b, insulating layer 143 can be removed.For example, insulating layer 143 can
It is formed, and can be removed after forming convex block by the polymer of such as photoresist.Selectively, insulating layer can be retained
143 with the side surface of protection the first convex block 145a and the second convex block 145b.
Referring to Figure 26, growth substrate 121 is removed, wavelength shifter 151 is then attached to luminescence unit S1, S2.It can lead to
Optical technology, mechanical polishing or the chemical etching of such as laser lift-off (LLO) are crossed to remove growth substrate 121.
Then, the surface of the exposure of the first conductive type semiconductor layer 125 is made to be subjected to the anisotropy erosion of such as PEC etching
It carves, to form rough surface on exposed the first conductive type semiconductor layer 125.
Meanwhile the wavelength shifter 151 of the phosphor sheet such as comprising phosphor can be attached to the first conductive type and partly led
Body layer 125.
Selectively, growth substrate 121 may include the impurity for converting the wavelength of the light generated in active layer 127.
In this case, growth substrate 121 can be used as wavelength shifter 151.
Then, LED encapsulation structure is divided into single packaging part along chip separation region 130c, to provide completion
LED encapsulation piece 300.At this point, second insulating layer 137 and wavelength shifter 151 are cut together, so that 137 He of second insulating layer
The cutting planes of wavelength shifter 151 may be formed on straight line.
Figure 27 is to explain the cross-sectional view for manufacturing the method for the LED encapsulation piece 400 of the 4th exemplary embodiment according to the present invention.
Referring to Figure 27, in manufacturing the method according to the LED encapsulation piece 400 of the present embodiment, technique and above-mentioned (Figure 24) are made
The technique for making the method for LED encapsulation piece 300 is identical, until forming third insulating layer 141 and other metal layers 140a, 140b.
In the present example embodiment, third insulating layer 141 is arrived into the engagement of substrate 161.Substrate 161, which can have, wherein may be used
To form the through-hole of the first convex block 165a and the second convex block 165b.In addition, the first convex block 165a and the second convex block 165b can be at them
End is formed with pad (not shown).In addition, substrate 161 can have part to be formed on the lower surface thereof and by metal material
The groove of 165c filling.Metal material 165c improves substrate heat dissipation.
Selectively, the substrate 161 with the first convex block 165a and the second convex block 165b can be prepared separately, and will have
The substrate 161 of first convex block 165a and the second convex block 165b are joined to first electrode pad 139a and second electrode pad
The chip of 139b.The first convex block 165a and the second convex block 165b can be electrically connected to the electricity of first electrode pad 139a and second respectively
Pole pad 139b.
Then, referring to as described in Figure 26, growth substrate 121 is removed, and wavelength shifter 151 can be attached to the list that shines
LED encapsulation structure is then divided into single LED encapsulation piece by first S1, S2.Therefore it provides the LED of the completion described in Figure 15
Packaging part 400.
Similarly, the exemplary embodiment of the present invention provides can be not using traditional lead frame or printed circuit
The wafer scale LED encapsulation piece being formed directly into the case where plate on the circuit board for module.Therefore, LED encapsulation piece can have
High efficiency simultaneously can show improved heat dissipation, while reduce time and the cost for manufacturing the LED encapsulation piece.In addition,
LED module with LED encapsulation piece mounted thereto can have high efficiency and can show improved heat dissipation.
In addition, LED encapsulation piece may include the multiple luminescence units being serially connected and the battle array reversely with each other being connected in parallel
Column.In addition, multiple luminescence units can connect into bridge rectifier, and it can be used to form bridge rectifier.Therefore, including LED is sealed
The LED module of piece installing can operate in the case where not individual AC/DC converter.
The present invention is described referring to some exemplary embodiments although having been combined attached drawing, for those skilled in the art
Member will be apparent that, can make various modifications and change to the present invention without departing from the spirit and scope of the present invention.
Also, it should be understood that some features of some embodiment may be used also without departing from the spirit and scope of the present invention
It is applied to other embodiments.It is therefore to be understood that embodiment is only supplied to those skilled in the art by illustrating, give
Embodiment is out to be supplied to those skilled in the art for full disclosure of the invention, and thorough understanding of the present invention is supplied to
Those skilled in the art.To, it is intended that the present invention covers the modifications and variations, as long as the modifications and variations are fallen into
In the range of claim and its equivalent.