CN105575990A - Wafer-level light emitting diode package and method of fabricating the same - Google Patents

Abstract

Exemplary embodiments of the present invention provide a wafer level light emitting diode (LED) package and a method of manufacturing the same. The LED package includes: a semiconductor stack including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer; a plurality of contact holes arranged in the second conductivity type semiconductor layer and the active layer, contacting The hole exposes the first conductive type semiconductor layer; the first bump is arranged on the first side of the semiconductor stack, and the first bump is electrically connected to the first conductive type semiconductor layer through a plurality of contact holes; the second bump is arranged On the first side of the semiconductor stack, the second bump is electrically connected to the second conductive type semiconductor layer and the protective insulating layer, covering sidewalls of the semiconductor stack.

Description

Wafer level light emitting diode package and manufacturing method thereof

This application is a divisional application of Application No. 201180046150.0 with the filing date of September 5, 2011, entitled "Wafer-Level Light-Emitting Diode Package and Manufacturing Method" submitted to the State Intellectual Property Office of China.

technical field

The present invention relates to a light-emitting diode package and its manufacturing method, more specifically, to a wafer-level light-emitting diode package and its manufacturing method.

Background technique

A light emitting diode (LED) is a semiconductor device including an N-type semiconductor and a P-type semiconductor and emitting light through recombination of holes and electrons. Such LEDs have been used in a wide range of applications such as display devices, traffic lights, and backlight units. In addition, considering potential advantages of lower power consumption and longer life than current electric bulbs or fluorescent lamps, the application range of LEDs has been expanded to general lighting by replacing current incandescent lamps and fluorescent lamps.

LEDs can be used in LED modules. The LED module is manufactured through a process of manufacturing LED chips at a wafer level, a packaging process, and a modulation process. Specifically, a semiconductor layer is grown on a substrate such as a sapphire substrate, undergoes a wafer-level patterning process to manufacture LED chips with electrode pads, and is then divided into individual chips (chip manufacturing process). Then, after individual chips are mounted on a lead frame or printed circuit board, the electrode pads are electrically connected to lead terminals by bonding wires, and the LED chips are covered by a molding member, thereby providing an LED package (packaging process). Then, the LED package is mounted on a circuit board such as a metal core printed circuit board (MC-PCB), thereby providing an LED module such as a light source module (modular process).

During the encapsulation process, a case and/or a molding member may be provided to the LED chip to protect the LED chip from the external environment. In addition, a phosphor may be included in the molding member to convert light emitted from the LED chip so that the LED package may emit white light, thereby providing a white LED package. Such a white LED package may be mounted on a circuit board such as MC-PCB, and a secondary lens may be provided to the LED package to adjust directional characteristics of light emitted from the LED package, thereby providing a desired white LED module.

However, miniaturization and satisfactory heat dissipation of conventional LED packages including lead frames or printed circuit boards may be difficult to achieve. In addition, the luminous efficiency of the LED may be deteriorated due to absorption of light by a lead frame or a printed circuit board, resistance heat due to lead terminals, and the like.

In addition, a chip manufacturing process, a packaging process, and a modular process may be performed separately, which increases time and cost for manufacturing an LED module.

Meanwhile, alternating current (AC) LEDs have been produced and put on the market. ACLEDs include LEDs that are connected directly to an AC power source to allow continuous light emission. One example of an AC LED that can be used by connecting directly to a high voltage AC power source is disclosed in US Patent No. 7,417,259 to Sakai et al.

According to US Pat. No. 7,417,259, LED elements are arranged in a two-dimensional pattern on an insulating substrate (eg, a sapphire substrate) and connected in series to form an LED array. The arrays of LEDs are connected in series with each other, thereby providing a light emitting device that can operate at high voltages. In addition, such LED arrays can be connected in antiparallel to each other on a sapphire substrate, thereby providing a single-chip light emitting device that can be operated with AC power to continuously emit light.

Since the AC-LED includes a light emitting unit on a growth substrate (for example, on a sapphire substrate), the AC-LED limits the structure of the light emitting unit and may limit improvement in light extraction efficiency. Accordingly, investigations have been conducted on light emitting diodes (for example, AC-LEDs based on a substrate separation process and including light emitting cells connected to each other in series).

Contents of the invention

technical problem

Exemplary embodiments of the present invention provide a wafer level LED package and a manufacturing method thereof that may be directly formed in a module of a circuit board without using a conventional lead frame or a printed circuit board.

Exemplary embodiments of the present invention also provide a wafer level LED package having high efficiency and exhibiting improved heat dissipation and a method of manufacturing the same.

Exemplary embodiments of the present invention also provide a method of manufacturing an LED package that can reduce manufacturing time and cost of an LED module.

Exemplary embodiments of the present invention also provide an LED module having high efficiency and exhibiting improved heat dissipation and a method of manufacturing the same.

Exemplary embodiments of the present invention also provide a wafer level light emitting diode package including a plurality of light emitting units and which can be directly formed in a module of a circuit board without using a conventional lead frame or a printed circuit board, and the same. Manufacturing method.

Additional aspects of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Technical solutions

An exemplary embodiment of the present invention discloses a light emitting diode including: a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer. The source layer, the first semiconductor layer and the second semiconductor layer have different conductivity types; the first contact layer is arranged on the first semiconductor layer; the second contact layer is arranged on the second semiconductor layer; the first insulating layer covers The side walls of the active layer and the second semiconductor layer and the second contact layer are in contact with the first contact layer, and the first insulating layer includes a first opening exposing the first semiconductor layer and a second opening exposing the second contact layer; Two insulating layers, arranged on the first insulating layer; first bumps, arranged on the first side of the semiconductor stack, the first bumps are electrically connected to the first contact layer; second bumps, arranged on the semiconductor stack The second bump is electrically connected to the second contact layer on the first side of the first bump; and a third insulating layer is disposed on side surfaces of the first bump and the second bump.

An exemplary embodiment of the present invention discloses an LED package including: a semiconductor stack including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a plurality of contact holes, disposed in the second conductivity type semiconductor layer and the active layer, the contact holes exposing the first conductivity type semiconductor layer; the first bumps disposed on the first side of the semiconductor stack, the first bumps being exposed through the plurality of contact holes electrically connected to the first conductive type semiconductor layer; second bumps arranged on the first side of the semiconductor stack, the second bumps being electrically connected to the second conductive type semiconductor layer; and a protective insulating layer covering the semiconductor stack side wall.

Exemplary embodiments of the present invention also disclose a light emitting diode module including the LED package according to the above exemplary embodiments. The LED module may include: a circuit board; an LED package mounted on the circuit board; and a lens adjusting a direction angle of light emitted from the LED package.

Exemplary embodiments of the present invention also disclose a method of manufacturing the LED package. The method includes: forming a semiconductor stack including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on a first substrate; patterning the semiconductor stack to form a chip isolation region; making the second conductive type type semiconductor layer and the active layer to form a plurality of contact holes exposing the first conductivity type semiconductor layer; form a protective insulating layer covering the sidewall of the semiconductor stack in the chip isolation region; and form a semiconductor stack on the the first bump and the second bump. The first bump is electrically connected to the first conductive type semiconductor layer through a plurality of contact holes, and the second bump is electrically connected to the second conductive type semiconductor layer.

Exemplary embodiments of the present invention also disclose a light emitting diode package. The LED package includes: a plurality of light emitting units, each light emitting unit including a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer; a plurality of contact holes, arranged in the second conductive type semiconductor layer of each light emitting unit In the layer and the active layer, the contact hole exposes the first conductivity type semiconductor layer of each light emitting unit; the protective insulating layer covers the sidewall of each light emitting unit; the connector is located on the first side of the light emitting unit, and electrically connecting two adjacent light-emitting units to each other; a first bump arranged on a first side of the light-emitting units and electrically connected to the first conductive type semiconductor layer through a plurality of contact holes of the first light-emitting units of the light-emitting units; and a second bump arranged on the first side of the light emitting unit and electrically connected to the second conductive type semiconductor layer of the second light emitting unit of the light emitting unit.

Exemplary embodiments of the present invention also disclose a light emitting diode module including the LED package described above. The module includes: a circuit board; an LED package disposed on the circuit board; and a lens adjusting a direction angle of light emitted from the LED package.

Exemplary embodiments of the present invention also disclose a method of manufacturing an LED package including a plurality of light emitting units. The method includes: forming a semiconductor stack including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on a first substrate; patterning the semiconductor stack to form a chip separation region and a light emitting unit separation region ; patterning the second conductivity type semiconductor layer and the active layer to form a plurality of light emitting units, each light emitting unit having a plurality of contact holes exposing the first conductivity type semiconductor layer; A protective insulating layer for sidewalls in the light emitting unit separation region; forming a connection piece connecting adjacent light emitting units to each other in series; and forming a first bump and a second bump on the plurality of light emitting units. Here, the first bump is electrically connected to the first conductive type semiconductor layer through a plurality of contact holes of the first light emitting unit of the light emitting unit, and the second bump is electrically connected to the second conductive type semiconductor layer of the second light emitting unit of the light emitting unit. .

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Description of drawings

The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention and are included to provide a further understanding of the invention and are incorporated in and constitute an integral part of this specification. part.

FIG. 1 is a schematic cross-sectional view of a light emitting diode package according to a first exemplary embodiment of the present invention.

2 is a schematic cross-sectional view of a light emitting diode package according to a second exemplary embodiment of the present invention.

3 is a cross-sectional view of a light emitting diode module including the light emitting diode package according to the first exemplary embodiment.

4 to 12 illustrate a method of manufacturing a light emitting diode package according to a first exemplary embodiment, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A in FIGS. 5 to 10 .

13 is a cross-sectional view illustrating a method of manufacturing a light emitting diode package according to a second exemplary embodiment of the present invention.

14 is a schematic cross-sectional view of a light emitting diode package according to a third exemplary embodiment of the present invention.

15 is a schematic cross-sectional view of a light emitting diode package according to a fourth exemplary embodiment of the present invention.

16 is a cross-sectional view of a light emitting diode module including a light emitting diode package according to a third exemplary embodiment.

17 to 26 illustrate a method of manufacturing a light emitting diode package according to a third exemplary embodiment, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A in FIGS. 18 to 23 .

27 is a cross-sectional view illustrating a method of manufacturing a light emitting diode package according to a fourth exemplary embodiment of the present invention.

detailed description

The present invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals denote like elements in the drawings.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

Fig. 1 is a schematic cross-sectional view of an LED package 100 according to a first exemplary embodiment of the present invention.

1, the LED package 100 may include a semiconductor stack 30, a first contact layer 35, a second contact layer 31, a first insulating layer 33, a second insulating layer 37, a first electrode pad 39a, a second electrode pad The disk 39b, the first bump 45a and the second bump 45b. The LED package 100 may further include an insulating layer 43 , a dummy bump 45 c and a wavelength converter 51 .

The semiconductor stack 30 includes a first conductive type upper semiconductor layer 25 , an active layer 27 and a second conductive type lower semiconductor layer 29 . The active layer 27 is disposed between the upper semiconductor layer 25 and the lower semiconductor layer 29 .

The active layer 27, the upper semiconductor layer 25, and the lower semiconductor layer 29 may be composed of a III-N-based compound semiconductor such as (Al, Ga, In)N semiconductor. Each of the upper semiconductor layer 25 and the lower semiconductor layer 29 may be a single layer or a multilayer. For example, the upper semiconductor layer 25 and/or the lower semiconductor layer 29 may include a superlattice layer in addition to the contact layer and the cladding layer. The active layer 27 may have a single quantum well structure or a multiple quantum well structure. The first conductivity type may be n-type, and the second conductivity type may be p-type. Optionally, the first conductivity type may be p-type, and the second conductivity type may be n-type. Since the upper semiconductor layer 25 may be formed of an n-type semiconductor layer having relatively low specific resistance, the upper semiconductor layer 25 may have a relatively thick thickness. Accordingly, a rough surface R may be formed on the upper surface of the upper semiconductor layer 25 , wherein the rough surface R increases extraction efficiency of light generated in the active layer 27 .

The semiconductor stack 30 has a plurality of contact holes 30a passing through the second conductivity type lower semiconductor layer 29 and the active layer 27 to expose the first conductivity type upper semiconductor layer (see (b) in FIG. 35 contacts the first conductive type upper semiconductor layer 25 exposed in the plurality of contact holes.

The second contact layer 31 contacts the second conductive type lower semiconductor layer 29 . The second contact layer 31 includes a reflective metal layer to reflect light generated in the active layer 27 . In addition, the second contact layer 31 may form an ohmic contact with the second conductive type lower semiconductor layer 29 .

The first insulating layer 33 covers the second contact layer 31 . In addition, the first insulating layer 33 covers sidewalls of the semiconductor stack 30 exposed in the plurality of contact holes 30a. In addition, the first insulating layer 33 may cover side surfaces of the semiconductor stack 30 . The first insulating layer 33 insulates the first contact layer 35 from the second contact layer 31, and simultaneously insulates the second conductive type lower semiconductor layer 29 and the active layer 27 exposed in the plurality of contact holes 30a from the first contact layer 35. . The first insulating layer 33 may be composed of a single layer or multiple layers (for example, a silicon oxide film or a silicon nitride film). Alternatively, the first insulating layer 33 may be composed of a distributed Bragg reflector formed by alternately stacking insulating layers having different refractive indices, such as SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ .

The first contact layer 35 is located under the first insulating layer 33 and passes through the first insulating layer 33 in the plurality of contact holes 30 a to contact the first conductive type upper semiconductor layer 25 . The first contact layer 35 includes a contact portion 35 a contacting the first conductive type upper semiconductor layer 25 and a connection portion 35 b connecting the contact portions 35 a to each other. Accordingly, the contact portions 35a are electrically connected to each other through the connection portion 35b. The first contact layer 35 is formed under some regions of the first insulating layer 33 and may consist of a reflective metal layer.

The second insulating layer 37 covers the first contact layer 35 below the first contact layer 35 . In addition, the second insulating layer 37 covers the side surfaces of the semiconductor stack 30 while covering the first insulating layer 33 . The second insulating layer 37 may consist of a single layer or multiple layers. In addition, the second insulating layer 37 may be a distributed Bragg reflector.

The first electrode pad 39 a and the second electrode pad 39 b are located under the second insulating layer 37 . The first electrode pad 39 a may be connected to the first contact layer 35 through the second insulating layer 37 . In addition, the second electrode pad 39 b may be connected to the second contact layer 31 through the second insulating layer 37 and the first insulating layer 33 .

The first bump 45a and the second bump 45b are located under the first electrode pad 39a and the second electrode pad 39b to be connected to the first electrode pad 39a and the second electrode pad 39b, respectively. The first bump 45a and the second bump 45b may be formed by coating. The first bump 45a and the second bump 45b are terminals electrically connected to a circuit board such as an MC-PCB and have coplanar ends. In addition, the first electrode pad 39a may be formed at the same level as that of the second electrode pad 39b, so that the first bump 45a and the second bump 45b may also be formed on the same plane. Therefore, the first bump 45a and the second bump 45b may have the same height.

Meanwhile, the dummy bump 45c may be located between the first bump 45a and the second bump 45b. A dummy bump 45 c may be formed together with the first bump 45 a and the second bump 45 b to provide a thermal path for exhausting heat from the semiconductor stack 30 .

The insulating layer 43 may cover side surfaces of the first bump 45a and the second bump 45b. The insulating layer 43 may also cover side surfaces of the dummy bump 45c. In addition, the insulating layer 43 fills the space between the first bump 45 a , the second bump 45 b and the dummy bump 45 c to prevent moisture from entering the semiconductor stack 30 from the outside. The insulating layer 43 also covers side surfaces of the first and second electrode pads 39a and 39b to protect the first and second electrode pads 39a and 39b from external environmental factors such as moisture. Although the insulating layer 43 may be configured to cover the entire side surfaces of the first bump 45a and the second bump 45b, the present invention is not limited thereto. Alternatively, the insulating layer 43 may cover the side surfaces of the first and second bumps 45 a and 45 b except some regions of the side surfaces near the ends of the first and second bumps.

In the present exemplary embodiment, the insulating layer 43 is shown to cover the side surfaces of the first and second electrode pads 39a and 39b, but the present invention is not limited thereto. Alternatively, another insulating layer may be used to cover the first electrode pad 39a and the second electrode pad 39b, and the insulating layer 43 may be formed under the other insulating layer. In this case, the first bump 45a and the second bump 45b may be connected to the first electrode pad 39a and the second electrode pad 39b through the other insulating layer.

The wavelength converter 51 may be located above the first conductive type upper semiconductor layer 25 opposite to the remaining semiconductor stack 30 . The wavelength converter 51 may contact the upper surface of the first conductive type upper semiconductor layer 25 . The wavelength converter 51 may be a phosphor sheet having a uniform thickness without limitation. Alternatively, the wavelength converter 51 may be a substrate doped with impurities for wavelength conversion, for example, a sapphire substrate or a silicon substrate.

In the present exemplary embodiment, side surfaces of the semiconductor stack 30 are covered with a protective insulating layer. The protective insulating layer may include, for example, the first insulating layer 33 and/or the second insulating layer 37 . In addition, the first contact layer 35 may be covered by the second insulating layer 37 to be protected from the external environment, and the second contact layer 31 may be covered by the first insulating layer 33 and the second insulating layer 37 to be protected from the external environment. influences. The first electrode pad 39 a and the second electrode pad 39 b are also protected by, for example, an insulating layer 43 . Therefore, deterioration of the semiconductor stack 30 due to moisture can be prevented.

The wavelength converter 51 may be attached to the first conductive type upper semiconductor layer 25 at the wafer level, and then separated together with the protective insulating layer during the chip separation process. Therefore, the side surface of the wavelength converter 51 can be in line with the protective insulating layer. That is, it is possible to make the side surface of the wavelength converter 51 flush with the side surface of the protective insulating layer along a straight line. In addition, the side surface of the wavelength converter 51 may be in line with the side surface of the insulating layer 43 . Therefore, it is possible to make the side surface of the wavelength converter 51, the side surface of the protective insulating layer, and the side surface of the insulating layer 43 all flush along a straight line.

FIG. 2 is a schematic cross-sectional view of a light emitting diode package 200 according to a second exemplary embodiment of the present invention.

Referring to FIG. 2 , an LED package 200 is similar to the LED package 100 according to the above exemplary embodiment. However, in the present exemplary embodiment, the first bump 65 a and the second bump 65 b are formed in the substrate 61 .

Specifically, the base 61 includes through holes in which the first bump 65a and the second bump 65b are respectively formed. The substrate 61 is an insulating substrate such as, but not limited to, a sapphire substrate or a silicon substrate. The substrate 61 having the first bump 65a and the second bump 65b may be attached to the first electrode pad 39a and the second electrode pad 39b. In this case, in order to prevent the first electrode pad 39a and the second electrode pad 39b from being exposed to the outside, the insulating layer 49 may cover side surfaces and bottom surfaces of the first electrode pad 39a and the second electrode pad 39b . In addition, the insulating layer 49 may have an opening exposing the first electrode pad 39a and the second electrode pad 39b, and then other metal layers 67a, 67b are formed in the opening. The other metal layers 67a, 67b may consist of a bonding metal.

FIG. 3 is a cross-sectional view of a light emitting diode module including the LED package 100 according to the first exemplary embodiment.

Referring to FIG. 3 , the LED module includes a circuit board 71 (eg, MC-PCB), an LED package 100 and a lens 81 . The circuit board 71 (eg, MC-PCB) has connection pads 73a, 73b for mounting the LED package 100 thereon. The first bump 45a and the second bump 45b (see FIG. 1 ) of the LED package 100 are connected to the connection pads 73a, 73b, respectively.

A plurality of LED packages 100 may be mounted on the circuit board 71 , and a lens 81 may be disposed on the LED packages 100 to adjust a direction angle of light emitted from the LED packages 100 .

According to the second exemplary embodiment, the light emitting diode package 200 may be mounted on a circuit board instead of the LED package 100 .

4 to 12 illustrate a method of manufacturing the LED package 100 according to the first exemplary embodiment. In FIGS. 5 to 10 , (a) is a plan view, and (b) is a cross-sectional view taken along line A-A of (a).

Referring to FIG. 4 , a semiconductor stack 30 including a first conductive type semiconductor layer 25 , an active layer 27 and a second conductive type semiconductor layer 29 is formed on a growth substrate 21 . The growth substrate 21 may be a sapphire substrate, but is not limited thereto. Alternatively, the growth substrate 21 may be other types of heterogeneous substrates, such as silicon substrates. Each of the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 29 may consist of a single layer or multiple layers. In addition, the active layer 27 may have a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layer may be formed of a III-N based compound semiconductor on the growth substrate 21 by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

A buffer layer (not shown) may be formed before forming the compound semiconductor layer. A buffer layer is formed to alleviate lattice mismatch between the growth substrate 21 and the compound semiconductor layer, and the buffer layer may be formed of a GaN-based material layer such as gallium nitride or aluminum nitride.

Referring to (a) and (b) of FIG. 5, the semiconductor stack 30 is patterned to form a chip (stack) separation region 30b while patterning the second conductivity type semiconductor layer 29 and the active layer 27 to form a first A plurality of contact holes 30 a in the conductive type semiconductor layer 25 . The semiconductor stack 30 may be patterned through a photolithography process and an etching process.

The chip separation area 30b is an area for dividing the LED package structure into individual LED packages, and the side surfaces of the first conductivity type semiconductor layer 25, the side surfaces of the active layer 27 and the side surfaces of the second conductivity type semiconductor layer 29 are on the chip. The separation area 30b is exposed. Advantageously, the chip separation region 30b may be configured to expose the substrate 21 without being limited thereto.

The plurality of contact holes 30a may be circular, but not limited thereto. The contact hole 30a may have various shapes. The second conductive type semiconductor layer 29 and the active layer 27 are exposed to sidewalls of the plurality of contact holes 30a. As shown, the contact hole 30a may have sloped sidewalls.

Referring to (a) and (b) of FIG. 6 , a second contact layer 31 is formed on the second conductive type semiconductor layer 29 . The second contact layer 31 is formed on the semiconductor stack 30 except for regions corresponding to the plurality of contact holes 30a.

The second contact layer 31 may include a transparent conductive oxide film such as indium tin oxide (ITO) or a reflective metal layer such as silver (Ag) or aluminum (Al). The second contact layer 31 may consist of a single layer or multiple layers. The second contact layer 31 may also be configured to form an ohmic contact with the second conductivity type semiconductor layer 29 .

The second contact layer 31 may be formed before or after forming the plurality of contact holes 30a.

Referring to (a) and (b) of FIG. 7 , a first insulating layer 33 is formed to cover the second contact layer 31 . The first insulating layer 33 may cover side surfaces of the semiconductor stack 30 exposed to the chip separation region 30b while covering sidewalls of the plurality of contact holes 30a. Here, the first insulating layer 33 may have openings 33a exposing the first conductive type semiconductor layer 25 in the plurality of contact holes 30a.

The first insulating layer 33 may be composed of a single layer or multiple layers (for example, a silicon oxide film or a silicon nitride film). Alternatively, the first insulating layer 33 may consist of a distributed Bragg reflector formed by alternately stacking insulating layers having different refractive indices. For example, the first insulating layer 33 may be formed by alternately stacking SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ . In addition, the first insulating layer 33 may be formed to provide a distributed Bragg reflector having high reflectivity for a wide wavelength range of blue, green, and red light by adjusting the thickness of each insulating layer.

Referring to (a) and (b) of FIG. 8 , a first contact layer 35 is formed on the first insulating layer 33 . The first contact layer 35 includes a contact portion 35a contacting the first conductive type upper semiconductor layer 25 exposed in the contact hole 30a and a connection portion 35b connecting the contact portions 35a to each other. The first contact layer 35 may be composed of a reflective metal layer, but is not limited thereto.

The first contact layer 35 is formed on some regions of the semiconductor stack 30 such that the first insulating layer 33 is exposed on other regions of the semiconductor stack 30 where the first contact layer 35 is not formed.

Referring to (a) and (b) of FIG. 9 , a second insulating layer 37 is formed on the first contact layer 35 . The second insulating layer 37 may be composed of a single layer or multiple layers (silicon oxide film or silicon nitride film). In addition, the second insulating layer 37 may be composed of a distributed Bragg reflector formed by alternately stacking insulating layers having different refractive indices.

The second insulating layer 37 may cover the first contact layer 35 while covering the first insulating layer 33 . The second insulating layer 37 may also cover side surfaces of the semiconductor stack 30 in the chip separation region 30b.

The second insulating layer 37 has an opening 37 a exposing the first contact layer 35 . In addition, the second insulating layer 37 and the first insulating layer 33 are formed with an opening 37 b exposing the second contact layer 31 .

Referring to (a) and (b) of FIG. 10 , a first electrode pad 39 a and a second electrode pad 39 b are formed on the second insulating layer 37 . The first electrode pad 39a is connected to the first contact layer 35 through the opening 37a, and the second electrode pad 39b is connected to the second contact layer 31 through the opening 37b.

The first electrode pad 39a is separated from the second electrode pad 39b, and each of the first electrode pad 39a and the second electrode pad 39b may have a relatively large area from a top perspective view, for example, not less than an LED 1/3 the area of the package.

Referring to FIG. 11, an insulating layer 43 is formed on the first electrode pad 39a and the second electrode pad 39b. The insulating layer 43 covers the first electrode pad 39a and the second electrode pad 39b, and has grooves exposing the upper surfaces of the electrode pads 39a and 39b. In addition, the insulating layer 43 may have a groove exposing the second insulating layer 37 between the first electrode pad 39a and the second electrode pad 39b.

Then, a first bump 45 a and a second bump 45 b are formed in the groove of the insulating layer 43 , and a dummy bump 45 c may be formed between the first bump and the second bump.

The bump may be formed by plating (eg, electroplating) using a metal material. A seed layer for plating may also be formed, if necessary.

After the first bump 45a and the second bump 45b are formed, the insulating layer 43 may be removed. For example, the insulating layer 43 may be formed of polymer such as photoresist, and may be removed after the bump is formed. Alternatively, the insulating layer 43 may be left to protect the side surfaces of the first bump 45a and the second bump 45b.

In the present exemplary embodiment, the insulating layer 43 is shown as being formed directly on the first pad electrode 39a and the second pad electrode 39b. In another exemplary embodiment, another insulating layer may be formed to cover the first electrode pad 39a and the second electrode pad 39b. Another insulating layer may be configured to have an opening exposing the first electrode pad 39a and the second electrode pad 39b. Then, a process of forming the insulating layer 43 and the bump may be performed.

Referring to FIG. 12 , the growth substrate 21 is removed, and the wavelength converter 51 is attached to the first conductive type semiconductor layer 25 . Growth substrate 21 may be removed by optical techniques such as laser lift-off (LLO), mechanical polishing, or chemical etching.

Then, anisotropic etching (eg, photoelectrochemical (PEC) etching) is performed on the exposed surface of the first conductive type semiconductor layer 25 to form a rough surface on the exposed first conductive type semiconductor layer 25 .

Meanwhile, a wavelength converter such as a phosphor sheet including phosphor may be attached to the first conductive type semiconductor layer 25 .

Alternatively, growth substrate 21 may contain impurities for converting the wavelength of light generated in active layer 27 . In this case, the growth substrate 21 can be used as the wavelength converter 51 .

Then, the LED package structure is divided into individual packages along the chip separation area 30 b, thereby providing the completed LED package 100 . At this time, the second insulating layer 37 is cut together with the wavelength converter 51 so that the cutting planes of the second insulating layer 37 and the wavelength converter 51 can be formed on a line.

FIG. 13 is a cross-sectional view illustrating a method of manufacturing the LED package 200 according to the second exemplary embodiment of the present invention.

Referring to FIG. 13 , in the method of manufacturing the LED package 200 according to this exemplary embodiment, the process is the same as that of the above-described method of manufacturing the LED package 100 until the first electrode pad 39a and the second electrode pad 39b are formed. ((a) and (b) of FIG. 10).

After the first electrode pad 39a and the second electrode pad 39b are formed, an insulating layer 49 is formed to cover the first electrode pad 39a and the second electrode pad 39b. The insulating layer 49 may cover side surfaces of the first and second electrode pads 39a and 39b to protect the first and second electrode pads 39a and 39b. The insulating layer 49 has openings exposing the first electrode pad 39a and the second electrode pad 39b. Further metal layers 67a, 67b are then formed in the openings. The other metal layers 67a, 67b may consist of a bonding metal.

The substrate 61 is bonded to the first electrode pad 39a and the second electrode pad 39b. The substrate 61 may have a through hole in which the first bump 65 a and the second bump 65 b may be formed. In addition, the first bump and the second bump may be formed to have pads 69a, 69b at their ends. The substrate 61 having the first bump 65a, the second bump 65b, the pad 69a, and the pad 69b may be separately prepared and bonded to the wafer having the first electrode pad 39a and the second electrode pad 39b.

Then, as described with reference to FIG. 12 , the growth substrate 21 is removed and the wavelength converter 51 may be attached to the first conductive type semiconductor layer 25 , followed by dividing the LED package structure into individual LED packages. Thus, a completed LED package 200 as described in FIG. 2 is provided.

FIG. 14 is a cross-sectional view of an LED package 300 according to a third exemplary embodiment of the present invention.

14, the LED package 300 may include a semiconductor stack 130 divided into a plurality of light emitting units (only two light emitting units S1, S2 are shown here), a first contact layer 135, a second contact layer 131, a first The insulating layer 133, the second insulating layer 137, the first electrode pad 139a, the second electrode pad 139b, the connector 139c connecting adjacent light emitting cells to each other in series, the first bump 145a and the second bump 145b. In addition, the LED package 300 may include a third insulating layer 141, an insulating layer 143, a dummy bump 145c, a wavelength converter 151 and other metal layers 140a, 140b.

The semiconductor stack 130 includes a first conductive type upper semiconductor layer 125 , an active layer 127 and a second conductive type lower semiconductor layer 129 . The semiconductor stack 130 of the present exemplary embodiment is similar to the semiconductor stack 30 described in FIG. 1 , and a detailed description thereof will be omitted here.

Each of the light emitting cells S1, S2 has a plurality of contact holes 130a extending through the second conductive type lower semiconductor layer 129 and the active layer 127 to expose the first conductive type upper semiconductor layer (see (b) of FIG. 18 ). , the first contact layer 135 contacts the first conductive type upper semiconductor layer 125 exposed in the plurality of contact holes. The light emitting cells S1, S2 are separated from each other by a cell separation region 130b (see (b) of FIG. 18).

The second contact layer 131 contacts the second conductive type lower semiconductor layer 129 of each light emitting unit S1, S2. The second contact layer 131 includes a reflective metal layer to reflect light generated in the active layer 127 . In addition, the second contact layer 131 may form an ohmic contact with the second conductive type lower semiconductor layer 129 .

The first insulating layer 133 covers the second contact layer 131 . In addition, the first insulating layer 133 covers sidewalls of the semiconductor stack 130 exposed in the plurality of contact holes 130a. In addition, the first insulating layer 133 may cover a side surface of each light emitting unit S1, S2. The first insulating layer 133 insulates the first contact layer 135 from the second contact layer 131, and simultaneously insulates the second conductive type lower semiconductor layer 129 and the active layer 127 exposed in the plurality of contact holes 130a from the first contact layer 135. . The first insulating layer 133 may be composed of a single layer or multiple layers (for example, a silicon oxide film or a silicon nitride film). In addition, the first insulating layer 133 may be composed of a distributed Bragg reflector formed by alternately stacking insulating layers having different refractive indices (for example, SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ ).

The first contact layer 135 is located under the first insulating layer 133 and contacts the first conductive type upper semiconductor layer 125 through the first insulating layer 133 in the plurality of contact holes 130 a in each light emitting unit S1 , S2 . The first contact layer 135 includes a contact portion 135a contacting the first conductive type upper semiconductor layer 125 and a connection portion 135b connecting the contact portions 135a to each other. Accordingly, the contact portions 135a are electrically connected to each other by the connection portion 135b. The first contact layers 135 under the respective light emitting cells S1 , S2 are separated from each other and formed under some regions of the first insulating layer 133 . The first contact layer 135 may be composed of a reflective metal layer.

The second insulating layer 137 covers the first contact layer 135 under the first contact layer 135 . In addition, the second insulating layer 137 may cover the first insulating layer 133 while covering the side surface of each light emitting unit S1, S2. The second insulating layer 137 may consist of a single layer or multiple layers. Alternatively, the second insulating layer 137 may consist of a distributed Bragg reflector.

The first electrode pad 139 a and the second electrode pad 139 b are located under the second insulating layer 137 . The first electrode pad 139a may be connected to the first contact layer 135 of the first light emitting unit S1 through the second insulating layer 137 . In addition, the second electrode pad 139b may be connected to the second contact layer 131 of the second light emitting unit S2 through the second insulating layer 137 and the first insulating layer 133 .

The connecting member 139c is located under the second insulating layer 137 and passes through the second insulating layer 137 to electrically connect two adjacent light emitting units S1 and S2 to each other. The connector 139c may connect the second contact layer 131 of one light emitting unit S1 to the first contact layer 135 of another light emitting unit S2 adjacent thereto, so that the two light emitting units S1, S2 are connected to each other in series.

In this exemplary embodiment, two light emitting units S1, S2 are shown. However, it should be understood that two or more light emitting units may be connected to each other in series through the plurality of connection members 139c. Here, the first electrode pads 139a, 139b may be connected in series to opposite ends located in such a series array.

Meanwhile, the third insulating layer 141 may cover the first electrode pad 139a, the second electrode pad 139b and the connector 139c under the first electrode pad 139a, the second electrode pad 139b and the connector 139c. The third insulating layer 141 may have openings exposing the first electrode pad 139a and the second electrode pad 139b. The third insulating layer 141 may be formed of a silicon oxide film or a silicon nitride film.

The first bump 145a and the second bump 145b are located under the first electrode pad 139a and the second electrode pad 139b, respectively. The first bump 145a and the second bump 145b may be formed through plating. The first bump 145a and the second bump 145b are terminals electrically connected to a circuit board (eg, MC-PCB), and have ends coplanar with each other. In addition, the first electrode pad 139a may be formed on the same level as that of the second electrode pad 139b, so that the first bump 145a and the second bump 145b may also be formed on the same plane. Accordingly, the first bump 145a and the second bump 145b may have the same height.

Other metal layers 140a, 140b may be disposed between the first bump 145a and the first electrode pad 139a and between the second bump 145b and the second electrode pad 139b. Here, other metal layers 140a, 140b are provided to form the first and second electrode pads 139a, 139b higher than the connectors 139c, and may be located inside the opening of the third insulating layer 141 . The first electrode pad 139a, the second electrode pad 139b and other metal layers 140a, 140b may constitute a final electrode pad.

Meanwhile, the dummy bump 145c may be located between the first bump 145a and the second bump 145b. A dummy bump 145c may be formed together with the first bump 145a and the second bump 145b to provide a heat path for exhausting from the light emitting units S1, S2. The dummy bump 145c is separated from the connector 139c by the third insulating layer 141 .

The insulating layer 143 may cover side surfaces of the first bump 145a and the second bump 145b. The insulating layer 143 may also cover side surfaces of the dummy bump 145c. In addition, the insulating layer 143 fills the space between the first bump 145 a , the second bump 145 b and the third bump 145 c to prevent moisture from entering the semiconductor package 130 from the outside. Although the insulating layer 143 may be configured to cover the entire side surfaces of the first bump 145a and the second bump 145b, the present invention is not limited thereto. Alternatively, the insulating layer 143 may cover side surfaces of the first and second bumps 145a and 145b except some regions of the side surfaces near ends of the first and second bumps.

The wavelength converter 151 may be located on the light emitting units S1, S2. The wavelength converter 151 may contact the upper surface of the first conductive type upper semiconductor layer 125 . The wavelength converter 151 also covers the cell separation region 130b and the chip separation region. The wavelength converter 151 may be a phosphor sheet having a uniform thickness, without being limited thereto. Alternatively, the wavelength converter 151 may be a substrate doped with impurities for wavelength conversion, for example, a sapphire substrate or a silicon substrate.

In this embodiment, side surfaces of the light emitting units S1, S2 may be covered by a protective insulating layer. The protective insulating layer may include, for example, the first insulating layer 133 and/or the second insulating layer 137 . In addition, the first contact layer 135 may be covered by the second insulating layer 137 to be protected from the external environment, and the second contact layer 131 may be covered by the first insulating layer 133 and the second insulating layer 137 to be protected from the external environment. influences. In addition, the first electrode pad 139 a and the second electrode pad 139 b are also protected by, for example, the third insulating layer 141 . Therefore, it is possible to prevent deterioration of the light emitting units S1, S2 due to moisture.

The wavelength converter 151 may be attached to the first conductive type upper semiconductor layer 125 at the wafer level, and then separated together with the protective insulating layer during the chip separation process (or package separation process). Therefore, the side surface of the wavelength converter 151 may be in line with the protective insulating layer. In addition, the side surface of the wavelength converter 151 may be in line with the side surface of the insulating layer 143 .

FIG. 15 is a schematic cross-sectional view of a light emitting diode package 400 according to a fourth exemplary embodiment of the present invention.

Referring to FIG. 15 , an LED package 400 is similar to the LED package 300 according to the above exemplary embodiment. But in this exemplary embodiment, the first bump 165 a and the second bump 165 b are formed in the base 161 .

Specifically, the base 161 includes through holes respectively having first and second bumps 165a and 165b formed therein. The substrate 161 is an insulating substrate such as, but not limited to, a sapphire substrate or a silicon substrate.

The substrate 161 having the first bump 165a and the second bump 165b may be attached to the third insulating layer 141, and the first bump 165a and the second bump 165b may be respectively connected to the first electrode pad 139a and the second electrode pad 139a. Disc 139b. Here, the first bump 165a and the second bump 165b may be bonded to other metal layers 140a, 140b, respectively.

16 is a cross-sectional view of a light emitting diode module including an LED package 300 according to the third exemplary embodiment on a circuit board.

Referring to FIG. 16 , the LED module includes, for example, a circuit board 171 of MC-PCB, an LED package 300 and a lens 181 . The circuit board 171 (eg, MC-PCB) has connection pads 173a, 173b for mounting the LED package 300 thereon. The first bump 145a and the second bump 145b (see FIG. 14 ) of the LED package 300 are connected to the connection pads 173a, 173b, respectively.

A plurality of LED packages 300 may be mounted on the circuit board 171 , and a lens 181 may be disposed on the LED packages 300 to adjust a direction angle of light emitted from the LED packages 300 .

In other exemplary embodiments, the light emitting diode package 400 may be mounted on the circuit board instead of the LED package 300 .

17 to 25 illustrate a method of manufacturing the LED package 300 according to the third exemplary embodiment. In FIGS. 18 to 23 , (a) is a plan view, and (b) is a sectional view taken along line A-A of (a).

Referring to FIG. 17 , a semiconductor stack 130 including a first conductive type semiconductor layer 125 , an active layer 127 and a second conductive type semiconductor layer 129 is formed on a growth substrate 121 . The growth substrate 121 and the semiconductor stack 130 are similar to the substrate 21 and the semiconductor stack 30 described with reference to FIG. 4 , and thus a detailed description thereof will be omitted here.

Referring to (a) and (b) of FIG. 18 , the semiconductor stack 130 is patterned to form a chip (package) separation region 130c and a cell separation region 130b, while patterning the second conductivity type semiconductor layer 129 and the active layer 127 to form light emitting units S1, S2, each light emitting unit S1, S2 has a plurality of contact holes 130a exposing the first conductive type semiconductor layer 125. The semiconductor stack 130 may be patterned through a photolithography process and an etching process.

The chip separation area 130c is an area for dividing the LED package structure into individual LED packages, the side surfaces of the first conductive type semiconductor layer 125, the side surfaces of the active layer 127, and the side surfaces of the second conductive layer type semiconductor layer 129 exposed at the chip separation region 130c. Advantageously, the chip separation region 130c and the cell separation region 130b may be configured to expose the substrate 121, without being limited thereto.

The plurality of contact holes 130a may have a circular shape, but is not limited thereto. The contact hole 130 may have various shapes. The second conductive type semiconductor layer 129 and the active layer 127 are exposed to sidewalls of the plurality of contact holes 130a. The contact hole 130a may have inclined sidewalls.

Referring to (a) and (b) of FIG. 19 , a second contact layer 131 is formed on the second conductive type semiconductor layer 129 . The second contact layer 131 is formed on the semiconductor stack 130 of each light emitting unit S1, S2 except for the region corresponding to the plurality of contact holes 130a.

The second contact layer 131 may include a transparent conductive oxide film such as indium tin oxide (ITO) or a reflective metal layer such as silver (Ag) or aluminum (Al). The second contact layer 131 may consist of a single layer or multiple layers. The second contact layer 131 may also be configured to form an ohmic contact with the second conductive type semiconductor layer 129 .

The second contact layer 131 may be formed before or after forming the plurality of contact holes 130a.

Referring to (a) and (b) of FIG. 20 , a first insulating layer 133 is formed to cover the second contact layer 131 . The first insulating layer 133 may cover a side surface of each light emitting unit S1, S2 while covering sidewalls of the plurality of contact holes 130a. Here, the first insulating layer 133 may have openings 133a exposing the first conductive type semiconductor layer 125 in the plurality of contact holes 130a.

The first insulating layer 133 may be composed of a single layer or multiple layers such as a silicon oxide film or a silicon nitride film. In addition, the first insulating layer 133 may be composed of a distributed Bragg reflector formed by alternately stacking insulating layers having different refractive indices. For example, the first insulating layer 133 may be formed by alternately stacking SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ . In addition, the first insulating layer 133 may be formed to provide a distributed Bragg reflector having high reflectivity for a wide wavelength range of blue, green, and red light by adjusting the thickness of each insulating layer.

Referring to (a) and (b) of FIG. 21 , a first contact layer 135 is formed on the first insulating layer 133 . A first contact layer 135 is formed on each light emitting unit S1, S2, and the first contact layer 135 includes a contact portion 135a exposed in the contact hole 130a and contacting the first conductive type upper semiconductor layer 125 and a contact portion 135a connected to each other. connecting portion 135b. The first contact layer 135 may be composed of a reflective metal layer, but is not limited thereto.

The first contact layer 135 is formed on some regions of each firing cell S1 , S2 such that the first insulating layer 133 is exposed at other regions of the semiconductor stack 130 where the first contact layer 135 is not formed.

Referring to (a) and (b) of FIG. 22 , a second insulating layer 137 is formed on the first contact layer 135 . The second insulating layer 137 may be composed of a single layer or multiple layers such as a silicon oxide film or a silicon nitride film. Alternatively, the second insulating layer 137 may be composed of a distributed Bragg reflector formed by alternately stacking insulating layers having different refractive indices.

The second insulating layer 137 may cover the first contact layer 135 while covering the first insulating layer 133 . The second insulating layer 137 may also cover a side surface of each light emitting unit S1, S2. In addition, the second insulating layer 137 may be filled in the chip separation region 130c and the cell separation region 130b.

The second insulating layer 137 has an opening 137a exposing the first contact layer 135 of each light emitting unit S1, S2. In addition, the second insulating layer 137 and the first insulating layer 133 are formed with an opening 137 b exposing the second contact layer 131 .

Referring to (a) and (b) of FIG. 23 , a connector 139 c , a first electrode pad 139 a and a second electrode pad 139 b are formed on the second insulating layer 137 . The first electrode pad 139a is connected to the first contact layer 135 of the first light emitting unit S1 through the opening 137a, and the second electrode pad 139b is connected to the second contact layer 131 of the second light emitting unit S2 through the opening 137b. In addition, the connector 139c connects the first contact layer 135 and the second contact layer 131 adjacent to the light emitting units S1, S2 to each other in series through the openings 137a, 137b.

Referring to FIG. 24, a third insulating layer 141 is formed on the first electrode pad 139a, the second electrode pad 139b, and the connector 139c. The third insulating layer 141 covers the first electrode pad 139a, the second electrode pad 139b and the connector 139c, and has grooves exposing the upper surfaces of the electrode pads 139a, 139b. Meanwhile, the third insulating layer 141 may have other metal layers 140a, 140b formed in grooves thereof. The other metal layers 140a, 140b increase the height of the electrode pads 139a, 139b so that the final electrode pads may have a higher height than the connector 139c. Other metal layers 140a, 140b may be formed before forming the third insulating layer 141 . The upper surfaces of the other metal layers 140a, 140b may be substantially coplanar with the upper surface of the third insulating layer 141 .

Referring to FIG. 25 , a patterned insulating layer 143 is formed on the third insulating layer 141 . The patterned insulating layer 143 has grooves exposing upper sides of the first electrode pad 139a and the second electrode pad 139b, for example, other metal layers 140a, 140b. In addition, the patterned insulating layer 143 may have grooves exposing the insulating layer 141 between the first electrode pad 139a and the second electrode pad 139b.

Then, a first bump 145 a and a second bump 145 b are formed in the groove of the insulating layer 143 , and a dummy bump 145 c may be formed between the first bump and the second bump.

The bumps may be formed by plating such as electroplating. If necessary, a seed layer for plating can also be formed.

After the first bump 145a and the second bump 145b are formed, the insulating layer 143 may be removed. For example, the insulating layer 143 may be formed of polymer such as photoresist, and may be removed after the bump is formed. Alternatively, the insulating layer 143 may remain to protect side surfaces of the first bump 145a and the second bump 145b.

Referring to FIG. 26, the growth substrate 121 is removed, and then the wavelength converter 151 is attached to the light emitting units S1, S2. The growth substrate 121 may be removed by optical techniques such as laser lift-off (LLO), mechanical polishing, or chemical etching.

Then, the exposed surface of the first conductive type semiconductor layer 125 is subjected to anisotropic etching such as PEC etching to form a rough surface on the exposed first conductive type semiconductor layer 125 .

Meanwhile, a wavelength converter 151 such as a phosphor sheet including phosphor may be attached to the first conductive type semiconductor layer 125 .

Alternatively, the growth substrate 121 may contain impurities for converting the wavelength of light generated in the active layer 127 . In this case, the growth substrate 121 may be used as the wavelength converter 151 .

Then, the LED package structure is divided into individual packages along the chip separation region 130 c, thereby providing the completed LED package 300 . At this time, the second insulating layer 137 is cut together with the wavelength converter 151 so that cutting planes of the second insulating layer 137 and the wavelength converter 151 may be formed on a straight line.

FIG. 27 is a cross-sectional view explaining a method of manufacturing an LED package 400 according to a fourth exemplary embodiment of the present invention.

Referring to FIG. 27 , in the method of manufacturing the LED package 400 according to this embodiment, the process is the same as that of the method of manufacturing the LED package 300 described above ( FIG. 24 ), until the formation of the third insulating layer 141 and other metal layers 140a, 140b.

In the present exemplary embodiment, the substrate 161 is bonded to the third insulating layer 141 . The substrate 161 may have a through hole in which the first bump 165 a and the second bump 165 b may be formed. In addition, the first bump 165a and the second bump 165b may be formed with pads (not shown) at ends thereof. In addition, the base 161 may have a groove partially formed on a lower surface thereof and filled with the metal material 165c. The metal material 165c improves the heat dissipation of the substrate.

Alternatively, the substrate 161 having the first bump 165a and the second bump 165b may be separately prepared, and the substrate 161 having the first bump 165a and the second bump 165b may be bonded to the substrate having the first electrode pad 139a and wafer of the second electrode pad 139b. The first bump 165a and the second bump 165b may be electrically connected to the first electrode pad 139a and the second electrode pad 139b, respectively.

Then, as described with reference to FIG. 26, the growth substrate 121 is removed, and the wavelength converter 151 may be attached to the light emitting units S1, S2, and then the LED package structure is divided into individual LED packages. Thus, the completed LED package 400 depicted in FIG. 15 is provided.

Also, exemplary embodiments of the present invention provide a wafer-level LED package that can be directly formed on a circuit board for a module without using a conventional lead frame or printed circuit board. Accordingly, the LED package can have high efficiency and can exhibit improved heat dissipation while reducing the time and cost for manufacturing the LED package. Furthermore, LED modules having LED packages mounted thereon can have high efficiency and can exhibit improved heat dissipation.

In addition, the LED package may include a plurality of light emitting units connected in series to each other and an array connected in antiparallel to each other. In addition, a plurality of light emitting units may be connected into a bridge rectifier and may be used to form a bridge rectifier. Therefore, the LED module including the LED package can be operated without a separate AC/DC converter.

Although the invention has been described with reference to some exemplary embodiments in conjunction with the accompanying drawings, it will be apparent to those skilled in the art that various modifications and changes can be made in the invention without departing from the spirit and scope of the invention. In addition, it should be understood that some features of a certain embodiment can also be applied to other embodiments without departing from the spirit and scope of the invention. Therefore, it should be understood that the embodiments are provided by way of illustration only, and that the embodiments are given so that a complete disclosure of the invention and a thorough understanding of the invention will be provided to those skilled in the art Technical staff. Thus, it is intended that the present invention covers the modifications and variations provided they come within the scope of the claims and their equivalents.

Claims (10)

1. a light-emitting diode, described light-emitting diode comprises:

Semiconductor stack overlapping piece, the active layer comprising the first semiconductor layer, the second semiconductor layer and be arranged between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer and the second semiconductor layer have different conduction types;

First contact layer, is arranged on the first semiconductor layer;

Second contact layer, is arranged on the second semiconductor layer;

First insulating barrier, is coated with sidewall and second contact layer of active layer and the second semiconductor layer, and contacts the first contact layer, and the first insulating barrier comprises the first opening of exposure first semiconductor layer and exposes the second opening of the second contact layer;

Second insulating barrier, is arranged on the first insulating barrier;

First projection, be arranged on the first side of semiconductor stack overlapping piece, the first projection is electrically connected to the first contact layer;

Second projection, be arranged on the first side of semiconductor stack overlapping piece, the second projection is electrically connected to the second contact layer; And

3rd insulating barrier, is arranged on the side surface of the first projection and the second projection.

2. light-emitting diode as claimed in claim 1, wherein, the second insulating barrier is set directly on the first contact layer.

3. light-emitting diode as claimed in claim 1, described light-emitting diode also comprises the wavelength conversion layer be set directly on semiconductor stack overlapping piece.

4. light-emitting diode as claimed in claim 3, wherein, wavelength conversion layer is arranged on second side relative with the first side of semiconductor stack overlapping piece.

5. light-emitting diode as claimed in claim 4, wherein, wavelength conversion layer comprises phosphor sheet or the material doped with impurity.

6. light-emitting diode as claimed in claim 4, wherein, wavelength conversion layer comprises the side surface coplanar with the side surface of the first insulating barrier and the second insulating barrier.

7. light-emitting diode as claimed in claim 6, wherein, the described side surface of the first insulating barrier and the second insulating barrier and the side surface of the 3rd insulating barrier coplanar.

8. light-emitting diode as claimed in claim 1, wherein, at least one in the first insulating barrier and the second insulating barrier comprises distributed Bragg reflector.

9. light-emitting diode as claimed in claim 1, wherein, the first insulating barrier makes the first contact layer separate with the second contact layer.

10. light-emitting diode as claimed in claim 1, wherein, the 3rd insulating barrier comprises polymer.