CN104465735B - Embedded gate insulation tunnelling enhancing transistor - Google Patents

Abstract

The invention relates to a high-transfer characteristic and low parasitic capacitance built-in gate insulation tunneling enhanced transistor. Compared with MOSFETs or TFETs of the same size, the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field intensity in the tunneling insulating layer is used to realize a more sensitive relationship. Good transfer characteristics; avoiding the obvious increase of parasitic capacitance between gate-source, source-gate, gate-drain and drain-gate due to the shrinking distance between gate electrode and drain electrode or between gate electrode and source electrode, making The device significantly reduces parasitic capacitance while ensuring high transfer characteristics; and since there is no gate-to-drain overlap region that MOSFETs or TFETs have, it does not cause significant reverse leakage current. The invention also proposes a specific manufacturing method of an embedded gate insulation tunneling enhancement transistor with high transfer characteristics and low parasitic capacitance. The transistor significantly improves the working characteristics of the nanoscale integrated circuit unit and is suitable for popularization and application.

Description

Embedded Gate Insulated Tunneling Enhancement Transistor

Technical field:

The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to an embedded gate insulation tunneling enhanced transistor with high transfer characteristics and low parasitic capacitance, which is suitable for the manufacture of high-performance ultra-high integrated integrated circuits.

Background technique:

Currently, the ever-shortening device channel lengths of integrated circuit unit metal-oxide-semiconductor field-effect transistors (MOSFETs) have resulted in degraded device transfer characteristics. The subthreshold swing increases with decreasing channel length, and the static power consumption increases significantly. Although the degradation of the device performance can be alleviated by improving the structure of the gate electrode, when the device size is further reduced, the transfer characteristics of the device will deteriorate again.

On the other hand, with the continuous reduction of device size, the distance between the drain electrode and the gate electrode, or the distance between the source electrode and the gate electrode is also continuously reduced, which makes the gate-source, source-gate of the device , Gate-to-drain and drain-gate parasitic capacitance increases significantly, which increases the power consumption of the integrated circuit, increases the signal propagation delay and negative feedback, and affects the gain-bandwidth product.

Tunneling Field Effect Transistors (TFETs), compared with the transfer characteristics of MOSFETs, although its average subthreshold swing has been improved, but its forward conduction current is too small, and the parasitic capacitance generated due to size reduction, compared with MOSFETs and No improvement.

The tunneling part of TFETs can be generated by introducing materials with narrower band gaps such as compound semiconductors, silicon germanium or germanium, which can increase the tunneling probability and improve the transfer characteristics, but increases the production cost and process difficulty. In addition, the use of high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot substantially increase the tunneling probability of the silicon material, so There is limited improvement in the transfer characteristics of TFETs.

In addition, since both TFETs and MOSFETs control the electric field, potential and carrier distribution inside the gate insulating layer and semiconductor through the electric field effect of the gate electrode, in order to improve the control ability of the gate electrode to the inside of the semiconductor, high dielectric The constant and thinning gate insulating layer strengthens the control ability of the gate electrode, but at the same time shortens the distance between the gate electrode and the drain region, the gate electrode and the source region, so that the overlapping area of the gate electrode and the drain electrode is at the gate electrode Larger gate-induced-drain leakage (GIDL) or gate-induced-source leakage (GISL) currents are generated when the polarity is reverse-biased.

Invention content:

purpose of invention

In order to significantly improve the transfer characteristics of nanoscale integrated circuit basic unit devices on the premise of being compatible with existing silicon-based process technologies, ensure that the devices have good forward current conduction characteristics while reducing sub-threshold swings, and completely solve the problem of device size The problem of significantly increasing parasitic capacitance caused by continuous shrinkage, and significantly reducing the reverse leakage current of the device, the present invention provides a high-transfer characteristic and low parasitic capacitance embedded gate insulation suitable for high-performance, high-integration integrated circuit manufacturing Tunneling enhancement transistor.

Technical solutions

The present invention is achieved through the following technical solutions:

For the embedded gate insulation tunneling enhanced transistor, a bulk silicon wafer containing only a single crystal silicon substrate 1 is used as a device substrate, or an SOI wafer containing both a single crystal silicon substrate 1 and a wafer insulating layer 2 is used as a The substrate for generating the device; the emitter region 3, the base region 4 and the collector region 5 are located above the monocrystalline silicon substrate 1 of the bulk silicon wafer or the wafer insulating layer 2 of the SOI wafer; the emitter 9 is located in the emitter region 3 above; the collector 10 is located above the collector region 5; the conductive layer 6 is embedded in the base region 4 and surrounded by three sides of the base region 4; the tunnel insulating layer 7 is embedded in the conductive layer 6 and is surrounded by the conductive layer 6) Surrounded on three sides; the gate electrode 8 is embedded in the tunneling insulating layer 7, and is surrounded by the tunneling insulating layer 7 on three sides; the blocking insulating layer 11 is located between the device units and between the electrodes, for each device unit and Between the electrodes play a role in isolation.

The emitter 9 and the collector 10 are isolated by a blocking insulating layer 11 ; the emitter region 3 and the collector region 5 are isolated by a blocking insulating layer 11 .

In order to achieve the device functions described in the present invention, the present invention proposes a high transfer characteristic and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, and its core structural features are:

The gate electrode 8 , the tunneling insulating layer 7 and the conductive layer 6 are all embedded in the base region 4 , and only the upper surface is in contact with the blocking insulating layer 11 .

A tunnel insulating layer 7, a conductive layer 6 and a base region 4 are sequentially interposed between the gate electrode 8 and the emitter region 3;

A tunnel insulating layer 7, a conductive layer 6 and a base region 4 are sequentially sandwiched between the gate electrode 8 and the collector region 4;

The gate electrode 8 is an electrode for controlling the tunneling effect generated by the tunneling insulating layer 7, and is an electrode for controlling the turning on and off of the device.

The tunneling insulating layer 7 is an insulating layer for generating gate insulating layer tunneling current.

The conductive layer 6 forms an ohmic contact with the base region 4 and is a metal material, or a semiconductor material having the same impurity type as the base region 4 and a doping concentration greater than 10 ¹⁸ per cubic centimeter.

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 3 and the collector electrode 10. ohmic contact.

Embedded gate insulation tunneling enhancement transistor, taking N type as an example, emitter region 3, base region 4 and collector region 5 are N region, P region and N region respectively, and its specific working principle is: when the collector electrode 10 is positive When the gate electrode 8 is at a low potential, there is not enough potential difference formed between the gate electrode 8 and the conductive layer 6. At this time, the tunneling insulating layer 7 is in a high-resistance state, and no obvious tunneling current passes through, so that the base region 4 A large enough base current cannot be formed between the emitter region 3 and the embedded gate insulation tunneling enhancement transistor with high transfer characteristics and low parasitic capacitance, that is, the device is in an off state; as the voltage of the gate electrode 8 gradually increases, the gate The potential difference between the electrode 8 and the conductive layer 6 gradually increases, so that the electric field intensity in the tunneling insulating layer 7 between the gate electrode 8 and the conductive layer 6 also gradually increases. When the electric field in the tunneling insulating layer 7 When the strength is below the critical value, the tunneling insulating layer 7 still maintains a good high-resistance state, and the potential difference between the gate electrode and the emitter is almost completely dropped between the inner wall and the outer wall of the tunneling insulating layer 7, which makes The potential difference between the base region and the emitter region is extremely small, so there is almost no current flowing in the base region, and the device remains in a good off state. When the electric field strength in the tunneling insulating layer 7 is above the critical value, the tunneling The insulating layer 7 will generate obvious tunneling current due to the tunneling effect, and the tunneling current will rise steeply at a very fast speed with the increase of the potential of the gate electrode 8, which makes the tunneling insulating layer 7 The high-resistance state is rapidly converted to a low-resistance state within a very short potential change interval. When the tunneling insulating layer 7 is in a low-resistance state, the resistance formed by the tunneling insulating layer 7 between the gate electrode 8 and the conductive layer 6 is It should be much smaller than the resistance formed between the conductive layer 6 and the emitter 3, which makes a sufficiently large forward bias voltage formed between the base region 4 and the emitter region 3, and under the action of the tunneling effect, the tunneling A large amount of electron movement is generated between the inner wall and the outer wall of the insulating layer 7, which provides a current source for the base region 4, and the current of the base region 4 flows out from the collector after being enhanced by the emitter region 3, and the device is in an open state at this time;

Advantages and effects

The present invention has following advantage and beneficial effect:

1. High transfer characteristics

High transfer characteristics and low parasitic capacitance Embedded gate insulation tunneling enhancement transistor, using the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, through the tunneling insulating layer embedded in the base region 4 7 Select an appropriate tunnel insulating material, and properly adjust the depth of embedding and the thickness of the tunnel insulating layer 7, so that the tunnel insulating layer 7 can achieve high resistance and low resistance within the extremely small potential change range of the gate electrode. The transition between states, and the tunneling current generated on the tunneling insulating layer 7 is used as the driving current to induce a large amount of electron current flowing out of the emitter collection, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands as the conduction of the device. Compared with the passing current, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary structure MOSFETs, TFETs or ordinary bipolar transistors, high transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistors, Higher transfer characteristics can be achieved.

2. Low parasitic capacitance characteristics

High transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, compared with MOSFETs or TFETs, the role of the emitter 9 and the source electrode is equivalent, and the role of the collector 10 and the drain electrode is equivalent, because the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 are all embedded in the base region 4, and only the upper surface is in contact with the blocking insulating layer 11 and away from the emitter 9 and the collector 10, which avoids the gate electrode and the collector electrode 10 like MOSFETs or TFETs. The significant increase in the parasitic capacitance between the gate-source, source-gate, gate-drain, and drain-gate due to the shrinking distance between the drain electrodes or between the gate electrode and the source electrode makes the device reduce the Parasitic capacitance generated by MOSFETs or TFETs of the same size.

3. Low reverse leakage current

High transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, because the distance between the gate electrode 8 and the emitter region 3 or the collector region 5 depends on the sum of the horizontal lengths of the tunneling insulating layer 7 and the conductive layer 6, and Compared with MOSFETs or TFETs, there is no gate-to-drain overlap region between the gate electrode 8 and the emitter region 3, or between the gate electrode 8 and the collector electrode, which MOSFETs or TFETs have, so no significant reaction is caused. to the leakage current.

Description of drawings

1 is a schematic diagram of a two-dimensional structure of an embedded gate insulation tunneling enhancement transistor formed on a bulk silicon substrate in the present invention;

Figure 2 is a schematic diagram of Step 1,

Figure 3 is a schematic diagram of step two,

Figure 4 is a schematic diagram of step three,

Figure 5 is a schematic diagram of step four,

Figure 6 is a schematic diagram of step five,

Figure 7 is a schematic diagram of step six,

Figure 8 is a schematic diagram of step seven,

Figure 9 is a schematic diagram of Step 8,

Figure 10 is a schematic diagram of step nine,

Figure 11 is a schematic diagram of step ten,

Fig. 12 is a schematic diagram of step eleven.

Explanation of reference signs:

1. Single crystal silicon substrate; 2. Wafer insulating layer; 3. Emitter region; 4. Base region; 5. Collector region; 6. Conductive layer; 7. Tunneling insulating layer; 8. Gate electrode; 9. Emitter; 10, collector; 11, blocking insulating layer.

detailed description

Below in conjunction with accompanying drawing, the present invention will be further described:

Figure 1 is a schematic diagram of a two-dimensional structure of an embedded gate insulation tunneling enhancement transistor formed on a bulk silicon substrate in the present invention; specifically, it includes a single crystal silicon substrate 1; a wafer insulating layer 2; an emitter region 3; a base region 4; Collector region 5; conductive layer 6; tunnel insulating layer 7; gate electrode 8; emitter 9; collector 10; blocking insulating layer 11.

High transfer characteristics and low parasitic capacitance Embedded gate insulation tunneling enhancement transistor, using a bulk silicon wafer containing only a single crystal silicon substrate 1 as the device substrate, or using a single crystal silicon substrate 1 and a wafer insulating layer at the same time 2 of the SOI wafer as the substrate for generating devices; the emitter region 3, the base region 4 and the collector region 5 are located above the single crystal silicon substrate 1 of the bulk silicon wafer or the wafer insulating layer 2 of the SOI wafer; The electrode 9 is located above the emitter region 3; the collector electrode 10 is located above the collector region 5; the conductive layer 6 is embedded in the base region 4 and surrounded by three sides of the base region 4; the tunnel insulating layer 7 is embedded in the conductive layer 6 and surrounded by the conductive layer 6 on three sides; the gate electrode 8 is embedded in the tunneling insulating layer 7 and surrounded by the tunneling insulating layer 7 on three sides; the blocking insulating layer 11 is located between the device units and between the electrodes, for each Between the device units and between the electrodes play an isolation role.

In order to achieve the device functions described in the present invention, the present invention proposes a high transfer characteristic and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, and its core structural features are:

The gate electrode 8 , the tunneling insulating layer 7 and the conductive layer 6 are all embedded in the base region 4 , and only the upper surface is in contact with the blocking insulating layer 11 .

A tunnel insulating layer 7, a conductive layer 6 and a base region 4 are sequentially interposed between the gate electrode 8 and the emitter region 3;

A tunnel insulating layer 7, a conductive layer 6 and a base region 4 are sequentially sandwiched between the gate electrode 8 and the collector region 4;

The gate electrode 8 is an electrode for controlling the tunneling effect generated by the tunneling insulating layer 7, and is an electrode for controlling the turning on and off of the device.

The tunneling insulating layer 7 is an insulating layer for generating gate insulating layer tunneling current.

The conductive layer 6 forms an ohmic contact with the base region 4 and is a metal material, or a semiconductor material having the same impurity type as the base region 4 and a doping concentration greater than 10 ¹⁸ per cubic centimeter.

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 3 and the collector electrode 10. ohmic contact.

High transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, taking N-type as an example, the emitter region 3, base region 4 and collector region 5 are N region, P region and N region respectively, and its specific working principle is : When the collector electrode 10 is positively biased and the gate electrode 8 is at a low potential, there is no sufficient potential difference formed between the gate electrode 8 and the conductive layer 6, and the tunneling insulating layer 7 is in a high-resistance state at this time, and no obvious tunneling current passes through , so that it is impossible to form a large enough base current between the base region 4 and the emitter region 3 to drive the embedded gate insulation tunneling enhancement transistor with high transfer characteristics and low parasitic capacitance, that is, the device is in the off state; with the voltage of the gate electrode 8 gradually increases, the potential difference between the gate electrode 8 and the conductive layer 6 gradually increases, so that the electric field intensity in the tunneling insulating layer 7 between the gate electrode 8 and the conductive layer 6 also gradually increases, when the tunneling When the electric field strength in the insulating layer 7 is below the critical value, the tunneling insulating layer 7 still maintains a good high-resistance state, and the potential difference between the gate electrode and the emitter is almost completely dropped on both sides of the inner and outer walls of the tunneling insulating layer 7 Between the base region and the emitter region, the potential difference between the base region and the emitter region is extremely small, so there is almost no current flowing in the base region, and the device remains in a good off state. When the electric field strength in the tunneling insulating layer 7 is at the critical When the value is above , the tunneling insulating layer 7 will generate obvious tunneling current due to the tunneling effect, and the tunneling current will rise steeply at a very fast speed with the increase of the potential of the gate electrode 8, which makes the tunneling The insulating layer 7 rapidly switches from a high-resistance state to a low-resistance state during the extremely short potential change interval of the gate electrode. The resistance formed between the conductive layer 6 and the emitter 3 is much smaller than the resistance formed between the conductive layer 6 and the emitter 3, which makes a sufficiently large forward bias voltage formed between the base region 4 and the emitter region 3, and in the tunneling effect Under the action, a large amount of electron movement is generated between the inner wall and the outer wall of the tunneling insulating layer 7, that is, a current source is provided for the base region 4, so that a sufficiently large base region current is formed between the base region 4 and the emitter region 3 to drive High transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, that is, the device is in the on state;

High transfer characteristics and low parasitic capacitance Embedded gate insulation tunneling enhancement transistor, using the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, through the tunneling insulating layer embedded in the base region 4 7 Select an appropriate tunnel insulating material, and properly adjust the depth of embedding and the thickness of the tunnel insulating layer 7, so that the tunnel insulating layer 7 can achieve high resistance and low resistance within the extremely small potential change range of the gate electrode. The transition between states, and the tunneling current generated on the tunneling insulating layer 7 is used as the driving current to induce a large amount of electron current flowing out of the emitter collection, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands as the conduction of the device. Compared with the passing current, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary structure MOSFETs, TFETs or ordinary bipolar transistors, high transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistors, Higher transfer characteristics can be achieved.

High transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, compared with MOSFETs or TFETs, the role of the emitter 9 and the source electrode is equivalent, and the role of the collector 10 and the drain electrode is equivalent, because the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 are all embedded in the base region 4, and only the upper surface is in contact with the blocking insulating layer 11 and away from the emitter 9 and the collector 10, which avoids the gate electrode and the collector electrode 10 like MOSFETs or TFETs. The significant increase in the parasitic capacitance between the gate-source, source-gate, gate-drain, and drain-gate due to the shrinking distance between the drain electrodes or between the gate electrode and the source electrode makes the device reduce the Parasitic capacitance generated by MOSFETs or TFETs of the same size.

High transfer characteristics and low parasitic capacitance embedded gate insulation tunneling enhancement transistor, because the distance between the gate electrode 8 and the emitter region 3 or the collector region 5 depends on the sum of the horizontal lengths of the tunneling insulating layer 7 and the conductive layer 6, and Compared with MOSFETs or TFETs, there is no gate-to-drain overlap region between the gate electrode 8 and the emitter region 3, or between the gate electrode 8 and the collector electrode, which MOSFETs or TFETs have, so no significant reaction is caused. to the leakage current.

The specific manufacturing process steps of the cells and arrays of the embedded gate insulation tunneling enhancement transistor with high transfer characteristics and low parasitic capacitance on the bulk silicon wafer proposed by the present invention are as follows:

Step 1, as shown in Figure 2, provide an SOI wafer, the bottom of the SOI wafer is the monocrystalline silicon substrate 1 of the SOI wafer, the middle of the SOI wafer is the wafer insulating layer 2, and the single crystal silicon substrate 1 above the SOI wafer The crystalline silicon thin film is used to form the emitter region 3, the base region 4 and the collector region 5 of the device, and a rectangular parallelepiped single crystal silicon island as shown in Figure 2 is formed on the provided SOI wafer through photolithography, etching and other processes An array area, which is used to further form the emitter region 3, the base region 4 and the collector region 5 of the device;

Step 2, as shown in FIG. 3, after depositing an insulating medium on the wafer, the surface is planarized, and a blocking insulating layer 11 is preliminarily formed;

Step 3, as shown in Figure 4, through the ion implantation process, an emitter region 3, a base region 4 and a collector region 5 are formed on each region of the rectangular parallelepiped single crystal silicon island array, wherein the doping type of the base region 4 must be Contrary to the emitter region 3 and the collector region 5;

Step 4, as shown in FIG. 5 , a groove-shaped region is etched on the base region 4 through an etching process.

Step five, as shown in Figure 6, deposit metal or over-doped polysilicon with the same impurity type as the base region 4 above the wafer, so that the inside of the groove formed in step four is completely filled, and then the surface is flattened Thinning to expose the base region 4, initially forming the conductive layer 6;

Step 6. As shown in FIG. 7 , a groove-shaped region is etched on the conductive layer 6 through an etching process to further form the conductive layer 6 .

Step 7, as shown in Figure 8, deposit a tunneling insulating layer dielectric on the wafer, so that the inside of the groove formed in step 6 is completely filled, and then planarize the surface to expose the conductive layer 6, initially forming a tunnel insulating layer 7;

Step 8. As shown in FIG. 9 , a groove-shaped region is etched on the tunneling insulating layer 7 through an etching process to further form the tunneling insulating layer 7 .

Step 9, as shown in FIG. 10 , deposit metal material or heavily doped polysilicon on the wafer, so that the inside of the groove formed in step 8 is completely filled, and then planarize the surface to expose the tunnel insulating layer 7, forming the gate electrode 8;

Step ten, as shown in FIG. 11 , deposit an insulating dielectric layer on the wafer and planarize the surface, and further form a blocking insulating layer 11;

Step eleven, as shown in FIG. 12 , etch through holes for forming the emitter 9 and the collector 10 inside the blocking insulating layer 11 above the emitter region 3 and the collector region 5 , and place the holes on the wafer A metal layer is deposited on the surface to fill the through hole with metal, and then the metal layer is etched to form the emitter 9 and the collector 10 .

Claims (10)

1. embedded gate insulation tunnelling enhancing transistor, it is characterised in that：Using only comprising monocrystalline substrate（1）Body Silicon Wafer make Monocrystalline substrate is included simultaneously for generating device substrate, or use（1）With wafer insulating barrier（2）SOI wafer be used as maker The substrate of part；Launch site（3）, base（4）And collecting zone（5）Positioned at the monocrystalline substrate of body Silicon Wafer（1）Or the crystalline substance of SOI wafer Circle insulating barrier（2）Top；Emitter stage（9）Positioned at launch site（3）Top；Colelctor electrode（10）Positioned at collecting zone（5）Top； Conductive layer（6）It is embedded in base（4）It is interior, and by base（4）Three bread enclose；Tunneling insulation layer（7）It is embedded in conductive layer（6）It is interior, And by conductive layer（6）Three bread enclose；Gate electrode（8）It is embedded in tunneling insulation layer（7）It is interior, and it is tunneled over insulating barrier（7）Three bread Enclose；Barrier insulating layer（11）Embedding gate insulation tunnelling positioned at single high transfer characteristic low parasitic capacitance strengthens the top of transistor.

2. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Emitter stage（9）With current collection Pole（10）Between pass through barrier insulating layer（11）Isolation；Launch site（3）With collecting zone（5）Between pass through barrier insulating layer（11）Every From.

3. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Gate electrode（8）, tunnelling it is exhausted Edge layer（7）And conductive layer（6）It is embedded in base（4）It is interior, only upper surface and barrier insulating layer（11）Contact.

4. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Gate electrode（8）With transmitting Area（3）Between accompany tunneling insulation layer successively（7）, conductive layer（6）And base（4）.

5. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Gate electrode（8）With current collection Area（5）Between accompany tunneling insulation layer successively（7）, conductive layer（6）And base（4）.

6. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Gate electrode（8）It is control Tunneling insulation layer（7）The electrode of tunneling effect is produced, is the electrode that control device is switched on and off.

7. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Tunneling insulation layer（7）For Insulating barrier for producing gate insulation layer tunnelling current.

8. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Conductive layer（6）With base （4）Form Ohmic contact, conductive layer（6）It is metal material either same base（4）It is with identical dopant type and adulterate it is dense Degree is more than 10¹⁸Semi-conducting material per cubic centimeter.

9. embedded gate insulation tunnelling enhancing transistor according to claim 1, it is characterised in that：Launch site（3）With base （4）Between, collecting zone（5）With base（4）Between there is opposite impurity type, and launch site（3）With emitter stage（9）Between formed Ohmic contact, collecting zone（5）With colelctor electrode（10）Between form Ohmic contact.

10. a kind of embedded gate insulation tunnelling as claimed in claim 1 strengthens the manufacture method of transistor, it is characterised in that：Should Processing step is as follows：

Step 1: providing a SOI wafer, the lower section of SOI wafer is the monocrystalline substrate of SOI wafer（1）, in SOI wafer Between be wafer insulating barrier（2）, the monocrystalline silicon thin film above SOI wafer is used for the launch site for forming device（3）, base（4）And collection Electric area（5）, rectangular-shape monocrystalline silicon isolated island array region is provided by photoetching, etching technics in the SOI wafer provided, should Region is used for the launch site for further forming device（3）, base（4）And collecting zone（5）；

Step 2: planarizing surface after deposit dielectric above wafer, barrier insulating layer is preliminarily formed（11）；

Step 3: by ion implantation technology, launch site is formed on each region of rectangular-shape monocrystalline silicon isolated island array （3）, base（4）And collecting zone（5）, wherein base（4）Doping type will and launch site（3）And collecting zone（5）Conversely；

Step 4: by etching technics, in base（4）On etch grooved regions；

Step 5: depositing metal above wafer or having and base（4）The polysilicon of the overweight doping of identical dopant type, makes Inside grooves formed in step 4 are completely filled, then by surface planarisation to exposing base（4）, preliminarily form conductive layer （6）；

Step 6: by etching technics, in conductive layer（6）On etch grooved regions, further form conductive layer（6）；

Step 7: depositing tunneling insulation layer medium above wafer, it is completely filled the inside grooves formed in step 6, Again by surface planarisation to exposing conductive layer（6）, preliminarily form tunneling insulation layer（7）；

Step 8: by etching technics, in tunneling insulation layer（7）On etch grooved regions, further formed tunnelling insulation Layer（7）；

Step 9: depositing metal material or heavily doped polysilicon above wafer, make the inside grooves formed in step 8 complete It is filled entirely, then by surface planarisation to exposing tunneling insulation layer（7）, form gate electrode（8）；

Step 10: depositing insulating medium layer above wafer and planarizing surface, barrier insulating layer is further formed（11）；

Step 11: positioned at launch site（3）And collecting zone（5）Top barrier insulating layer（11）Inside is etched for shape Into emitter stage（9）And colelctor electrode（10）Through hole, and in wafer upper surface deposited metal, be filled with metal through hole, then right Metal level is performed etching, and forms emitter stage（9）And colelctor electrode（10）.