CN104282737B - High-integration-level H-shaped source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor - Google Patents

Abstract

The invention relates to a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor, which adopts two gate electrodes controlled independently of each other, such as an H-shaped assisted control gate electrode and a gate electrode, to ensure that the device is reduced The doping concentration is used to increase the mobility, avoiding the decrease of device mobility and stability caused by the enhancement of random scattering effect under high doping concentration, and at the same time, the H-shaped auxiliary control gate electrode is used to effectively reduce the resistance of the source and drain regions, thereby solving the problem of The low doping concentration of the channel of ordinary junctionless transistors will lead to the increase of the source-drain resistance, while the high doping concentration will lead to the decrease of device mobility and stability. At the same time, the U-shaped single crystal Silicon is used as the channel part of the device. Compared with the ordinary planar structure, the effective channel length is significantly increased to reduce the short channel effect of the device at the deep nanoscale without additional increase in the chip area, so it is suitable for popularization and application.

Description

Highly integrated H-shaped source-drain-gate assisted control U-shaped channel high mobility junctionless transistor

technical field

The invention belongs to the field of ultra-large-scale integrated circuit manufacturing, and in particular relates to a high-integration H-shaped source-drain-gate auxiliary control U-shaped channel high-mobility junction-free transistor structure suitable for ultra-high integrated integrated circuit manufacturing.

Background technique

The basic unit of integrated circuits, MOSFETs, transistors, with the continuous reduction in size, need to achieve multiple orders of magnitude concentration differences within a distance of several nanometers to form extremely steep source and drain PN junctions. Such a concentration gradient is essential for doping And heat treatment process has extremely high requirements. The above problems can be effectively solved by junction-free field-effect transistors fabricated on SOI wafers. Junction-free transistors adopt multi-subconduction, and the source, drain and channel regions of the device have the same high doping concentration. The characteristics of making the silicon film thin enough, taking N-type devices as an example, when the gate is under reverse bias, because the silicon film is very thin, the electrons in the channel region are easily depleted under the action of the gate electric field, A blocking state of the device is thereby achieved. As the gate bias increases, the multi-sub-depletion in the channel region is relieved, and electron accumulation is formed at the interface to realize device turn-on. However, such a channel with high doping concentration will lead to a significant decrease in the mobility of the device, and the random scattering of impurities will seriously affect the reliability of the device. In order to improve the mobility and reliability of junction-free devices, it is necessary to reduce the doping concentration of the silicon thin film. However, the reduction of the doping concentration will increase the source-drain resistance and affect the turn-on characteristics of the device. In addition, the common transistor structure based on the planar structure, with the continuous shortening of the channel length, the short channel effect is gradually enhanced, and the device is difficult to turn off. Therefore, in order to solve the above-mentioned problems existing in existing transistors, it is necessary to design a junction-free transistor capable of overcoming the short-channel effect and having high integration and high mobility.

Contents of the invention

purpose of invention

In order to solve the contradictory relationship between the mobility of junctionless transistors and the source-drain resistance and overcome the short channel effect of ordinary planar structure transistors, the present invention provides a highly integrated H-shaped source-drain-gate assisted control U-shaped channel high Mobility Junctionless Transistor Structures.

Technical solutions

The present invention is achieved through the following technical solutions:

A highly integrated H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor, including a silicon substrate of an SOI wafer, and an insulating layer of the SOI wafer above the silicon substrate of the SOI wafer; its characteristics The reason is: the top of the insulating layer of the SOI wafer is U-shaped single crystal silicon, the surface of the U-shaped single crystal silicon is attached with a gate insulating layer, and the adjacent U-shaped single crystal silicon is separated by an insulating dielectric layer; the gate insulating layer A gate electrode is attached to the surface, and above the gate electrode is an H-shaped auxiliary control gate electrode. An insulating dielectric layer is provided between the H-shaped auxiliary control gate electrode and the gate electrode, and is insulated from the gate electrode through the insulating dielectric layer. The U-shaped single crystal silicon An insulating dielectric layer is deposited on the upper surface of the U-shaped single crystal silicon through an etching process, and the insulating dielectric layer on the upper surface of both ends of the U-shaped single crystal silicon is etched away, and metal is injected into the etched through hole to form a source electrode and a drain electrode respectively. pole.

The two electrodes of the H-shaped auxiliary control gate electrode and the gate electrode are electrodes controlled independently of each other, and the two are insulated from each other through an insulating dielectric layer. Forming three-sided surroundings, it plays a major role in controlling the electric field, potential and carrier distribution at the upper ends of the two vertical parts of the U-shaped single crystal silicon, while the gate electrode is located below the H-shaped auxiliary control gate electrode. The vertical part and the horizontal part of the crystalline silicon except two ends form a three-sided surround, and play a major role in controlling the internal electric field, potential and carrier distribution. Among them, the H-shaped auxiliary control gate electrode is always at a high potential, so that the parts at both ends of the upper surface of the U-shaped single crystal silicon form electron accumulation, thereby reducing the resistance value of the upper surface of the U-shaped single crystal silicon as the source region and drain region of the device. , so that both ends are always in a low-resistance state, that is, the source-drain resistance is effectively reduced.

U-shaped single crystal silicon is used as the channel part of the device, which is formed of high-mobility single crystal silicon material with a doping concentration lower than 10 ¹⁷ cm ^-3 . Compared with ordinary junction-free transistors with high doping concentration, the channel of the device Partly due to the low doping concentration, there is no significant decrease in device mobility due to the enhanced scattering effect of dopant impurities at high concentrations.

The gate insulating layer is an insulating material dielectric layer or a silicon dioxide layer with a high dielectric constant.

A gate insulating layer is attached to the U-shaped single crystal silicon except for the surfaces on both sides in contact with the insulating dielectric layer; a gate electrode is attached to the parts of the gate insulating layer except for the surfaces in contact with the insulating dielectric layer on both sides.

Advantages and effects

The present invention has following advantage and beneficial effect:

1. Since the present invention adopts the H-shaped auxiliary control gate electrode and the gate electrode, which are independently controlled gate electrodes, the channel of the device can still pass through the H-shaped gate electrode at low doping concentration while ensuring high mobility. The independent control of the auxiliary control gate electrode obtains a lower source-drain resistance, thereby effectively solving the problem that the low doping concentration of the channel of ordinary junctionless transistors will increase the source-drain resistance and affect the turn-on characteristics of the device.

2. The present invention uses U-shaped single crystal silicon as the channel part of the device, and the channels formed by the vertical parts on both sides of the U-shaped single crystal silicon are located under the source electrode and the drain electrode respectively. On the premise of occupying an additional chip area, the effective channel length of the device is increased, thus helping the device to overcome the influence of the short channel effect.

3. The H-shaped auxiliary control gate electrode and gate electrode used in the present invention have the structural feature of forming three sides surrounding each part of the U-shaped single crystal silicon. This structural feature makes the H-shaped auxiliary control gate electrode and the gate electrode pair U-shaped. The ability to control the electric field, potential and carrier distribution in single crystal silicon is enhanced, which is conducive to assisting in improving the device to overcome the influence of the short channel effect, and is conducive to improving the sub-threshold characteristics of the device, so that the device has a steeper sub-threshold slope for better switching characteristics.

Description of drawings

Fig. 1 is a schematic diagram of a three-dimensional structure of a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor formed on an SOI substrate;

2 is a top view of the highly integrated H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor formed on the SOI substrate of the present invention;

Fig. 3 is a schematic diagram of a three-dimensional structure of a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor of the present invention after peeling off the insulating dielectric layer located on the upper surface of the device;

Fig. 4 is a top view of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor of the present invention after peeling off the part of the insulating dielectric layer located on the upper surface of the device;

Fig. 5 is a schematic diagram of a three-dimensional structure of a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor based on the above-mentioned basis after stripping the source electrode and the drain electrode;

Fig. 6 is a top view of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor of the present invention after the source electrode and drain electrode are stripped on the above basis;

7 is a schematic diagram of a three-dimensional structure of a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor based on the above-mentioned basis after the H-shaped assisted control gate electrode is stripped;

8 is a top view of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor of the present invention after the H-shaped assisted control gate electrode is stripped on the above basis;

Fig. 9 is a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor of the present invention after stripping the insulating dielectric layer between the H-shaped assisted control gate electrode and the gate electrode on the basis of the above. 3D structure diagram;

Fig. 10 is a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor of the present invention after stripping the insulating dielectric layer between the H-shaped assisted control gate electrode and the gate electrode on the basis of the above. top view;

Fig. 11 is a schematic diagram of the three-dimensional structure of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor of the present invention after the gate electrode is stripped on the above basis;

Fig. 12 is a top view of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor of the present invention after the gate electrode is stripped on the above basis;

Fig. 13 is a three-dimensional schematic diagram of the high-integration H-shaped source-drain-gate assisted U-shaped channel high-mobility junction-free transistor of the present invention after stripping off the gate insulating layer on the above basis;

Fig. 14 is a top view of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor of the present invention after stripping off the gate insulating layer on the above basis;

Fig. 15 to Fig. 32 are process flow charts of a specific example of the preparation method of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor structural unit of the present invention.

Figure 15 is a schematic diagram of Step 1,

Figure 16 is a top view of step one,

Figure 17 is a schematic diagram of step two,

Figure 18 is a top view of step two,

Figure 19 is a schematic diagram of step three,

Figure 20 is a top view of Step 3,

Figure 21 is a schematic diagram of Step 4,

Figure 22 is a plan view of Step 4,

Figure 23 is a schematic diagram of step five,

Figure 24 is a top view of Step 5,

Figure 25 is a schematic diagram of step six,

Figure 26 is a top view of step six,

Figure 27 is a schematic diagram of step seven,

Figure 28 is a top view of step seven,

Figure 29 is a schematic diagram of Step 8,

Figure 30 is a top view of Step 8,

Figure 31 is a schematic diagram of step nine,

Fig. 32 is a plan view of step nine.

The reference sign says:

1. Source electrode; 2. Drain electrode; 3. H-shaped auxiliary control gate electrode; 4. Gate electrode; 5. Gate insulating layer; 6. Insulating dielectric layer; 7. U-shaped single crystal silicon; 8. SOI wafer 9. Silicon substrate of SOI wafer.

detailed description

Below in conjunction with accompanying drawing, the present invention will be further described:

The present invention provides a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor. Through the joint action of the H-shaped assisted control gate electrode 3 and the gate electrode 4, which are independently controlled electrodes, Under the condition of low doping concentration, a junction-free transistor with high mobility and low source-drain resistance is realized. Taking the N-type as an example, when the device is working, the H-shaped auxiliary control gate electrode 3 always maintains a constant high potential, so that the left and right sides of the H-shaped auxiliary control gate electrode 3 are respectively located under the source electrode 1 and the drain electrode 2. The left and right ends of the U-shaped single crystal silicon 7 form electron accumulation, and the accumulated electrons enhance the conductivity of the left and right ends of the U-shaped single crystal silicon 7 as the source region and drain region of the device, which effectively reduces the source-drain resistance; And the gate electrode 4 is the gate electrode that actually controls the device to be turned on or off. When the gate electrode 4 is at a low potential, the electrons in the U-shaped single crystal silicon 7 located on the left, right and lower sides of the gate electrode 4 are on the gate electrode 4. Under the electric field effect, it is emptied, so that the U-shaped channel formed by the U-shaped single crystal silicon 7 is in a pinch-off state, so the device is in an off state at this time, and as the potential of the gate electrode 4 gradually increases, the U-shaped single crystal The number of electrons in the U-shaped channel formed by the silicon 7 also gradually increases. When the gate electrode 4 is at a high potential, under the action of the electric field effect, a large number of electrons are formed in the U-shaped single crystal silicon 7 and the gate insulating layer 5 Electron accumulation is formed at the interface of the U-shaped single crystal silicon 7, so that the U-shaped channel formed by the U-shaped single crystal silicon 7 is in the open state, so the device is in the open state at this time, and the H-shaped source-drain-gate auxiliary control with high integration is realized through the above-mentioned specific implementation methods U-shaped channel high mobility junctionless transistor.

In order to achieve the device functions described in the present invention, the highly integrated H-shaped source-drain-gate assisted U-shaped channel high-mobility junction-free transistor proposed by the present invention has the following core structural features:

1. In order to make the device have high mobility, the U-shaped single crystal silicon 7 is formed of a high-mobility single crystal silicon material with a doping concentration lower than 10 ¹⁷ cm ^-3 ; to enhance the H-shaped auxiliary control gate electrode 3 and gate electrode 4 For the ability to control the carrier concentration distribution of each part in the U-shaped single crystal silicon 7, the gate insulating layer 5 can be an insulating material dielectric layer with a high dielectric constant, but it can also be a silicon dioxide layer.

2. As one of the independently controlled gate electrodes, the H-shaped auxiliary control gate electrode 3 plays a major control role on the vertical parts on both sides of the U-shaped monocrystalline silicon 7 adjacent to the two ends of the source electrode 1 and the drain electrode 2. The H-shaped structural feature is adopted, so that the H-shaped auxiliary control gate electrode 3 forms three sides around the two ends of the vertical parts on both sides of the U-shaped single crystal silicon 7 adjacent to the source electrode 1 and the drain electrode 2, which helps to strengthen the H-shaped auxiliary control. The ability of the gate electrode 3 to control the electric field, potential and carrier distribution of the source region and the drain region keeps a constant high potential when the device is working, so that the left and right ends of the U-shaped single crystal silicon 7 form a concentration higher than 10 ²⁰ cm ^{- 3} , the accumulated electrons enhance the conductivity of the vertical parts on both sides of the U-shaped single crystal silicon 7 as the source and drain regions of the device, which are adjacent to the two ends of the source electrode 1 and the drain electrode 2, which effectively reduces the source and drain resistance;

3. The gate electrode 4, as one of the independently controlled gate electrodes, is the gate electrode that actually controls the device to be turned on or off, and is adjacent to the vertical parts on both sides controlled by the H-shaped auxiliary control gate electrode 3 in the U-shaped single crystal silicon 7 The other parts other than the two ends of the source electrode 1 and the drain electrode 2 play a major control role. When the gate electrode 4 is at a low potential, the electrons in the U-shaped single crystal silicon 7 located on the left, right and lower sides of the gate electrode 4 are in the gate electrode. 4 is emptied under the electric field effect, so that the U-shaped channel formed by the U-shaped single crystal silicon 7 is in a pinch-off state, so the device is in an off state at this time, and as the potential of the gate electrode 4 gradually increases, the U-shaped channel The number of electrons in the U-shaped channel formed by the single crystal silicon 7 also gradually increases. When the gate electrode 4 is at a high potential, under the action of the electric field effect, a large number of electrons are formed in the U-shaped single crystal silicon 7 and the gate insulation. Electron accumulation is formed at the interface of the layer 5, so that the U-shaped channel formed by the U-shaped single crystal silicon 7 is in the open state, so the device is in the open state at this time, and the gate electrode 4 also forms three sides around the U-shaped single crystal silicon 7, Therefore, the control ability of the gate electrode 4 on the electric field, potential and carrier distribution in the U-shaped single crystal silicon 7 is enhanced, which helps to reduce the short channel effect of the device, and increases the subthreshold slope to improve the switching characteristics of the device.

4. The gate electrode 4 and the H-shaped auxiliary control gate electrode 3 are insulated from each other by an insulating dielectric layer 6 .

5. The present invention uses U-shaped single crystal silicon as the channel part of the device, and the vertical channel parts on both sides are respectively located under the source electrode and the drain electrode. Compared with the ordinary planar structure, it does not occupy an additional chip area. Next, the effective channel length of the device is increased, thus helping the device to overcome the influence of the short channel effect.

Below in conjunction with accompanying drawing, the present invention will be further described:

Figure 1 is a schematic diagram of the three-dimensional structure of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor formed on the SOI substrate of the present invention; Figure 2 is a highly integrated H-shaped source-drain gate of the present invention A top view of the high-mobility junction-free transistor with assisted control U-shaped channel formed on the SOI substrate; FIG. Schematic diagram of the three-dimensional structure of the dielectric layer behind the upper surface of the device; specifically includes the silicon substrate 9 of the SOI wafer, and above the silicon substrate 9 of the SOI wafer is the insulating layer 8 of the SOI wafer; above the insulating layer 8 of the SOI wafer It is a U-shaped single crystal silicon 7, the surface of the U-shaped single crystal silicon 7 is attached with a gate insulating layer 5, and the adjacent U-shaped single crystal silicon 7 is isolated by an insulating dielectric layer 6; the surface of the gate insulating layer 5 is attached with Gate electrode 4, above the gate electrode 4 is an H-shaped auxiliary control gate electrode 3, which is insulated and isolated from the gate electrode 4 by an insulating dielectric layer 6, and an insulating dielectric layer 6 is deposited on the upper surface of the U-shaped single crystal silicon 7, and is formed by engraving The etching process etches away the insulating dielectric layer 6 on the upper surface of the U-shaped single crystal silicon 7, and injects metal into the etched through holes to form the source electrode 1 and the drain electrode 2 respectively; as shown in Figure 4, the present invention provides A schematic diagram of a three-dimensional structure of a highly integrated H-shaped source-drain-gate-assisted U-shaped channel high-mobility junctionless transistor after peeling off the part of the insulating dielectric layer 6 on the upper surface of the device, the source electrode 1 and the drain electrode 2; Fig. 5 is a top view of a high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junctionless transistor provided by the present invention after peeling off the insulating dielectric layer 6, source electrode 1 and drain electrode 2; Fig. 6 A high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor provided by the present invention peels off the insulating dielectric layer 6 on the upper surface of the device and is located between the H-shaped assisted control gate electrode 3 and the gate electrode 4, the three-dimensional structural schematic diagram of the source electrode 1, the drain electrode 2 and the H-shaped auxiliary control gate electrode 3; FIG. 7 is a highly integrated H-shaped source-drain-gate auxiliary control U-shaped channel provided by the present invention In the high-mobility junctionless transistor, the insulating dielectric layer 6 is peeled off on the upper surface of the device and the part between the H-shaped auxiliary control gate electrode 3 and the gate electrode 4, the source electrode 1, the drain electrode 2 and the H-shaped auxiliary control gate electrode 3 Subsequent top view; the doping concentration of the U-shaped single crystal silicon 7 is set to be lower than 10 ¹⁷ cm ^-3 ; in order to enhance the internal electric field, potential and loading of the U-shaped single crystal silicon 7 to the H-shaped auxiliary control gate electrode 3 and gate electrode 4 In order to control the flow carrier distribution, the gate insulating layer 5 can be a dielectric layer of insulating material with a high dielectric constant, or can be a common silicon dioxide material.

The specific manufacturing process steps of the unit and the array of the high-integration H-shaped source-drain-gate assisted control U-shaped channel high-mobility junction-free transistor proposed by the present invention are as follows:

Step 1: Provide an SOI wafer with a doping concentration lower than 10 ¹⁷ cm ⁻³ , the silicon substrate 9 of the SOI wafer is below the SOI wafer, and the silicon substrate 9 for forming the U-shaped single crystal silicon 7 is above the SOI wafer. A single crystal silicon thin film, between which is the insulating layer 8 of the SOI wafer, forms a series on the insulating layer 8 of the provided SOI wafer through photolithography, etching and other processes, as shown in Figure 15 and Figure 16, The shown cuboid is used to form a U-shaped single crystal silicon 7;

Step 2, as shown in Figure 17 and Figure 18, after depositing an insulating medium above the wafer, the surface is flattened to form an insulating medium layer 6, which is used for isolation between device units;

Step 3, as shown in Fig. 19 and Fig. 20, the cuboid single crystal silicon film is etched into a U-shaped single crystal silicon film through an etching process, so as to further generate a U-shaped single crystal silicon 7;

Step 4, as shown in Figure 21 and Figure 22, on the basis of the above steps, continue to remove the parts on both sides of the single crystal silicon film through the etching process, so as to finally form a U-shaped single crystal silicon 7 used as the channel part of the device ;

Step 5, as shown in Figure 23 and Figure 24, on the basis of the above steps, an insulating medium with a high dielectric constant is deposited on the surface of the wafer, and the surface is polished;

Step 6. As shown in FIG. 25 and FIG. 26 , on the basis of the above steps, the insulating medium with high dielectric constant in the middle and on both sides is etched away by etching process, so as to form the gate insulating layer 7 ;

Step 7, as shown in Figure 27 and Figure 28, on the basis of the above steps, metal or polysilicon is deposited on the surface of the wafer, and the gate electrode 4 is formed by an etching process after polishing the surface;

Step 8. As shown in FIG. 29 and FIG. 30 , on the basis of the above steps, an insulating dielectric layer is deposited on the surface of the wafer, and after polishing the surface, an insulating dielectric layer 6 is further formed by an etching process.

Step 9, as shown in Figure 31 and Figure 32, on the basis of the above steps, deposit metal or polysilicon on the surface of the wafer again and polish the surface, so as to generate the H-shaped auxiliary control gate electrode 3;

Step 10. On the basis of the above steps, deposit an insulating medium on the surface of the wafer to further generate an insulating medium layer 6. After polishing the surface, etch off the insulating medium layer on the upper surface of the U-shaped single crystal silicon 7 through an etching process 6 to generate source and drain via holes, and inject metal into source and drain via holes respectively to generate source electrode 1 and drain electrode 2, as shown in Figure 1 and Figure 2, the high Integrated H-shaped source-drain-gate assisted U-shaped channel high-mobility junction-free transistor.

Claims (5)

1. a kind of silicon substrate of high integration H-shaped source and drain grid auxiliary control U-shaped raceway groove high mobility nodeless mesh body pipe, including SOI wafer （9）, the silicon substrate of SOI wafer（9）Top is the insulating barrier of SOI wafer（8）；It is characterized in that：The insulating barrier of SOI wafer（8） Top is U-shaped monocrystalline silicon（7）, U-shaped monocrystalline silicon（7）Surface have gate insulator（5）, adjacent U-shaped monocrystalline silicon（7）Between By insulating medium layer（6）Isolation；Gate insulator（5）Has gate electrode in surface（4）, gate electrode（4）Top is H-shaped auxiliary control grid Electrode（3）, H-shaped auxiliary control gate electrode（3）With gate electrode（4）Between be provided with insulating medium layer（6）, and by insulating medium layer（6） With gate electrode（4）It is dielectrically separated from, U-shaped monocrystalline silicon（7）Upper surface be deposited with insulating medium layer（6）, and carved by etching technics Eating away U-shaped monocrystalline silicon（7）The insulating medium layer of two ends upper surface（6）, and injection metal is generated respectively in the through hole for etching away It is source electrode（1）And drain electrode（2）.

2. high integration H-shaped source and drain grid auxiliary control U-shaped raceway groove high mobility nodeless mesh body pipe according to claim 1, it is special Levy and be：H-shaped auxiliary control gate electrode（3）And gate electrode（4）The two electrodes are the electrode of control independent of one another, and the two is by insulation Dielectric layer（6）Realize insulated from each other, wherein H-shaped auxiliary control gate electrode（3）To U-shaped monocrystalline silicon（7）Two upper ends of vertical component Three faces are formed around and gate electrode（4）Then it is located at H-shaped auxiliary control gate electrode（3）Lower section.

3. high integration H-shaped source and drain grid auxiliary control U-shaped raceway groove high mobility nodeless mesh body pipe according to claim 1, it is special Levy and be：U-shaped monocrystalline silicon（7）As the raceway groove part of device, 10 are less than by doping concentration¹⁷cm^-3High mobility monocrystalline silicon material Material is formed.

4. high integration H-shaped source and drain grid auxiliary control U-shaped raceway groove high mobility nodeless mesh body pipe according to claim 1, it is special Levy and be：Gate insulator（7）It is insulating materials dielectric layer or silicon dioxide layer with high-k.

5. high integration H-shaped source and drain grid auxiliary control U-shaped raceway groove high mobility nodeless mesh body pipe according to claim 1, it is special Levy and be：U-shaped monocrystalline silicon（7）Except both sides and insulating medium layer（6）Has gate insulator in the position outside surface being in contact （5）；Gate insulator（5）Except both sides and insulating medium layer（6）Has gate electrode in the position outside surface being in contact（4）.