CN107833926B - Square cylindrical gate embedded U-shaped channel field effect transistor and its manufacturing method - Google Patents

Abstract

The invention relates to a high-integration-level square cylindrical gate embedded U-shaped channel field effect transistor and a manufacturing method thereof. In the groove formed by the U-shaped monocrystalline silicon, only an insulating medium needs to be filled to realize the mutual isolation of the vertical channels at two sides, a metal material or a polycrystalline silicon material for generating a gate electrode does not need to be introduced into the groove, the internal structure of the groove is relatively simple, and the highly integrated metal oxide semiconductor field effect transistor with the physical gate electrode length of only 1 nanometer in the traditional sense, namely the distance between a source electrode and a drain electrode is only 1 nanometer can be realized. The invention adopts the square cylindrical gate electrode, and ensures the control capability of the gate electrode to the U-shaped monocrystalline silicon channel on the premise of not introducing the gate electrode into the groove formed by the U-shaped monocrystalline silicon, namely the control capability of the gate electrode to the channel is ensured while the integration level is improved. Therefore, the method is suitable for popularization and application.

Description

Square cylindrical gate embedded U-shaped channel field effect transistor and its manufacturing method

technical field

The invention belongs to the field of ultra-large-scale integrated circuit manufacturing, and in particular relates to a high-integration square cylindrical gate embedded U-shaped channel field effect transistor suitable for ultra-high-integration integrated circuit manufacturing and a manufacturing method thereof.

Background technique

With the continuous reduction in size of the basic unit MOSFETs of integrated circuits, the distance between the source electrode and the drain electrode is reduced to tens of nanometers. On the one hand, the shortening of the channel reduces the control ability of the gate electrode and causes the sub-threshold swing to increase. , the increase of leakage current, the increase of static power consumption and the decrease of the potential barrier caused by the drain electrode voltage lead to the drift of the threshold voltage and the significant decrease of the breakdown resistance. In order to improve the gate electrode control capability of nanoscale MOSFETs transistors, multi-gate technologies such as double gate and folded gate have been proposed. However, when the physical length of the device channel is further reduced to more than ten nanometers to several nanometers, due to the further shortening of the channel length, the control ability of the double gate and the folded gate will also be weakened. In order to solve this problem, the inventor proposed A U-shaped channel field effect transistor is proposed. On the premise of not increasing the distance between the source electrode and the drain electrode, by using a U-shaped vertical channel, the channel length can be effectively extended, and on the premise that the integration degree can be further improved , significantly reducing the short-channel effect. However, this kind of transistor needs to form a multi-layer structure such as insulating layer, gate electrode and insulating layer in the source and drain directions inside the U-shaped groove. On the one hand, complicated process steps are required to realize the inside of the groove. The complexity of the internal structure is also not conducive to the further improvement of the integration degree.

SUMMARY OF THE INVENTION

Purpose of invention:

In order to solve the problem that the integration degree is difficult to be further improved due to the complicated internal structure of the U-shaped channel field effect transistor groove previously proposed by the inventor and to simplify the production process steps, the present invention proposes that the U-shaped channel field is embedded in the square cylindrical gate with high integration degree. Effect transistor and method of making the same.

Technical solutions:

The present invention is achieved through the following technical solutions:

A square cylindrical gate embedded U-shaped channel field effect transistor, comprising a silicon substrate of an SOI wafer, an insulating layer of the SOI wafer above the silicon substrate of the SOI wafer; U-shaped above the insulating layer of the SOI wafer U-shaped monocrystalline silicon, a gate insulating layer and a square cylindrical gate electrode; U-shaped monocrystalline silicon has a U-shaped groove structure, and the interior of the groove and the front, rear, left, and right sides of the groove are filled and covered by a gate insulating layer, and the U-shaped The left and right sides of the U-shaped groove formed by monocrystalline silicon do not contain any other structural layers except the gate insulating layer. The gate insulating layer is located on the left and right sides of the U-shaped groove structure formed by U-shaped monocrystalline silicon. The area between the vertical parts; the two vertical parts on the left and right sides of the U-shaped groove structure formed by U-shaped monocrystalline silicon are isolated from each other by the gate insulating layer; The outer surface of the U-shaped single crystal silicon is wrapped around the entire outer surface except the upper and lower surfaces; the square cylindrical gate electrode is in contact with the front, rear, left, and right sides of the gate insulating layer, and the gate insulating layer is wrapped on all sides, and passes through the gate electrode. The insulating layer and the U-shaped monocrystalline silicon are insulated and isolated from each other, so that the U-shaped monocrystalline silicon is embedded in the inside of the cylindrical shape formed by the square cylindrical gate electrode, and the left and right sides of the U-shaped groove structure formed by the U-shaped monocrystalline silicon are embedded. The two vertical parts on the side and the lower horizontal part have the effect of field effect control; the source electrode and the drain electrode are composed of metal materials and are respectively located on the upper surface of the left and right vertical parts of the U-shaped groove structure formed by U-shaped single crystal silicon. above, and respectively form ohmic contact with the upper surfaces of the left and right vertical parts of the U-shaped groove structure formed by the U-shaped single crystal silicon, and the source electrode and the drain electrode are insulated and isolated from each other by an insulating medium layer.

The manufacturing method of the U-shaped channel field effect transistor embedded in the square cylindrical gate, the manufacturing steps are as follows:

Step 1: Provide an SOI wafer. Below the SOI wafer is the silicon substrate of the SOI wafer, above the silicon substrate of the SOI wafer is the insulating layer of the SOI wafer, and above the insulating layer of the SOI wafer is the silicon substrate for the SOI wafer. A single crystal silicon layer of U-shaped single crystal silicon is formed, part of the U-shaped single crystal silicon is removed by photolithography and etching, and U-shaped single crystal silicon is further formed on the SOI wafer;

Step 2: depositing an insulating medium on the SOI wafer and planarizing the surface to expose the U-shaped monocrystalline silicon, and initially forming a gate insulating layer;

Step 3: Etch the front, rear, left, right, and left surrounding parts of the U-shaped monocrystalline silicon above the insulating layer of the SOI wafer and the front and rear sides of the gate insulating layer formed in step 2 through photolithography and etching processes to expose the SOI wafer. the insulating layer;

Step 4: Deposit an insulating medium on the SOI wafer and planarize the surface to expose the upper surface of the U-shaped single crystal silicon, and then partially etch the insulating medium around the U-shaped single crystal silicon by photolithography and etching processes. Etch to expose the insulating layer of the SOI wafer, and further form a gate insulating layer;

Step 5: depositing metal or polysilicon on the SOI wafer and planarizing the surface to expose the upper surface of the U-shaped monocrystalline silicon to form a square cylindrical gate electrode;

Step 6: Deposit an insulating medium on the surface of the wafer, and remove the insulating medium above the vertical parts on both sides of the U-shaped groove formed by the U-shaped single crystal silicon through an etching process to form an insulating medium layer and source-drain through holes, and then remove the insulating medium. Metal or polysilicon is deposited on the upper surface of the wafer, the surface is planarized until the insulating dielectric layer is exposed, and source electrodes and drain electrodes are formed in the through holes.

Advantages and Effects:

The present invention has the following advantages and beneficial effects:

1. Achieve higher integration under the same lithography process level;

Compared with the prior art, since the interior of the groove formed by the U-shaped single crystal silicon of the present invention only needs to be filled with an insulating medium to realize the isolation of the two vertical parts on both sides from each other, there is no need to introduce metal for generating the gate electrode inside the groove. The material or polysilicon material avoids the formation of a multi-layer multi-material structure inside the groove formed by U-shaped monocrystalline silicon. Compared with the U-shaped channel transistor of the prior art, two layers of insulating medium and one layer of gate need to be formed inside the groove. This technical feature of the electrode, the square cylindrical gate of the present invention only needs to form a layer of insulating medium inside the groove of the U-shaped channel field effect transistor, so the structure is relatively simple, and the gap between the source electrode and the drain electrode can be realized. A highly integrated metal-oxide-semiconductor field-effect transistor with a pitch of only 1 nanometer. The cylindrical gate electrode is controlled by the outer surface of the U-shaped monocrystalline silicon. Therefore, the high-integration square cylindrical gate of the present invention is embedded with a U-shaped channel field effect transistor, and its structure determines its premise of the same lithography technology. A shorter distance between the source electrode and the drain electrode can be achieved under the same process level, thereby achieving the technical effect of achieving higher integration at the same process level.

2. Strong grid control capability;

The square cylindrical gate embedded U-shaped channel field effect transistor proposed by the present invention improves the integration degree, and at the same time, because the square cylindrical gate electrode surrounds the vertical channel part on both sides of the U-shaped monocrystalline silicon on three sides, and the horizontal The channel is surrounded on all sides, and the square cylindrical gate electrode ensures its control of the electric field, potential and carrier distribution inside the U-shaped single crystal silicon. Even if the depth of the groove is only a few nanometers and the distance between the source electrode and the drain electrode is only 1 nanometer, under the control of the square cylindrical gate electrode, the U-shaped channel field effect transistor embedded in the square cylindrical gate still remains. The control effect of the metal oxide semiconductor field effect transistor in an ideal state can be achieved. That is, the control ability of the gate electrode to the channel is ensured while improving the integration degree.

Description of drawings

1 is a top view of a U-shaped channel field effect transistor embedded in a square cylindrical gate of the present invention;

2 is a cross-sectional view along dotted line A of a top view of a square cylindrical gate embedded U-shaped channel field effect transistor of the present invention;

3 is a cross-sectional view along dotted line B of a top view of a square cylindrical gate embedded U-shaped channel field effect transistor of the present invention;

4 is a cross-sectional view along dotted line C of a top view of a square cylindrical gate embedded U-shaped channel field effect transistor of the present invention;

Fig. 5 is the top view of step one;

Fig. 6 is the sectional view along dotted line A of step 1;

Fig. 7 is the sectional view along dotted line B of step 1;

Fig. 8 is the top view of step 2;

9 is a cross-sectional view along dotted line A of step 2;

10 is a cross-sectional view along dotted line B of step 2;

Figure 11 is a top view of step three;

12 is a cross-sectional view along dotted line A of step 3;

13 is a cross-sectional view along dotted line B of step 3;

14 is a cross-sectional view along the dotted line C of step 3;

Fig. 15 is the top view of step 4;

Fig. 16 is the sectional view along the dotted line A of step 4;

17 is a cross-sectional view along the dotted line B of step 4;

18 is a cross-sectional view along the dotted line C of step 4;

Figure 19 is a top view of step five;

Figure 20 is a cross-sectional view along dotted line A in step 5;

21 is a cross-sectional view along the dashed line B of step 5;

22 is a cross-sectional view along the dotted line C of step 5;

Figure 23 is a top view of step six;

24 is a cross-sectional view along the dotted line A of step 6;

25 is a cross-sectional view along the dotted line B of step 6;

FIG. 26 is a cross-sectional view taken along the dotted line C in the sixth step.

Description of reference numbers:

1. Source electrode; 2. Drain electrode; 3. Insulating dielectric layer; 4. Square cylindrical gate electrode; 5. Insulating layer of SOI wafer; 6. Silicon substrate of SOI wafer; 7. U-shaped monocrystalline silicon 8. The gate insulating layer.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings:

As shown in FIG. 1, FIG. 2, FIG. 3 and FIG. 4, a square cylindrical gate embedded U-shaped channel field effect transistor includes a silicon substrate 6 of an SOI wafer, and is characterized in that: Above the substrate 6 is the insulating layer 5 of the SOI wafer; the insulating layer 5 of the SOI wafer has a U-shaped monocrystalline silicon 7, a gate insulating layer 8 and a square cylindrical gate electrode 4; the U-shaped monocrystalline silicon 7 has a U-shaped monocrystalline silicon Structural features of the U-shaped groove, the inside of the groove and the front and rear left and right side surfaces are filled and covered by the gate insulating layer 8, and the left and right sides of the U-shaped groove formed by the U-shaped monocrystalline silicon 7 are except the gate insulating layer 8. Without any other structural layers, the gate insulating layer 8 is located in the area between the two vertical parts on the left and right sides of the U-shaped groove structure formed by the U-shaped single crystal silicon 7; The two vertical parts on the left and right sides of the groove structure are isolated from each other by the gate insulating layer 8; Form a wrap around; the square cylindrical gate electrode 4 is in contact with each other on the front, back, left and right sides of the gate insulating layer 8, forming a four-sided wrap on the gate insulating layer 8, and through the gate insulating layer 8 and the U-shaped monocrystalline silicon 7 to each other Insulation isolation, so that the U-shaped single crystal silicon 7 is embedded in the cylindrical interior formed by the square cylindrical gate electrode 4, and the two vertical parts on the left and right sides of the U-shaped groove structure formed by the U-shaped single crystal silicon 7 are The source electrode 1 and the drain electrode 2 are composed of metal materials, and are respectively located above the upper surfaces of the vertical parts on the left and right sides of the U-shaped groove structure formed by the U-shaped single crystal silicon 7, and Ohmic contacts are formed with the upper surfaces of the left and right vertical parts of the U-shaped groove structure formed by the U-shaped single crystal silicon 7 respectively.

The present invention provides a high-integration square cylindrical gate embedded U-shaped channel field effect transistor. Taking the N-type as an example, when the device is working, the square cylindrical gate electrode 4 is the gate electrode that controls the device to be turned on or off. When the gate electrode 4 is at a low potential, the electrons in the areas on the left and right sides and below the square cylindrical gate electrode 4 of the U-shaped single crystal silicon 7 are evacuated under the electric field effect of the square cylindrical gate electrode 4, so that the U-shaped single crystal silicon 7 is evacuated under the electric field effect of the square cylindrical gate electrode 4. The U-shaped channel formed by the crystalline silicon 7 is in a pinch-off state, so the device is in an off state at this time. As the potential of the square cylindrical gate electrode 4 gradually increases, the U-shaped channel formed by the U-shaped single crystal silicon 7 The number of electrons in the channel also increases gradually. When the square cylindrical gate electrode 4 is at a high potential, under the action of the electric field, a large number of electrons are formed at the interface between the U-shaped single crystal silicon 7 and the gate insulating layer 8 to form electron accumulation. , so that the U-shaped channel formed by the U-shaped monocrystalline silicon 7 is in the open state, so the device is in the open state at this time, and the square cylindrical gate electrode 4 surrounds the vertical part of the U-shaped monocrystalline silicon 7 on three sides, and the horizontal channel Surrounding on all sides enhances the control ability of the gate to the monocrystalline silicon channel. Through the above-mentioned specific embodiments, a U-shaped channel field effect transistor with a square cylindrical gate embedded with a high degree of integration is realized.

In order to achieve the device function of the present invention, the square cylindrical gate proposed by the present invention is embedded with a U-shaped channel field effect transistor, and its core structural features are:

1. The gate insulating layer 8 is in the shape of a Chinese character "Sun" when viewed from above, and forms a wrap around the entire outer surface of the U-shaped single crystal silicon 7 except for the upper and lower surfaces, and the two vertical parts of the U-shaped single crystal silicon 7 pass through the gate The insulating layers 8 are insulated from each other;

2. A square cylindrical gate electrode 4 is attached to the surface of the gate insulating layer 8, and the square cylindrical gate electrode 4 forms a wrap around the outer surface of the gate insulating layer 8 except the upper surface, so that the U-shaped monocrystalline silicon 7 is embedded in the The cylindrical interior formed by the square cylindrical gate electrode 4;

3. The present invention uses U-shaped monocrystalline silicon 7 as the channel portion of the device, and the vertical channel portions on both sides are located below the source electrode 1 and the drain electrode 2 respectively. Compared with the ordinary planar structure, no additional chips are occupied. On the premise of reducing the area, the effective channel length of the device is increased, thus helping the device to overcome the influence of the short channel effect.

In the method for manufacturing a U-shaped channel field effect transistor with a square cylindrical gate embedded in the present invention, the manufacturing steps are as follows:

Step 1: As shown in FIG. 5 , FIG. 6 and FIG. 7 , provide an SOI wafer, below the SOI wafer is the silicon substrate 6 of the SOI wafer, and above the silicon substrate 6 of the SOI wafer is the SOI wafer. The insulating layer 5, above the insulating layer 5 of the SOI wafer is a single crystal silicon layer for forming U-shaped single crystal silicon 7, and part of the U-shaped single crystal silicon 7 is removed by photolithography and etching process, and the SOI wafer is placed on the SOI wafer. Further forming U-shaped single crystal silicon 7;

Step 2: As shown in FIG. 8 , FIG. 9 and FIG. 10 , an insulating medium is deposited over the SOI wafer and the surface is planarized to expose the U-shaped monocrystalline silicon 7 , and the gate insulating layer 8 is initially formed;

Step 3: As shown in FIG. 11 , FIG. 12 , FIG. 13 and FIG. 14 , the front, rear, left, right and surrounding parts of the U-shaped monocrystalline silicon 7 above the insulating layer 5 of the SOI wafer, and step 2 are removed by photolithography and etching processes. The front and rear sides of the formed gate insulating layer 8 are etched to expose the insulating layer 5 of the SOI wafer;

Step 4: As shown in Figure 15, Figure 16, Figure 17 and Figure 18, deposit an insulating medium on the SOI wafer and planarize the surface to expose the upper surface of the U-shaped monocrystalline silicon 7, and then pass photolithography, etching The process partially etches the insulating medium around the U-shaped monocrystalline silicon 7 to expose the insulating layer 5 of the SOI wafer, and further forms the gate insulating layer 8;

Step 5. As shown in Figure 19, Figure 20, Figure 21 and Figure 22, deposit metal or polysilicon on the SOI wafer and planarize the surface to expose the upper surface of the U-shaped monocrystalline silicon 7 to form a square cylindrical gate electrode 4;

Step 6: As shown in Figure 23, Figure 24, Figure 25 and Figure 26, deposit an insulating medium on the surface of the wafer, and remove the vertical parts on both sides of the U-shaped groove formed by the U-shaped single crystal silicon 7 through an etching process Above the insulating medium, an insulating medium layer 3 and source-drain through holes are formed, and then metal or polysilicon is deposited on the upper surface of the wafer, and the surface is planarized until the insulating medium layer 3 is exposed, and the source electrode 1 and the drain electrode 2 are formed in the through holes. .

Claims (2)

1. A square tubular gate embedded U-channel field effect transistor comprising a silicon substrate (6) of an SOI wafer, characterized in that: an insulating layer (5) of the SOI wafer is arranged above a silicon substrate (6) of the SOI wafer; u-shaped monocrystalline silicon (7), a gate insulating layer (8) and a square cylindrical gate electrode (4) are arranged above an insulating layer (5) of the SOI wafer; the U-shaped monocrystalline silicon (7) is characterized by having a U-shaped groove structure, the inner part, the front side, the rear side, the left side and the right side of the groove are filled and covered by gate insulation layers (8), the left side and the right side of the U-shaped groove formed by the U-shaped monocrystalline silicon (7) do not contain any other structural layer except the gate insulation layers (8), and the gate insulation layers (8) are positioned in the area between two vertical parts at the left side and the right side of the U-shaped groove structure formed by the U-shaped monocrystalline silicon (7); two vertical parts at the left side and the right side of a U-shaped groove structure formed by U-shaped monocrystalline silicon (7) are isolated from each other through a grid insulation layer (8); the grid insulation layer (8) presents a Chinese character 'ri' shape when viewed from top, the outer surface of the whole U-shaped monocrystalline silicon (7) except the upper surface and the lower surface is wrapped, and two vertical parts of the U-shaped monocrystalline silicon (7) are insulated and isolated from each other through the grid insulation layer (8); the square cylindrical gate electrode (4) is in mutual contact with the front side, the rear side, the left side and the right side of the gate insulating layer (8), the gate insulating layer (8) is wrapped in four sides, and the gate insulating layer (8) and the U-shaped monocrystalline silicon (7) are insulated and isolated from each other, so that the U-shaped monocrystalline silicon (7) is embedded in the cylindrical part formed by the square cylindrical gate electrode (4), and a field effect control effect is realized on two vertical parts and a lower horizontal part at the left side and the right side of a U-shaped groove structure formed by the U-shaped monocrystalline silicon (7); the source electrode (1) and the drain electrode (2) are made of metal materials, are respectively positioned above the upper surfaces of the vertical parts at the left side and the right side of the U-shaped groove structure formed by the U-shaped monocrystalline silicon (7), and respectively form ohmic contact with the upper surfaces of the vertical parts at the left side and the right side of the U-shaped groove structure formed by the U-shaped monocrystalline silicon (7), and the source electrode (1) and the drain electrode (2) are insulated and isolated from each other through an insulating medium layer (3);

the groove formed by the U-shaped monocrystalline silicon is only filled with an insulating medium to realize the isolation of the two vertical parts at two sides, and a metal material or a polycrystalline silicon material for generating a gate electrode is not required to be introduced into the groove;

because the vertical channel parts on the two sides of the U-shaped monocrystalline silicon of the square cylindrical gate electrode surround three sides and surround the horizontal channel on four sides, the square cylindrical gate electrode (4) ensures the control effect on the distribution of an electric field, electric potential and current carriers in the U-shaped monocrystalline silicon (7).

2. The method of claim 1, wherein the gate-embedded channel FET comprises: the manufacturing method of the transistor comprises the following steps:

the method comprises the following steps: providing an SOI wafer, wherein a silicon substrate (6) of the SOI wafer is arranged below the SOI wafer, an insulating layer (5) of the SOI wafer is arranged above the silicon substrate (6) of the SOI wafer, a monocrystalline silicon layer for forming U-shaped monocrystalline silicon (7) is arranged above the insulating layer (5) of the SOI wafer, and the U-shaped monocrystalline silicon (7) is further formed on the SOI wafer by removing part of the U-shaped monocrystalline silicon (7) through photoetching and etching processes;

step two: depositing an insulating medium above the SOI wafer and flattening the surface until the U-shaped monocrystalline silicon (7) is exposed, and preliminarily forming a gate insulating layer (8);

step three: etching the front, rear, left and right peripheral parts of the U-shaped monocrystalline silicon (7) above the insulating layer (5) of the SOI wafer and the front and rear sides of the gate insulating layer (8) formed in the step two to expose the insulating layer (5) of the SOI wafer through photoetching and etching processes;

step four: depositing an insulating medium above the SOI wafer and flattening the surface until the upper surface of the U-shaped monocrystalline silicon (7) is exposed, and then partially etching the insulating medium around the U-shaped monocrystalline silicon (7) by photoetching and etching processes until the insulating layer (5) of the SOI wafer is exposed, thereby further forming a gate insulating layer (8);

step five: depositing metal or polysilicon above the SOI wafer and flattening the surface until the upper surface of the U-shaped monocrystalline silicon (7) is exposed to form a square cylindrical gate electrode (4);

step six: depositing an insulating medium on the surface of the wafer, removing the insulating medium above the vertical parts at two sides of the U-shaped groove formed by the U-shaped monocrystalline silicon (7) through an etching process to form an insulating medium layer (3) and a source-drain through hole, depositing metal or polycrystalline silicon on the upper surface of the wafer, flattening the surface until the insulating medium layer (3) is exposed, and forming a source electrode (1) and a drain electrode (2) in the through hole.

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