CN104409487B - The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method - Google Patents

Abstract

The invention relates to a bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor. Compared with MOSFETs or tunneling field effect transistors of the same size, the breakdown protection region with low impurity concentration is introduced into the collector junction and the emitter junction to significantly improve the performance. Improve the forward and reverse withstand voltage capability of the device at the deep nanoscale; have an insulating tunneling structure on both sides of the base region, and under the control of the gate electrode, the insulating tunneling effect occurs on both sides of the base region at the same time. On the side, the generation rate of tunneling current is improved; excellent switching characteristics are achieved by utilizing the extremely sensitive relationship between the impedance of the tunneling insulating layer and its internal field strength; the tunneling signal is enhanced through the emitter to achieve excellent forward conduction characteristics; In addition, the present invention also proposes a specific manufacturing method suitable for manufacturing bidirectional breakdown protection double-gate insulation tunneling enhancement transistors on low-cost bulk silicon wafers. The transistor significantly improves the working characteristics of the nanoscale integrated circuit unit and is suitable for popularization and application.

Description

Bulk silicon bidirectional breakdown protection double gate insulated tunneling enhanced transistor and manufacturing method thereof

Technical field:

The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor and a manufacturing method thereof, which are suitable for manufacturing high-performance ultra-high integrated integrated circuits.

Background technique:

At present, with the continuous improvement of the integration level, the source electrode and the channel or between the drain electrode and the channel of the integrated circuit unit Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) devices form a steep mutation PN within a few nanometers. Junction, when the drain-source voltage is large, this steep abrupt PN junction will have a breakdown effect, which will cause the device to fail. As the size of the device continues to shrink, this breakdown effect becomes more and more obvious. In addition, the continuous shortening of the channel length leads to the increase of the sub-threshold swing of MOSFETs, which leads to the serious degradation of switching characteristics and the obvious increase of static power consumption. Although the degradation of device performance can be alleviated by improving the gate electrode structure, when the device size is further reduced to below 20 nanometers, even with the optimized gate electrode structure, the subthreshold swing of the device will also decrease. increases with further reduction in device channel length, resulting in further deterioration of device performance;

Tunneling Field Effect Transistors (TFETs), compared with MOSFETs, although its average subthreshold swing has been improved, but its forward conduction current is too small. The narrow material used to form the tunneling part of the tunneling field effect transistor can increase the tunneling probability to improve the transfer characteristics, but increases the difficulty of the process. In addition, the use of high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot substantially increase the tunneling probability of the silicon material, so There is a limited improvement in transfer characteristics for tunneling field effect transistors.

Invention content:

purpose of invention

In order to significantly improve the breakdown resistance of sub-20nm-scale devices while being compatible with existing bulk silicon-based process technologies; significantly improve the switching characteristics of basic unit devices for nanoscale integrated circuits; ensure that the devices have good forward Current conduction characteristics, the invention provides a bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhanced transistor and a manufacturing method thereof suitable for the manufacture of high-performance ultra-high integration integrated circuits.

Technical solutions

The present invention is achieved through the following technical solutions:

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhanced transistor, using a bulk silicon wafer including a single crystal silicon substrate 1 as the substrate for generating devices; emitter region 3, base region 4, collector region 5 and breakdown protection The region 2 is located above the single crystal silicon substrate 1; the base region 4 is located between the emitter region 3 and the collector region 5, the breakdown protection region 2 is located on both sides of the base region 4; the emitter 9 is located above the emitter region 3; The collector electrode 10 is located above the collector region 5; the conductive layer 6, the tunneling insulating layer 7 and the gate electrode 8 sequentially form a sandwich structure on both sides of the base region 4; , the base region 4 and the upper surface of the single crystal silicon substrate 1 other than those below the breakdown protection region 2 are in contact with each other.

In order to achieve the device functions described in the present invention, the present invention proposes bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, and its core structural features are:

The impurity concentration in the breakdown protection region 2 is lower than 10 ¹⁶ per cubic centimeter.

The impurity concentration of the base region 4 is not lower than 10 ¹⁷ per cubic centimeter, and both sides of the base region 4 are in contact with the conductive layer 6 to form ohmic contacts.

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 5 and the collector electrode 10. ohmic contact.

The conductive layer 6 is formed on both sides of the base region 4, and the conductive layer 6 is a metal material or a semiconductor material having the same impurity type as the base region 4 and a doping concentration greater than 10 ¹⁹ per cubic centimeter.

The tunneling insulating layer 7 is an insulating material layer for generating tunneling current, and has two independent parts, each part is formed on the other side of the conductive layer 6 on both sides of the base region 4 , which is in contact with the base region 4 .

The gate electrode 8 is an electrode that controls the tunneling effect of the tunneling insulating layer 7, and is an electrode that controls the on and off of the device, and is connected to the other side of the two independent parts of the tunneling insulating layer 7 that is in contact with the conductive layer 6. side contact.

The conductive layer 6, the tunneling insulating layer 7 and the gate electrode 8 are all isolated from the emitter region 3, the emitter electrode 9, the collector region 5 and the collector electrode 10 through the blocking insulating layer 11; The silicon substrates 1 are isolated from each other.

The conductive layer 6, the tunneling insulating layer 7 and the gate electrode 8 jointly constitute the tunneling base of the bulk silicon bidirectional breakdown protection double-gate insulating tunneling enhancement transistor. When the tunneling insulating layer 7 under the control of the gate electrode 8 tunnels When tunneling, current flows from the gate electrode 8 to the conductive layer 6 through the tunneling insulating layer 7 and supplies power to the base region 4 .

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, taking N-type as an example, the emitter region 3, base region 4 and collector region 5 are N region, P region and N region respectively, and its specific working principle is as follows: When the collector electrode 10 is positively biased and the gate electrode 8 is at a low potential, there is no sufficient potential difference formed between the gate electrode 8 and the conductive layer 6. At this time, the tunneling insulating layer 7 is in a high-resistance state, and no obvious tunneling current passes through. Therefore make it impossible to form a large enough base current between the base region 4 and the emitter region 3 to drive the bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, that is, the device is in an off state; as the gate electrode 8 voltage gradually increases As the temperature rises, the potential difference between the gate electrode 8 and the conductive layer 6 gradually increases, so that the electric field intensity in the tunneling insulating layer 7 between the gate electrode 8 and the conductive layer 6 also gradually increases. When the tunneling insulating layer When the electric field strength in 7 is below the critical value, the tunneling insulating layer 7 still maintains a good high-resistance state, and the potential difference between the gate electrode and the emitter is almost completely dropped between the inner wall and the outer wall of the tunneling insulating layer 7. , which makes the potential difference between the base region and the emitter region extremely small, so there is almost no current flowing in the base region, and the device remains in a good off state, and when the electric field strength in the tunneling insulating layer 7 is above the critical value , the tunneling insulating layer 7 will generate a significant tunneling current due to the tunneling effect, and the tunneling current will rise steeply at a very fast speed as the potential of the gate electrode 8 increases, which makes the tunneling insulating layer 7 is rapidly converted from a high-resistance state to a low-resistance state during the extremely short potential change interval of the gate electrode. When the tunneling insulating layer 7 is in a low-resistance state, the tunneling insulating layer 7 is between the gate electrode 8 and the conductive layer 6 The formed resistance is much smaller than the resistance formed between the conductive layer 6 and the emitter 3, which makes a sufficiently large forward bias voltage formed between the base region 4 and the emitter region 3, and under the action of the tunneling effect , a large amount of current movement is generated between the inner wall and the outer wall of the tunneling insulating layer 7, and the conductive layer 6, the tunneling insulating layer 7 and the gate electrode 8 together constitute the tunneling of the bulk silicon bidirectional breakdown protection double-gate insulating tunneling enhanced transistor Base, when the tunneling insulating layer 7 tunnels under the control of the gate electrode 8, the current flows from the gate electrode 8 to the conductive layer 6 through the tunneling insulating layer 7, and supplies power to the base region 4; the current in the base region 4 passes through After the emitter region 3 is enhanced, it flows out from the collector, and the device is in the open state at this time.

The specific process steps of a method for manufacturing a bulk silicon bidirectional breakdown-protected double-gate insulated tunneling enhanced transistor are as follows:

Step 1: Provide a bulk silicon wafer with a doping concentration not higher than 10 ¹⁶ per cubic centimeter, and perform doping on the monocrystalline silicon thin film above the bulk silicon wafer through ion implantation or diffusion process to initially form the base region 4 .

Step 2: Doping the upper part of the bulk silicon wafer by ion implantation or diffusion process again, and forming impurity of the opposite type to the impurity in step 1 on both sides of the base region 4 formed in step 1, with a concentration not lower than 10 ¹⁹ The heavily doped region per cubic centimeter is used to further form the emitter region 3 and the collector region 5, leaving an undoped region between the heavily doped region and the base region, the undoped region The impurity area is used to form the breakdown protection area 2.

Step 3. Form a rectangular parallelepiped single crystal silicon island queue on the provided bulk silicon wafer through photolithography, etching and other processes, so that each unit is sequentially arranged with an emission area 3, a breakdown protection area 2, and a base area 4 , Breakdown protection zone 2 and collector zone 5.

Step 4: After depositing an insulating medium on the wafer, planarize the surface to expose the emitter region 3 , the base region 4 , the collector region 5 and the breakdown protection region 2 , and initially form a blocking insulating layer 11 .

Step 5. Further form a cuboid single crystal silicon island array on the provided bulk silicon wafer through photolithography, etching and other processes, so that each single crystal silicon island queue formed in step 3 is divided into multiple independent unit.

Step 6. Deposit an insulating medium on the wafer, so that the part etched in step 5 is fully filled, and planarize the surface to expose the emitter region 3, the base region 4, the collector region 5 and the breakdown protection region 2 , and further form a blocking insulating layer 11 .

Step 7: Etching the insulating barrier layer 11 on both sides of the base region 4 of each unit on the wafer surface to expose the single crystal silicon substrate 1 through an etching process.

Step 8. Deposit metal or heavily doped polysilicon with the same impurity type as the base region 4 on the wafer, so that the blocking insulating layer 11 etched in step 7 is completely filled, and then planarize the surface to expose The conductive layer 6 is formed by the emitter region 3 , the base region 4 , the collector region 5 , the breakdown protection region 2 and the blocking insulating layer 11 .

Step 9: Etching the blocking insulating layer 11 on the sides of the conductive layer 6 on both sides of the base region away from the base region.

Step 10. Deposit a tunneling insulating layer dielectric on the wafer, so that the blocking insulating layer 11 etched away in step 9 is completely filled with the tunneling insulating layer dielectric, and then planarize the surface to expose the emitter region 3 and the base region 4. Collector region 5 , conductive layer 6 , breakdown protection region 2 and blocking insulating layer 11 to form tunneling insulating layer 7 .

Step 11: Etching the blocking insulating layer 11 on the sides of the tunneling insulating layer 7 on both sides of the base area away from the base area.

Step 12, depositing metal or heavily doped polysilicon on the wafer, so that the blocking insulating layer 11 etched in step 11 is completely filled.

Step 13: Planarize the surface to expose the emitter region 3 , base region 4 , collector region 5 , conductive layer 6 , tunneling insulating layer 7 , breakdown protection region 2 and blocking insulating layer 11 , and initially form the gate electrode 8 .

Step fourteen, depositing an insulating medium on the wafer to further form a blocking insulating layer 11 .

Step fifteen: Etch away the blocking insulating layer 11 above the gate electrode 8 formed in step thirteen through an etching process.

Step sixteen, depositing metal or heavily doped polysilicon on the wafer, so that the blocking insulating layer 11 etched away in step fifteen is completely filled, the surface is planarized, and the gate electrode 8 is further formed.

Step 17: Etch away the part other than the part used to form the wiring between the device units by an etching process, and further form the gate electrode 8 .

Step eighteen, depositing an insulating medium on the wafer, planarizing the surface, and further forming a blocking insulating layer 11 .

Step 19: Etching away the blocking insulating layer 11 above the emitter region 3 and the collector region 5 through an etching process to form through holes for the emitter 9 and the collector 10 .

Step 20, depositing metal on the wafer, so that the through holes of the emitter 9 and the collector 10 formed in step 18 are completely filled, and forming the emitter 9 and the collector 10 through an etching process.

Advantages and effects

The present invention has following advantage and beneficial effect:

1. Low cost

The specific manufacturing method of bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhanced transistor is applicable to ordinary bulk silicon wafers, which can significantly reduce the cost compared with transistors with the same function manufactured under expensive SOI wafers.

2. Two-way breakdown protection function

The bulk silicon bidirectional breakdown protects the double-gate insulation tunneling enhancement transistor, and uses the breakdown protection region 12 to improve the forward and reverse withstand voltage characteristics of the device. Taking an N-type device as an example, when the collector 10 is forward-biased relative to the emitter 9, the collector junction composed of the conductive layer 6, the base region 4, the breakdown protection region 12 and the collector region 5 is in a reverse-biased state. The breakdown protection zone 12 located between the base region 4 and the collector region 5 has an anti-breakdown protection effect on the reverse-biased collector junction, so it can significantly improve the forward withstand voltage capability of the device; when the collector electrode 10 is relative to the emitter electrode 9 When reverse biased, the emitter junction composed of the conductive layer 6, the base region 4, the breakdown protection region 12 and the emission region 3 is in the reverse bias state, and the breakdown protection region 12 located between the base region 4 and the emission region 3 is for The reverse-biased emitter junction has the function of anti-breakdown protection, so it can significantly improve the reverse withstand voltage capability of the device;

3. High tunneling current generation rate

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor has insulation tunneling structures on both sides of the base region 4, and under the control of the gate electrode 8, the insulation tunneling effect occurs on both sides of the base region at the same time, thus improving The generation rate of tunneling current.

4. Excellent switching characteristics

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor and its manufacturing method utilizes the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, and selects an appropriate value for the tunneling insulating layer 7 tunnel insulating material, and properly adjust the height and thickness of the tunnel insulating layer 7, the tunnel insulating layer 7 can realize the transition between the high-resistance state and the low-resistance state within a very small gate electrode potential variation range, More excellent switching characteristics can be realized.

5. High forward current

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, the gate insulation tunneling current flows to the base region through the conductive layer 6, and passes through the emission region for signal enhancement, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands as a device Compared with the conduction current of TFETs, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary TFETs devices, bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistors can achieve higher forward conduction current .

Description of drawings

FIG. 1 is a schematic top view of a two-dimensional structure of a bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhancement transistor of the present invention;

Fig. 2 is a schematic cross-sectional view obtained by cutting along the tangent line A in Fig. 1,

Fig. 3 is a schematic cross-sectional view obtained by cutting along the tangent line B in Fig. 1,

Figure 4 is a schematic top view of Step 1,

Fig. 5 is a schematic cross-sectional view obtained by cutting along the tangent line A in Fig. 4,

Figure 6 is a schematic top view of step 2,

Fig. 7 is a schematic cross-sectional view of step 2 obtained by cutting along tangent line A in Fig. 6,

Figure 8 is a schematic top view of step 3,

Fig. 9 is a schematic cross-sectional view of step 3 obtained by cutting along tangent line A in Fig. 8,

Figure 10 is a schematic top view of Step 4,

Fig. 11 is a schematic cross-sectional view of step 4 obtained by cutting along tangent line A in Fig. 10,

Figure 12 is a schematic top view of step five,

Fig. 13 is a schematic cross-sectional view of step 5 obtained by cutting along the tangent line B in Fig. 12,

Figure 14 is a schematic top view of step six,

Fig. 15 is a schematic cross-sectional view of step 6 obtained by cutting along the tangent line B in Fig. 14,

Figure 16 is a schematic top view of step seven,

Fig. 17 is a schematic cross-sectional view of step 7 obtained by cutting along the tangent line B in Fig. 16,

Figure 18 is a schematic top view of Step 8,

Fig. 19 is a schematic cross-sectional view of step 8 obtained by cutting along tangent line B in Fig. 18,

Figure 20 is a schematic top view of step nine,

Fig. 21 is a schematic cross-sectional view of step nine obtained by cutting along the tangent line B in Fig. 20,

Figure 22 is a schematic top view of step ten,

Fig. 23 is a schematic cross-sectional view of step ten obtained by cutting along the tangent line B in Fig. 22,

Fig. 24 is a schematic top view of step eleven,

Fig. 25 is a schematic cross-sectional view of step eleven obtained by cutting along the tangent line B in Fig. 24,

Fig. 26 is a schematic top view of step 12,

Fig. 27 is a schematic cross-sectional view of step 12 obtained by cutting along tangent line A in Fig. 26,

Fig. 28 is a schematic cross-sectional view of step 12 obtained by cutting along the tangent line B in Fig. 26,

Fig. 29 is a schematic top view of step 13,

Fig. 30 is a schematic cross-sectional view of step 13 obtained by cutting along the tangent line B in Fig. 29,

Fig. 31 is a schematic top view of step fourteen,

Fig. 32 is a schematic cross-sectional view of step 14 obtained by cutting along tangent line A in Fig. 31,

Fig. 33 is a schematic cross-sectional view of step 14 obtained by cutting along the tangent line B in Fig. 31,

Figure 34 is a schematic top view of step fifteen,

Fig. 35 is a schematic cross-sectional view of step 15 obtained by cutting along tangent line B in Fig. 34,

Fig. 36 is a schematic top view of step sixteen,

Fig. 37 is a schematic cross-sectional view of step 16 obtained by cutting along tangent line A in Fig. 36,

Fig. 38 is a schematic cross-sectional view of step 16 obtained by cutting along the tangent line B in Fig. 36,

Fig. 39 is a schematic top view of step seventeen,

Fig. 40 is a schematic cross-sectional view of step 17 obtained by cutting along tangent line A in Fig. 39,

Fig. 41 is a schematic top view of step eighteen,

Fig. 42 is a schematic cross-sectional view of step 18 obtained by cutting along tangent line A in Fig. 41,

Fig. 43 is a schematic cross-sectional view of step 18 obtained by cutting along tangent line B in Fig. 41,

Figure 44 is a schematic top view of step nineteen,

FIG. 45 is a schematic cross-sectional view of step nineteen obtained by cutting along tangent line A in FIG. 44 .

Explanation of reference signs:

1. Single crystal silicon substrate; 2. Breakdown protection area; 3. Emitter area; 4. Base area; 5. Collector area; 6. Conductive layer; 7. Tunneling insulating layer; 8. Gate electrode; 9. Emitter; 10, collector; 11, blocking insulating layer.

detailed description

Below in conjunction with accompanying drawing, the present invention will be further described:

Figure 1 is a schematic top view of the two-dimensional structure of the bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor of the present invention; Figure 2 is a schematic cross-sectional view obtained by cutting along the tangent line A in Figure 1; Figure 3 is obtained by cutting along the tangent line B in Figure 1 A schematic cross-sectional view; specifically including a single crystal silicon substrate 1; breakdown protection region 2; emitter region 3; base region 4; collector region 5; conductive layer 6; tunnel insulating layer 7; gate electrode 8; emitter 9; Collector 10 ; blocking insulating layer 11 .

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhanced transistor, using a bulk silicon wafer including a single crystal silicon substrate 1 as the substrate for generating devices; emitter region 3, base region 4, collector region 5 and breakdown protection The region 2 is located above the single crystal silicon substrate 1; the base region 4 is located between the emitter region 3 and the collector region 5; the emitter 9 is located above the emitter region 3; the collector electrode 10 is located above the collector region 5; the conductive layer 6. The tunnel insulating layer 7 and the gate electrode 8 form a sandwich structure on both sides of the base region 4 in sequence; The upper surface portions of single crystal silicon substrates 1 are in contact with each other.

In order to achieve the device functions described in the present invention, the present invention proposes bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, and its core structural features are:

The impurity concentration in the breakdown protection region 2 is lower than 10 ¹⁶ per cubic centimeter.

The impurity concentration of the base region 4 is not lower than 10 ¹⁷ per cubic centimeter, and both sides are in contact with the conductive layer 6 to form ohmic contacts.

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 3 and the collector electrode 10. ohmic contact.

The conductive layer 6 is formed on both sides of the base region 4 and is made of a metal material or a semiconductor material having the same impurity type as the base region 4 and having a doping concentration greater than 10 ¹⁹ per cubic centimeter.

The tunneling insulating layer 7 is an insulating material layer for generating tunneling current, and has two independent parts, each part is formed on the other side of the conductive layer 6 on both sides of the base region 4 , which is in contact with the base region 4 .

The gate electrode 8 is an electrode that controls the tunneling effect of the tunneling insulating layer 7, and is an electrode that controls the on and off of the device, and is connected to the other side of the two independent parts of the tunneling insulating layer 7 that is in contact with the conductive layer 6. side contact.

The conductive layer 6, the tunneling insulating layer 7 and the gate electrode 8 are all isolated from the emitter region 3, the emitter electrode 9, the collector region 5 and the collector electrode 10 through the blocking insulating layer 11; The silicon substrates 1 are isolated from each other.

The conductive layer 6, the tunneling insulating layer 7 and the gate electrode 8 jointly constitute the tunneling base of the bulk silicon bidirectional breakdown protection double-gate insulating tunneling enhancement transistor. When the tunneling insulating layer 7 under the control of the gate electrode 8 tunnels When tunneling, current flows from the gate electrode 8 to the conductive layer 6 through the tunneling insulating layer 7 and supplies power to the base region 4 .

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, taking N-type as an example, the emitter region 3, base region 4 and collector region 5 are N region, P region and N region respectively, and its specific working principle is as follows: When the collector electrode 10 is positively biased and the gate electrode 8 is at a low potential, there is no sufficient potential difference formed between the gate electrode 8 and the conductive layer 6. At this time, the tunneling insulating layer 7 is in a high-resistance state, and no obvious tunneling current passes through. Therefore make it impossible to form a large enough base current between the base region 4 and the emitter region 3 to drive the bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, that is, the device is in an off state; as the gate electrode 8 voltage gradually increases As the temperature rises, the potential difference between the gate electrode 8 and the conductive layer 6 gradually increases, so that the electric field intensity in the tunneling insulating layer 7 between the gate electrode 8 and the conductive layer 6 also gradually increases. When the tunneling insulating layer When the electric field strength in 7 is below the critical value, the tunneling insulating layer 7 still maintains a good high-resistance state, and the potential difference between the gate electrode and the emitter is almost completely dropped between the inner wall and the outer wall of the tunneling insulating layer 7. , which makes the potential difference between the base region and the emitter region extremely small, so there is almost no current flowing in the base region, and the device remains in a good off state, and when the electric field strength in the tunneling insulating layer 7 is above the critical value , the tunneling insulating layer 7 will generate a significant tunneling current due to the tunneling effect, and the tunneling current will rise steeply at a very fast speed as the potential of the gate electrode 8 increases, which makes the tunneling insulating layer 7 is rapidly converted from a high-resistance state to a low-resistance state during the extremely short potential change interval of the gate electrode. When the tunneling insulating layer 7 is in a low-resistance state, the tunneling insulating layer 7 is between the gate electrode 8 and the conductive layer 6 The formed resistance is much smaller than the resistance formed between the conductive layer 6 and the emitter 3, which makes a sufficiently large forward bias voltage formed between the base region 4 and the emitter region 3, and under the action of the tunneling effect , a large amount of current movement is generated between the inner wall and the outer wall of the tunneling insulating layer 7, and the conductive layer 6, the tunneling insulating layer 7 and the gate electrode 8 together constitute the tunneling of the bulk silicon bidirectional breakdown protection double-gate insulating tunneling enhanced transistor Base, when the tunneling insulating layer 7 tunnels under the control of the gate electrode 8, the current flows from the gate electrode 8 to the conductive layer 6 through the tunneling insulating layer 7, and supplies power to the base region 4; the current in the base region 4 passes through After the emitter region 3 is enhanced, it flows out from the collector, and the device is in the open state at this time.

The specific manufacturing method of bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhanced transistor is applicable to ordinary bulk silicon wafers, which can significantly reduce the cost compared with transistors with the same function manufactured under expensive SOI wafers.

The bulk silicon bidirectional breakdown protects the double-gate insulation tunneling enhancement transistor, and uses the breakdown protection region 12 to improve the forward and reverse withstand voltage characteristics of the device. Taking an N-type device as an example, when the collector 10 is forward-biased relative to the emitter 9, the collector junction composed of the conductive layer 6, the base region 4, the breakdown protection region 12 and the collector region 5 is in a reverse-biased state. The breakdown protection zone 12 located between the base region 4 and the collector region 5 has an anti-breakdown protection effect on the reverse-biased collector junction, so it can significantly improve the forward withstand voltage capability of the device; when the collector electrode 10 is relative to the emitter electrode 9 When reverse biased, the emitter junction composed of the conductive layer 6, the base region 4, the breakdown protection region 12 and the emission region 3 is in the reverse bias state, and the breakdown protection region 12 located between the base region 4 and the emission region 3 is for The reverse-biased emitter junction has the function of anti-breakdown protection, so the reverse withstand voltage capability of the device can be significantly improved.

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor has insulation tunneling structures on both sides of the base region 4, and under the control of the gate electrode 8, the insulation tunneling effect occurs on both sides of the base region at the same time, thus improving The generation rate of tunneling current.

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor and its manufacturing method utilizes the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, and selects an appropriate value for the tunneling insulating layer 7 tunnel insulating material, and properly adjust the height and thickness of the tunnel insulating layer 7, the tunnel insulating layer 7 can realize the transition between the high-resistance state and the low-resistance state within a very small gate electrode potential variation range, More excellent switching characteristics can be realized.

Bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor, the gate insulation tunneling current flows to the base region through the conductive layer 6, and passes through the emission region for signal enhancement, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands as a device Compared with the conduction current of TFETs, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary TFETs devices, bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistors can achieve higher forward conduction current .

The specific manufacturing process steps of the unit and array of the bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor on the bulk silicon wafer proposed by the present invention are as follows:

Step 1, as shown in Figures 4 to 5, provide a bulk silicon wafer with a doping concentration not higher than 1016 per cubic centimeter, and perform doping on the single crystal silicon thin film above the bulk silicon wafer by ion implantation or diffusion process Miscellaneous, initially forming the base region 4.

Step 2, as shown in Fig. 6 to Fig. 7, doping the upper part of the bulk silicon wafer by ion implantation or diffusion process again, and forming impurities of the same type as in step 1 on both sides of the base region 4 formed in step 1. On the contrary, the heavily doped region with a concentration not lower than 1019 per cubic centimeter is used to further form the emitter region 3 and the collector region 5, leaving an undoped region between the heavily doped region and the base region. The undoped region is used to form the breakdown protection region 2 .

Step 3, as shown in Fig. 8 to Fig. 9, a cuboid-shaped single crystal silicon island formation is formed on the provided bulk silicon wafer through photolithography, etching and other processes, so that each unit is sequentially arranged with emission regions 3, Breakdown protection area 2, base area 4, breakdown protection area 2 and collector area 5.

Step 4, as shown in Figures 10 to 11, after depositing an insulating medium on the wafer, planarize the surface to expose the emitter region 3, the base region 4, the collector region 5 and the breakdown protection region 2, and initially form a blocking insulating layer 11.

Step five, as shown in Figure 12 to Figure 13, further form a rectangular parallelepiped single crystal silicon island array on the provided bulk silicon wafer through photolithography, etching and other processes, so that each single crystal silicon formed in step three Island queues are divided into multiple independent units.

Step 6, as shown in Figure 14 to Figure 15, deposit an insulating medium on the wafer, so that the part etched in step 5 is fully filled, and planarize the surface to expose the emitter region 3, the base region 4, the collector The electrical region 5 and the breakdown protection region 2 further form a blocking insulating layer 11 .

Step 7. As shown in FIG. 16 to FIG. 17 , the blocking insulating layer 11 on both sides of the base region 4 of each unit on the wafer surface is etched to expose the single crystal silicon substrate 1 through an etching process.

Step 8, as shown in FIGS. 18 to 19 , deposit metal or heavily doped polysilicon with the same impurity type as the base region 4 on the wafer, so that the blocking insulating layer 11 etched in step 7 is completely covered. filling, and then planarizing the surface to expose the emitter region 3 , the base region 4 , the collector region 5 , the breakdown protection region 2 and the blocking insulating layer 11 to form the conductive layer 6 .

Step 9, as shown in FIG. 20 to FIG. 21 , etch the blocking insulating layer 11 on the sides of the conductive layer 6 on both sides of the base region away from the base region.

Step 10. As shown in FIG. 22 to FIG. 23 , deposit a tunneling insulating layer dielectric on the wafer, so that the blocking insulating layer 11 etched in step 9 is completely filled with the tunneling insulating layer dielectric, and then the surface is flattened Thinning to expose the emitter region 3 , the base region 4 , the collector region 5 , the conductive layer 6 , the breakdown protection region 2 and the blocking insulating layer 11 to form the tunneling insulating layer 7 .

Step eleven, as shown in FIG. 24 to FIG. 25 , etch the blocking insulating layer 11 on the sides of the tunneling insulating layer 7 on both sides of the base region away from the base region.

Step 12, as shown in FIG. 26 to FIG. 28 , deposit metal or heavily doped polysilicon on the wafer, so that the blocking insulating layer 11 etched in step 11 is completely filled.

Step 13, as shown in Figures 29 to 30, planarize the surface to expose the emitter region 3, the base region 4, the collector region 5, the conductive layer 6, the tunnel insulating layer 7, the breakdown protection region 2 and the blocking insulating layer 11. Preliminarily forming the gate electrode 8 .

Step fourteen, as shown in FIG. 31 to FIG. 33 , deposit an insulating medium on the wafer to further form a blocking insulating layer 11 .

Step fifteen, as shown in FIG. 34 to FIG. 35 , the blocking insulating layer 11 above the gate electrode 8 formed in step 13 is etched away by an etching process.

Step sixteen, as shown in Figure 36 to Figure 38, deposit metal or heavily doped polysilicon on the wafer, so that the blocking insulating layer 11 etched in step fifteen is completely filled, and the surface is planarized, A gate electrode 8 is further formed.

Step seventeen, as shown in FIG. 39 to FIG. 40 , etch away the part other than the part used to form the wiring between the device units through an etching process, and further form the gate electrode 8 .

Step eighteen, as shown in FIG. 41 to FIG. 43 , deposit an insulating medium on the wafer, planarize the surface, and further form a blocking insulating layer 11 .

Step nineteen, as shown in FIGS. 44 to 45 , the blocking insulating layer 11 above the emitter region 3 and the collector region 5 is etched away by an etching process to form through holes for the emitter 9 and the collector 10 .

Step 20, as shown in Figures 1 to 3, deposit metal on the wafer, so that the through holes of the emitter 9 and collector 10 formed in step 18 are completely filled, and form the emitter through an etching process pole 9 and collector 10.

Claims (8)

1. Bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhanced transistor, characterized in that: a bulk silicon wafer containing a single crystal silicon substrate (1) is used as the substrate for generating the device; the emitter region (3), the base region (4), the collector region (5) and the breakdown protection region (2) are located above the monocrystalline silicon substrate (1); the base region (4) is located between the emitter region (3) and the collector region (5) , the breakdown protection area (2) is located on both sides of the base area (4); the emitter (9) is located above the emitter area (3); the collector (10) is located above the collector area (5); the conductive layer ( 6), the tunnel insulating layer (7) and the gate electrode (8) form a sandwich structure on both sides of the base region (4) in turn; the blocking insulating layer (11) is located in the emitter region (3), the collector region (5) . The base region (4) and the upper surface of the monocrystalline silicon substrate (1) other than the breakdown protection region (2) are in contact with each other; the impurity concentration in the breakdown protection region (2) is lower than 10 ¹⁶ per cubic centimeter; The impurity concentration of the base region (4) is not lower than 10 ¹⁷ per cubic centimeter; both sides of the base region (4) are in contact with the conductive layer (6) and form ohmic contacts. 2. The bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhanced transistor according to claim 1, characterized in that: between the emitter region (3) and the base region (4), between the collector region (5) and the base region (4) have opposite impurity types between them, and an ohmic contact is formed between the emitter region (3) and the emitter electrode (9), and an ohmic contact is formed between the collector region (5) and the collector electrode (10). 3. The bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhanced transistor according to claim 1, characterized in that: the conductive layer (6) is formed on both sides of the base region (4), and the conductive layer (6) is metal The material is or a semiconductor material having the same impurity type as the base region (4) and having a doping concentration greater than 10 ¹⁹ per cubic centimeter. 4. The bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhancement transistor according to claim 1, characterized in that: the tunneling insulating layer (7) is an insulating material layer for generating tunneling current, and has two independent Each part is formed on the other side of the conductive layer (6) on both sides of the base region (4) which is in contact with the base region (4). 5. The bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhancement transistor according to claim 1, characterized in that: the gate electrode (8) is an electrode that controls the tunneling effect of the tunneling insulating layer (7), and controls Device turn-on and turn-off electrodes are in contact with two separate parts of the tunneling insulating layer (7) on the one side that is in contact with the conductive layer (6) and on the other side. 6. The bulk silicon bidirectional breakdown protection double-gate insulation tunneling enhancement transistor according to claim 1, characterized in that: the conductive layer (6), the tunneling insulating layer (7) and the gate electrode (8) are all insulated by barrier The layer (11) is isolated from the emitter region (3), the emitter (9), the collector region (5) and the collector electrode (10); the gate electrode (8) is connected to the single crystal silicon substrate through the blocking insulating layer (11) (1) Mutual isolation. 7. The bulk silicon bidirectional breakdown protection double-gate insulating tunneling enhancement transistor according to claim 1, characterized in that: the conductive layer (6), the tunneling insulating layer (7) and the gate electrode (8) together form a bulk Silicon bidirectional breakdown protects the tunneling base of the double-gate insulating tunneling enhancement transistor. When the tunneling insulating layer (7) tunnels under the control of the gate electrode (8), the current passes through the tunnel from the gate electrode (8) The insulating layer (7) flows to the conductive layer (6) and supplies power to the base region (4). 8. A method for manufacturing a bulk silicon bidirectional breakdown protection double-gate insulated tunneling enhanced transistor as claimed in claim 1, characterized in that: the method steps are as follows: Step 1: Provide a bulk silicon wafer with a doping concentration not higher than 10 ¹⁶ per cubic centimeter, and dope the single crystal silicon thin film above the bulk silicon wafer through ion implantation or diffusion process, and initially form a base region (4 ); Step 2: Doping the upper part of the bulk silicon wafer by ion implantation or diffusion process again, and forming impurity of the opposite type to the impurity in step 1 on both sides of the base region (4) formed in step 1, with a concentration not lower than 10 ¹⁹ heavily doped regions per cubic centimeter, the heavily doped region is used to further form the emitter region (3) and the collector region (5), leaving undoped region, the undoped region is used to form a breakdown protection region (2); Step 3: Form a cuboid-shaped monocrystalline silicon island queue on the provided bulk silicon wafer through photolithography and etching processes, so that each unit is sequentially arranged with an emission area (3), a breakdown protection area (2), Base area (4), breakdown protection area (2) and collector area (5); Step 4. After depositing an insulating medium on the wafer, planarize the surface to expose the emitter region (3), base region (4), collector region (5) and breakdown protection region (2), and initially form a blocking insulating layer ( 11); Step 5. Further form a cuboid-shaped single crystal silicon island array on the provided bulk silicon wafer through photolithography and etching processes, so that each single crystal silicon island formation formed in step 3 is divided into multiple independent units ; Step 6. Deposit an insulating medium on the wafer, so that the part etched in step 5 is fully filled, and planarize the surface to expose the emitter region (3), base region (4), and collector region (5) and the breakdown protection area (2), further forming a blocking insulating layer (11); Step 7. Etching the blocking insulating layer (11) on both sides of the base region (4) of each unit on the wafer surface to expose the single crystal silicon substrate (1) through an etching process; Step 8. Deposit metal or heavily doped polysilicon with the same impurity type as the base region (4) on the wafer, so that the blocking insulating layer (11) etched in step 7 is completely filled, and then the surface planarizing to expose the emitter region (3), base region (4), collector region (5), breakdown protection region (2) and blocking insulating layer (11), forming a conductive layer (6); Step 9: Etching the blocking insulating layer (11) on the side of the conductive layer (6) on both sides of the base region away from the base region; Step 10. Deposit a tunneling insulating layer dielectric on the wafer, so that the blocking insulating layer (11) etched away in step 9 is completely filled with the tunneling insulating layer dielectric, and then planarize the surface to expose the emitter region (3 ), a base region (4), a collector region (5), a conductive layer (6), a breakdown protection region (2) and a blocking insulating layer (11), forming a tunneling insulating layer (7); Step eleven, etching the blocking insulating layer (11) on the side of the tunneling insulating layer (7) on both sides of the base area away from the base area; Step 12, depositing metal or heavily doped polysilicon on the wafer, so that the blocking insulating layer (11) etched in step 11 is completely filled; Step 13. Planarize the surface to expose the emitter region (3), base region (4), collector region (5), conductive layer (6), tunnel insulating layer (7), and breakdown protection region (2) and a blocking insulating layer (11), initially forming a gate electrode (8); Step 14, depositing an insulating medium above the wafer to further form a blocking insulating layer (11); Step 15. Etching away the blocking insulating layer (11) above the gate electrode (8) formed in step 13 through an etching process; Step 16. Deposit metal or heavily doped polysilicon on the wafer, so that the blocking insulating layer (11) etched in step 15 is completely filled, and the surface is planarized to further form the gate electrode (8) ; Step 17: Etching away the part other than the part used to form the wiring between the device units through an etching process, and further forming the gate electrode (8); Step 18, depositing an insulating medium on the wafer, planarizing the surface, and further forming a blocking insulating layer (11); Step nineteen, etching away the blocking insulating layer (11) above the emitter region (3) and the collector region (5) through an etching process to form through holes for the emitter electrode (9) and the collector electrode (10); Step 20. Deposit metal on the wafer, so that the through holes of the emitter (9) and collector (10) formed in step 18 are completely filled, and form the emitter (9) and collector (10).