CN102903757B - Method for forming SOI MOSFET (Silicon On Insulator Metal-Oxide-Semiconductor Field Effect Transistor) body contact by using side wall process - Google Patents

Abstract

The invention provides a SOI MOSFET body contact forming method using side wall technology. It includes a bottom semiconductor substrate 1 formed by etching; a left buried oxide layer 6 (A) and a right buried oxide layer 6 (B) on the bottom semiconductor substrate (1); a top silicon film (7); A gate oxide layer (8) is grown on the top silicon film (7); a polysilicon gate (9) is located on the gate oxide layer (8); the feature is that the leads of the body contact (11) are located at two different heights between the horizontal planes of the underlying semiconductor substrate (1). The present invention provides a SOI MOSFET body contact structure capable of deriving redundant holes in the neutral body region, realizing anti-floating body effect and preventing self-heating effect; also provides a simplified manufacturing process and reduced manufacturing cost, A method for forming an SOI MOSFET body contact structure for improving device reliability.

Description

A method for forming SOI MOSFET body contact using sidewall technology

technical field

The invention relates to an electronic component, and the invention also relates to a method for forming the electronic component. Specifically, it is a SOI MOSFET body contact structure using sidewall technology and its forming method.

Background technique

As a full dielectric isolation technology, SOI technology has many incomparable advantages over bulk silicon technology. However, SOI devices also have some parasitic effects, among which the floating body effect of partially depleted SOI devices is the biggest problem compared with bulk silicon devices, which has also become one of the reasons restricting the development and wide application of SOI technology. Floating body effect will produce kink effect, drain breakdown voltage reduction, abnormal subthreshold slope, etc., which seriously affect the performance of the device.

Due to the impact of the floating body effect on device performance, how to suppress the floating body effect has become a hot spot in the research of SOI devices. The suppression methods for the floating body effect can be divided into two categories: one is to release the accumulated holes in the body region by means of body contact, and the other is to control the minority carrier lifetime by injecting recombination centers from the perspective of technology.

Body contact refers to making the neutral region above the buried oxide layer and the bottom of the silicon film in an electrically floating state contact with the outside, so that holes cannot accumulate in this region. Traditional body contact methods include T-type gate, H-type gate and BTS structure. However, the body contact resistance of traditional T-gate and H-gate devices increases with the increase of the channel width, and the corresponding floating body effect is more significant. Although the method of increasing the thickness of the silicon film can be adopted to solve the problem of high contact resistance, but As the thickness of the silicon film increases, the source-drain junction depth of the device increases, which increases the body parasitic capacitance, thereby affecting the performance of the device. The BTS structure is to form a P+ region directly in the source region. This structure makes the source and drain asymmetrical, making the source and drain unable to be interchanged, thereby reducing the effective channel width.

Therefore, how to reduce the contact resistance and parasitic capacitance while realizing the body contact structure has become a hot spot in researching the body contact problem of SOI MOSFET devices.

At the same time, due to the low thermal conductivity of the SOI buried oxide layer, the SOI device has a DC self-heating effect. As the drain voltage and gate voltage of the device increase, the power consumption increases, and the temperature in the silicon body rises above the ambient temperature. Mobility, threshold voltage, impact ionization, floating body potential, leakage current, and subthreshold slope in the device etc. will be affected by temperature, which will cause changes in device characteristics. However, in most of the existing body contact structures, there are few studies on the resistance to the self-heating effect of the device.

Many existing methods to suppress the floating body effect of SOI MOSFET devices through the body contact structure are to form a trench under the source region or the drain region, and connect the neutral body region to the gate electrode to lead out the neutral body region. Although this method can suppress the floating body effect of SOI MOSFET devices, it sometimes destroys the isolation effect of SOI MOSFET devices. At the same time, due to the formation of contact trenches, mask plates and etching techniques must be used repeatedly in the formation method. This complicates the manufacturing process of the device, which is not conducive to reducing the production cost.

Contents of the invention

The object of the present invention is to provide a kind of SOI MOSFET body contact structure that can lead out redundant hole in the neutral body region, realize anti-floating body effect, also have the generation that prevents self-heating effect simultaneously and utilize side wall technology. The purpose of the present invention is also to provide a method for simplifying the manufacturing process, reducing the manufacturing cost, and improving the reliability of the device using the SOI MOSFET body contact structure of the sidewall process.

The purpose of the present invention is achieved like this:

The SOI MOSFET body contact structure utilizing the sidewall process in the present invention is: a bottom semiconductor substrate 1 formed by etching to form a step structure with two different height levels; layer 6A and the right buried oxide layer 6B; a top silicon film 7 on the left buried oxide layer 6A and right buried oxide layer 6B and the underlying semiconductor substrate 1; a gate oxide grown on the top silicon film 7 layer 8; a polysilicon gate 9 located on the gate oxide layer 8; characterized in that the terminal of the body contact 11 is located between two levels of the underlying semiconductor substrate 1 at different heights.

The material of the conductive substrate 1 is silicon, germanium, group III~V compound semiconductor materials, group II~VI compound semiconductor materials or other compound semiconductor materials, and single crystal materials can also be used.

The masking film 2 is made of a hard masking material or a soft masking material, but the material used for the masking film 2 cannot be the same as that of the underlying semiconductor substrate 1 .

The single crystal material can be made into an n-type substrate or a p-type substrate by doping.

The present invention utilizes the SOI MOSFET body contact structure forming method of side wall technology, is characterized in that comprising the following steps:

Step 1. Deposit a masking film 2 on a semiconductor substrate 1, and apply a photoresist on the masking film 2. The semiconductor substrate 1 is used as the underlying substrate of the device.

Step 2: Carry out the first etching on the underlying semiconductor substrate 1 to remove the redundant masking film 2 and expose part of the underlying semiconductor substrate 1 .

Step 3: Continue etching the underlying semiconductor substrate 1 to form two horizontal surfaces with different heights, and remove the remaining masking film 2 .

Step 4, depositing a silicon nitride isolation layer 4 on the underlying semiconductor substrate 1, and performing a second etching on the silicon nitride isolation layer 4 to form a silicon nitride spacer 5.

Step 5, growing the left buried oxide layer 6A and the right buried oxide layer 6B on the underlying semiconductor substrate, and etching the silicon nitride sidewall 5 for the third time to expose the underlying semiconductor substrate 1 .

Step 6, growing the top silicon film 7 epitaxially, and forming a body contact 11 to lead out a channel at the place where the top silicon film 7 is directly connected with the bottom semiconductor substrate 1 .

Step 7, forming an active region by photolithography, growing a gate oxide layer 8, depositing a polysilicon gate 9, photoetching the polysilicon gate 9, and implanting source and drain terminals to form a source terminal and a drain terminal.

The main features of the method of the present invention are as follows:

The invention proposes a SOI MOSFET body contact structure utilizing a sidewall process and a forming method thereof. Compared with the traditional method of simply using trench etching and mask etching technology to start from the top layer of the device and etch down layer by layer to manufacture the SOIMOSFET body contact structure, the present invention utilizes sidewall technology and epitaxial growth technology The purpose of simplifying the process steps is achieved. In particular, the body terminal is implemented by an epitaxial silicon layer directly connected to the underlying semiconductor substrate. This structure can not only lead out the redundant holes in the neutral body region, realize the anti-floating body effect, but also effectively prevent self-heating. The production of the effect. The invention can realize the body contact structure and increase the effectiveness of anti-floating body effect without adding process steps.

Description of drawings

1 is a schematic diagram of a bottom semiconductor substrate with a masking film before etching;

Fig. 2 is a cross-sectional view of the structure of Fig. 1 after applying photoresist;

Fig. 3 is a schematic diagram of the first etching of the structure of Fig. 1;

4 is a cross-sectional view after depositing a silicon nitride isolation layer on the etched underlying semiconductor substrate;

FIG. 5 is a schematic diagram of washing away excess silicon nitride isolation layers on the basis of the structure shown in FIG. 4 to form silicon nitride side walls;

Fig. 6 is a schematic diagram of depositing a SiO layer _on the structure shown in Fig. 5;

7 is a schematic diagram of the structure after the silicon nitride sidewall is washed away;

Fig. 8 is a cross-sectional view of epitaxially growing a top silicon film on the basis of the structure shown in Fig. 7;

Fig. 9 is a schematic diagram of the final device structure.

detailed description

The present invention is described in detail below in conjunction with accompanying drawing example:

Combined with Figure 1. A masking film 2 is shown deposited on an underlying semiconductor substrate 1 . The material of the underlying semiconductor substrate 1 can be freely selected, for example: silicon, germanium, group III~V compound semiconductor materials, group II~VI compound semiconductor materials or other compound semiconductor materials, etc., and single crystal materials can also be used. For single crystal materials It can also be made into an n-type substrate or a p-type substrate by doping. The material used for the masking film 2 can be a hard masking material like _SiO2 , or a soft masking material like photoresist, but no matter which type of masking material is used, it should be noted that the material used for the masking film cannot be compatible with the underlying semiconductor material. The same substrate material prevents problems during etching.

Combined with Figure 2. Glue is applied on a part of the masking film 2 to form a photoresist protective layer 3 to protect a part of the underlying semiconductor substrate, so that this part of the underlying semiconductor substrate will not be subjected to photo-etching in the next step.

Combined with Figure 3. The first photoetching is performed on the glue-coated structure, and the uncoated masking film 2 is etched away until the underlying semiconductor substrate 1 is exposed.

Combined with Figure 4. The etching is continued to form two horizontal substrate surfaces 1A and 1B with different heights on the underlying semiconductor substrate 1, and the spacer surface 10 of the underlying semiconductor substrate is directly formed between the two horizontal substrate surfaces 1A and 1B. Remove the photoresist 3 and the redundant masking film 2, and then grow nitride on the first horizontal substrate surface 1A, the second horizontal substrate surface 1B and the bottom semiconductor substrate spacer surface 10 by low-pressure chemical vapor deposition. Silicon isolation layer 4.

Combined with Figure 5. The silicon nitride isolation layer 4 is directly etched by ion etching, and the silicon nitride isolation layer on the horizontal substrate surface 1A and the horizontal substrate surface 1B is removed to form a silicon nitride spacer 5 as shown in the figure. .

Combined with Figure 6. On the basis of the structure shown in FIG. 5 , a buried oxide layer 6A on the left and a buried oxide layer 6B on the right are grown on the horizontal substrate surface 1A and the horizontal substrate surface 1B as the buried oxide layer of the SOI MOSFET device.

Combined with Figure 7. The buried oxide layer 6A on the left and the buried oxide layer 6B on the right are coated with glue for protection, and a third etching is performed to remove the silicon nitride sidewall 5 by etching, and then remove excess photoresist.

Combined with Figure 8. The top silicon film 7 is epitaxially grown, and the physical properties of the material can be the same as or different from the material of the underlying semiconductor substrate. The body contact 11 is formed by the region between the left buried oxide layer 6A and the right buried oxide layer 6B.

Combined with Figure 9. The structure shown in FIG. 8 is photolithographically formed to form an active region, a gate oxide layer is grown, a polysilicon gate is deposited, the polysilicon gate is photolithographically etched, and source and drain terminals are implanted to form a source terminal and a drain terminal.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be noted that the above descriptions are only specific embodiments of the present invention, and do not limit the present invention. Within the spirit and principles of the present invention, all adjustments and optimizations should be included in the protection scope of the present invention.

Claims (1)

1. a kind of SOI MOSFET body contact structure formation method utilizing side wall technology, it is characterized in that comprising the following steps: Step 1, depositing a masking film (2) on the semiconductor substrate (1), and coating photoresist on the masking film (2), and the semiconductor substrate (1) is used as the underlying substrate of the device; Step 2. Etching the underlying semiconductor substrate (1) for the first time, removing excess masking film (2), and exposing part of the underlying semiconductor substrate (1); Step 3, continue etching the underlying semiconductor substrate (1) to form two horizontal surfaces with different heights, and remove the remaining masking film (2); Step 4, depositing a silicon nitride isolation layer (4) on the underlying semiconductor substrate (1), and performing a second etching on the silicon nitride isolation layer (4) to form a silicon nitride spacer (5); Step 5, grow the left buried oxide layer 6 (A) and the right buried oxide layer 6 (B) on the underlying semiconductor substrate, and remove the silicon nitride sidewall (5) by etching for the third time, exposing the underlying semiconductor substrate (1); Step 6, epitaxially growing the top silicon film (7), forming a body contact (11) lead-out channel at the point where the top silicon film (7) is directly connected to the bottom semiconductor substrate (1); Step 7, photolithography to form the active region, growing the gate oxide layer (8), depositing the polysilicon gate (9), photoetching the polysilicon gate (9), implanting the source and drain ends to form the source and drain ends, and finally obtaining the spacer Process SOI MOSFET body contact structure.