CN104485352B - Groove embeds gate insulation tunnelling enhancing transistor and its manufacturing method - Google Patents

Abstract

The invention relates to a gate insulation tunneling enhancement transistor embedded in a groove. Compared with MOSFETs or TFETs devices of the same size, the design scheme adopted realizes the advantages of low parasitic capacitance and low reverse leakage current without increasing the chip area. . The extremely sensitive relationship between the impedance of the tunneling insulating layer and its internal field strength is used to achieve excellent switching characteristics; the tunneling signal is enhanced through the emitter to achieve excellent forward conduction characteristics; compared with ordinary planar structures, it avoids the emission area, The base area and the collector area are arranged in sequence along the horizontal direction, thus saving chip area and achieving higher integration. In addition, the present invention also proposes a specific manufacturing method of an insulated gate-insulated tunneling enhancement transistor embedded in a groove. The transistor significantly improves the working characteristics of the nanoscale integrated circuit unit and is suitable for popularization and application.

Description

Insulated gate insulated tunneling enhanced transistor embedded in groove and manufacturing method thereof

Technical field:

The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a gate-insulated tunneling enhancement transistor embedded in a groove and a manufacturing method thereof, which are suitable for manufacturing high-performance ultra-high-integrated integrated circuits.

Background technique:

Currently, as the device size of metal-oxide-semiconductor field-effect transistors (MOSFETs), the basic unit of integrated circuits, continues to shrink, the distance between the drain electrode and the gate electrode, or the distance between the source electrode and the gate electrode, is also continuously reduced. Small, this will significantly increase the gate-source, source-gate, gate-drain and drain-gate parasitic capacitance of the device, increase the power consumption of the integrated circuit, increase the propagation delay and negative feedback of the signal, and affect the gain-bandwidth product .

On the other hand, the continuous shortening of the channel length of MOSFETs has led to a significant decline in the switching characteristics of the device. The specific performance is that the subthreshold swing increases with the decrease of the channel length, and the static power consumption increases significantly. Although the degradation of the performance of the device can be alleviated by improving the structure of the gate electrode, when the size of the device is further reduced, the switching characteristics of the device will continue to deteriorate.

Compared with MOSFETs, tunneling field effect transistors (TFETs) proposed in recent years have improved their average subthreshold swing, but their forward current is too small, and the characteristics of parasitic capacitance generated under the same size are not the same. improve.

In addition, TFETs can be formed as the tunneling part of TFETs by introducing materials with narrower band gaps such as compound semiconductors, silicon germanium, or germanium, which can increase the tunneling probability to improve switching characteristics, but increases the difficulty of the process. Using a high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot essentially improve the tunneling probability of the silicon material. Therefore, for TFETs The improvement of forward conduction characteristics is very limited.

In addition, since both TFETs and MOSFETs control the electric field, potential and carrier distribution inside the gate insulating layer and semiconductor through the electric field effect of the gate electrode, in order to improve the control ability of the gate electrode to the inside of the semiconductor, high dielectric The constant and thinning gate insulating layer strengthens the control ability of the gate electrode, but at the same time shortens the distance between the gate electrode and the drain region, the gate electrode and the source region, so that the overlapping area of the gate electrode and the drain electrode is at the gate electrode Larger gate-induced-drain leakage (GIDL) or gate-induced-source leakage (GISL) currents are generated when the polarity is reverse-biased.

Invention content:

purpose of invention

In order to completely solve the problem of significant increase in parasitic capacitance due to the continuous shrinking of device size under the premise of being compatible with existing silicon-based process technologies, significantly reduce the reverse leakage current of the device, and significantly improve the switching of nanoscale integrated circuit basic unit devices characteristics, and ensure that the device has good forward current conduction characteristics while reducing the sub-threshold swing, the invention provides a groove-embedded gate insulation tunneling enhancement transistor suitable for high-performance, high-integration integrated circuit manufacturing and methods of manufacture thereof.

Technical solutions

The present invention is achieved through the following technical solutions:

The gate-insulated tunneling enhanced transistor embedded in the groove adopts a bulk silicon wafer including only a single-crystal silicon substrate 1 as a device substrate, or adopts an SOI wafer including a single-crystal silicon substrate 1 and a wafer insulating layer 2 at the same time. The circle serves as the substrate for generating devices; the base region 4 is located above the single crystal silicon substrate 1 of the bulk silicon wafer or the wafer insulating layer 2 of the SOI wafer, and has groove-shaped features; the emitter region 3 and the collector region 5 are respectively located on both sides of the upper end of the base region 4 groove; the emitter 9 is located above the emitter region 3; the collector electrode 10 is located above the collector region 5; the conductive layer 6 is located on the inner wall of the groove formed by the base region 4, and is Region 4 is surrounded on three sides; tunnel insulating layer 7 is located on the inner wall of conductive layer 6 and is surrounded by conductive layer 6 on three sides; the side and bottom of gate electrode 8 are surrounded by three inner walls of tunnel insulating layer 7; blocking insulating layer 11 is located in the device unit Between each electrode and between each device unit and between each electrode to play an isolation role.

Adjacent base regions 4 are isolated by blocking insulating layer 11; adjacent emitter regions 3 and collector regions 5 are isolated by blocking insulating layer 11; adjacent emitters 9 and collectors 10 are separated by blocking insulating layers. Layer 11 isolation.

In order to achieve the device functions described in the present invention, the present invention proposes a gate embedded insulated tunneling enhancement transistor in a groove and a manufacturing method thereof, the core structural features of which are:

The groove-shaped feature is composed of the emitter region 3, the base region 4 and the collector region 5, and the base region 4 itself also has a groove-shaped feature.

Only the upper surface of the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 is in contact with the blocking insulating layer 11, and the top upper surfaces of the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 are lower than the groove side of the base region 4 top surface of the wall.

The gate electrode 8 is an electrode for controlling the tunneling effect generated by the tunneling insulating layer 7, and is an electrode for controlling the turning on and off of the device.

The tunneling insulating layer 7 is an insulating material layer for generating gate electrode tunneling current, its inner wall is in contact with the gate electrode 8 , and its outer wall is in contact with the conductive layer 6 .

The outer wall of the conductive layer 6 forms ohmic contact with the base region 4 and is made of metal material or semiconductor material with the same impurity type as the base region 4 and with a doping concentration greater than 10 ¹⁹ per cubic centimeter.

The conductive layer 6 is essentially the floating base of the embedded gate insulation tunneling enhancement transistor in the groove. When the tunneling insulating layer 7 tunnels, the current flows from the gate electrode 8 to the conductive layer 6 through the tunneling insulating layer 7, and is The base area 4 supplies power.

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 3 and the collector electrode 10. ohmic contact.

Groove-embedded gate insulation tunneling enhancement transistor, taking N-type as an example, emitter region 3, base region 4 and collector region 5 are respectively N region, P region and N region, and its specific working principle is: when the collector 10 is forward-biased and the gate electrode 8 is at a low potential, there is no sufficient potential difference between the gate electrode 8 and the conductive layer 6. At this time, the tunneling insulating layer 7 is in a high-resistance state, and no obvious tunneling current passes through, so that the base Between the region 4 and the emitter region 3, a large enough base current cannot be formed to drive the embedded gate insulation tunneling enhancement transistor and its manufacturing method in the groove, that is, the device is in an off state; as the voltage of the gate electrode 8 gradually increases , the potential difference between the gate electrode 8 and the conductive layer 6 gradually increases, so that the electric field intensity in the tunneling insulating layer 7 between the gate electrode 8 and the conductive layer 6 also gradually increases. When the electric field intensity is below the critical value, the tunneling insulating layer 7 still maintains a good high-resistance state, and the potential difference between the gate electrode and the emitter is almost completely dropped between the inner wall and the outer wall of the tunneling insulating layer 7. The potential difference between the base region and the emitter region is extremely small, so there is almost no current flowing in the base region, and the device is therefore kept in a good off state, and when the electric field strength in the tunneling insulating layer 7 is above the critical value, The tunneling insulating layer 7 will generate obvious tunneling current due to the tunneling effect, and the tunneling current will rise steeply at a very fast speed as the potential of the gate electrode 8 increases, which makes the tunneling insulating layer 7 In the extremely short potential change interval of the gate electrode, the high resistance state is rapidly converted to the low resistance state. When the tunneling insulating layer 7 is in the low resistance state, the tunneling insulating layer 7 is formed between the gate electrode 8 and the conductive layer 6. The resistance is much smaller than the resistance formed between the conductive layer 6 and the emitter 3, which makes a sufficiently large forward bias voltage formed between the base region 4 and the emitter region 3, and under the action of the tunneling effect, in A large amount of current moves between the inner and outer walls of the tunneling insulating layer 7, and the conductive layer 6 serves as the floating base of the insulated gate insulation tunneling enhancement transistor in the groove. When tunneling occurs in the tunneling insulating layer 7, the current flows from the gate electrode 8 flows to the conductive layer 6 through the tunneling insulating layer 7, and supplies power to the base region 4; the current in the base region 4 flows out from the collector after being strengthened by the emitter region 3, and the device is in an on state at this time.

Advantages and effects

The present invention has following advantage and beneficial effect:

1. Low parasitic capacitance characteristics

The gate insulation tunneling enhancement transistor embedded in the groove, compared with MOSFETs or TFETs devices, the role of the emitter 9 and the source electrode is equivalent, and the role of the collector 10 and the drain electrode is equivalent, because the gate electrode 8, the tunneling insulating layer 7 and the conductive Layer 6 is embedded in the groove formed by base region 4. Only the upper surface of gate electrode 8, tunneling insulating layer 7 and conductive layer 6 is in contact with blocking insulating layer 11, and due to gate electrode 8, tunneling The top upper surfaces of the insulating layer 7 and the conductive layer 6 are lower than the top upper surfaces of the sidewalls of the groove of the base region 4, which makes the composite gate insulating layer composed of the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 smooth. Through the base away from the emitter 9 and the collector 10, because the distance between the top upper surface of the gate electrode 8, the tunnel insulating layer 7 and the conductive layer 6 and the top upper surface of the base region 4 groove sidewalls is not Affects the size of the chip area occupied by the device unit, which avoids the gate-source, source-gate, gate-drain and The parasitic capacitance between the drain and the gate is significantly increased, that is, compared with MOSFETs or TFETs devices, under the same size process, the embedded gate insulation tunneling enhancement transistor in the groove has the advantage of low parasitic capacitance.

2. Low reverse leakage current

Insulated tunneling enhanced transistor embedded in the groove, since there is no overlap between the gate electrode and the drain electrode or between the gate electrode and the source electrode like MOSFETs or TFETs between the gate electrode 8 and the emitter region 3 or the collector region 5 area, the potential change of the gate electrode 8 away from the emitter region 3 or the collector region 5 will not generate a strong enough electric field effect on the emitter region 3 or the collector region 5, and will not cause the emitter region 3 or the collector region 5 to be due to The band-to-band tunneling current effect caused by strong energy band bending, so compared with MOSFETs or TFETs devices, the gate-insulated tunneling enhancement transistor embedded in the groove has the advantage of low reverse leakage current.

3. Excellent switching characteristics

Groove-embedded gate insulation tunneling enhancement transistor and its manufacturing method, using the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, by selecting an appropriate tunneling insulating material for the tunneling insulating layer 7 , and properly adjust the sidewall height, sidewall and bottom thickness of the tunneling insulating layer 7, the tunneling insulating layer 7 can realize the high-resistance state and the low-resistance state within a very small range of the gate electrode potential change. The conversion can achieve better switching characteristics.

4. High forward current

The gate insulation tunneling enhancement transistor is embedded in the groove, and the gate insulation tunneling current flows to the base region through the conductive layer 6, and then passes through the emission region for signal enhancement, and ordinary TFETs only use a small amount of semiconductor interband tunneling current as the conduction of the device Compared with the current, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary TFETs devices, the gate insulation tunneling enhancement transistor embedded in the groove can achieve higher forward conduction current.

5. High integration

A gate-insulated tunneling enhancement transistor is embedded in the groove, and the base region 4 has a groove-shaped geometric feature. The emitter region 3 and the collector region 5 are formed above the two sides of the groove in the base region 4. Compared with the ordinary planar structure, the groove The embedded gate insulation tunneling enhanced transistor avoids the sequential arrangement of the emitter region 3 , the base region 4 and the collector region 5 along the horizontal direction, thus saving chip area and achieving higher integration.

Description of drawings

1 is a schematic diagram of a two-dimensional structure formed on an SOI substrate with a gate-insulated tunneling enhancement transistor embedded in a groove of the present invention;

Figure 2 is a schematic diagram of Step 1,

Figure 3 is a schematic diagram of step two,

Figure 4 is a schematic diagram of step three,

Figure 5 is a schematic diagram of step four,

Figure 6 is a schematic diagram of step five,

Figure 7 is a schematic diagram of step six,

Figure 8 is a schematic diagram of step seven,

Figure 9 is a schematic diagram of Step 8,

Figure 10 is a schematic diagram of step nine,

Figure 11 is a schematic diagram of step ten,

Figure 12 is a schematic diagram of step eleven,

Figure 13 is a schematic diagram of step twelve,

Figure 14 is a schematic diagram of step 13,

Figure 15 is a schematic diagram of step fourteen,

Figure 16 is a schematic diagram of step fifteen,

Figure 17 is a schematic diagram of step sixteen,

Fig. 18 is a schematic diagram of step seventeen.

Explanation of reference signs:

1. Single crystal silicon substrate; 2. Wafer insulating layer; 3. Emitter region; 4. Base region; 5. Collector region; 6. Conductive layer; 7. Tunneling insulating layer; 8. Gate electrode; 9. Emitter; 10, collector; 11, blocking insulating layer.

Detailed ways

Below in conjunction with accompanying drawing, the present invention will be further described:

Figure 1 is a schematic diagram of a two-dimensional structure of a gate-insulated tunneling enhancement transistor embedded in a groove of the present invention formed on an SOI substrate; it specifically includes a single crystal silicon substrate 1; a wafer insulating layer 2; an emitter region 3; a base region 4 ; Collector region 5; Conductive layer 6; Tunneling insulating layer 7; Gate electrode 8; Emitter 9; Collector 10;

The gate-insulated tunneling enhanced transistor embedded in the groove adopts a bulk silicon wafer including only a single-crystal silicon substrate 1 as a device substrate, or adopts an SOI wafer including a single-crystal silicon substrate 1 and a wafer insulating layer 2 at the same time. The circle serves as the substrate for generating devices; the base region 4 is located above the single crystal silicon substrate 1 of the bulk silicon wafer or the wafer insulating layer 2 of the SOI wafer, and has groove-shaped features; the emitter region 3 and the collector region 5 are respectively located on both sides of the upper end of the base region 4 groove; the emitter 9 is located above the emitter region 3; the collector electrode 10 is located above the collector region 5; the conductive layer 6 is located on the inner wall of the groove formed by the base region 4, and is Region 4 is surrounded on three sides; tunnel insulating layer 7 is located on the inner wall of conductive layer 6 and is surrounded by conductive layer 6 on three sides; the side and bottom of gate electrode 8 are surrounded by three inner walls of tunnel insulating layer 7; blocking insulating layer 11 is located in the device unit Between each electrode and between each device unit and between each electrode to play an isolation role.

In order to achieve the device functions described in the present invention, the present invention proposes a gate embedded insulated tunneling enhancement transistor in a groove and a manufacturing method thereof, the core structural features of which are:

The groove-shaped feature is composed of the emitter region 3, the base region 4 and the collector region 5, and the base region 4 itself also has a groove-shaped feature.

Only the upper surface of the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 is in contact with the blocking insulating layer 11, and the top upper surfaces of the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 are lower than the groove side of the base region 4 top surface of the wall.

The gate electrode 8 is an electrode that controls the tunneling effect of the tunneling insulating layer 7, and is an electrode that controls the turning on and off of the device;

The tunneling insulating layer 7 is an insulating material layer for generating gate electrode tunneling current, its inner wall is in contact with the gate electrode 8 , and its outer wall is in contact with the conductive layer 6 .

The outer wall of the conductive layer 6 forms ohmic contact with the base region 4 and is made of metal material or semiconductor material with the same impurity type as the base region 4 and with a doping concentration greater than 10 ¹⁹ per cubic centimeter.

The conductive layer 6 is essentially the floating base of the embedded gate insulation tunneling enhancement transistor in the groove. When the tunneling insulating layer 7 tunnels, the current flows from the gate electrode 8 to the conductive layer 6 through the tunneling insulating layer 7, and is Base area 4 power supply;

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 3 and the collector electrode 10. ohmic contact.

Groove-embedded gate insulation tunneling enhancement transistor, taking N-type as an example, emitter region 3, base region 4 and collector region 5 are respectively N region, P region and N region, and its specific working principle is: when the collector 10 is forward-biased and the gate electrode 8 is at a low potential, there is no sufficient potential difference between the gate electrode 8 and the conductive layer 6. At this time, the tunneling insulating layer 7 is in a high-resistance state, and no obvious tunneling current passes through, so that the base Between the region 4 and the emitter region 3, a large enough base current cannot be formed to drive the embedded gate insulation tunneling enhancement transistor and its manufacturing method in the groove, that is, the device is in an off state; as the voltage of the gate electrode 8 gradually increases , the potential difference between the gate electrode 8 and the conductive layer 6 gradually increases, so that the electric field intensity in the tunneling insulating layer 7 between the gate electrode 8 and the conductive layer 6 also gradually increases. When the electric field intensity is below the critical value, the tunneling insulating layer 7 still maintains a good high-resistance state, and the potential difference between the gate electrode and the emitter is almost completely dropped between the inner wall and the outer wall of the tunneling insulating layer 7. The potential difference between the base region and the emitter region is extremely small, so there is almost no current flowing in the base region, and the device is therefore kept in a good off state, and when the electric field strength in the tunneling insulating layer 7 is above the critical value, The tunneling insulating layer 7 will generate obvious tunneling current due to the tunneling effect, and the tunneling current will rise steeply at a very fast speed as the potential of the gate electrode 8 increases, which makes the tunneling insulating layer 7 In the extremely short potential change interval of the gate electrode, the high resistance state is rapidly converted to the low resistance state. When the tunneling insulating layer 7 is in the low resistance state, the tunneling insulating layer 7 is formed between the gate electrode 8 and the conductive layer 6. The resistance is much smaller than the resistance formed between the conductive layer 6 and the emitter 3, which makes a sufficiently large forward bias voltage formed between the base region 4 and the emitter region 3, and under the action of the tunneling effect, in A large amount of current moves between the inner and outer walls of the tunneling insulating layer 7, and the conductive layer 6 serves as the floating base of the insulated gate insulation tunneling enhancement transistor in the groove. When tunneling occurs in the tunneling insulating layer 7, the current flows from the gate electrode 8 flows to the conductive layer 6 through the tunneling insulating layer 7, and supplies power to the base region 4; the current in the base region 4 flows out from the collector after being strengthened by the emitter region 3, and the device is in an on state at this time.

The gate insulation tunneling enhancement transistor embedded in the groove, compared with MOSFETs or TFETs devices, the role of the emitter 9 and the source electrode is equivalent, and the role of the collector 10 and the drain electrode is equivalent, because the gate electrode 8, the tunneling insulating layer 7 and the conductive Layer 6 is embedded in the groove formed by base region 4. Only the upper surface of gate electrode 8, tunneling insulating layer 7 and conductive layer 6 is in contact with blocking insulating layer 11, and due to gate electrode 8, tunneling The top upper surfaces of the insulating layer 7 and the conductive layer 6 are lower than the top upper surfaces of the sidewalls of the groove of the base region 4, which makes the composite gate insulating layer composed of the gate electrode 8, the tunneling insulating layer 7 and the conductive layer 6 smooth. Through the base away from the emitter 9 and the collector 10, because the distance between the top upper surface of the gate electrode 8, the tunnel insulating layer 7 and the conductive layer 6 and the top upper surface of the base region 4 groove sidewalls is not Affects the size of the chip area occupied by the device unit, which avoids the gate-source, source-gate, gate-drain and The parasitic capacitance between the drain and the gate is significantly increased, that is, compared with MOSFETs or TFETs devices, under the same size process, the embedded gate insulation tunneling enhancement transistor in the groove has the advantage of low parasitic capacitance.

Insulated tunneling enhanced transistor embedded in the groove, since there is no overlap between the gate electrode and the drain electrode or between the gate electrode and the source electrode like MOSFETs or TFETs between the gate electrode 8 and the emitter region 3 or the collector region 5 area, the potential change of the gate electrode 8 away from the emitter region 3 or the collector region 5 will not generate a strong enough electric field effect on the emitter region 3 or the collector region 5, and will not cause the emitter region 3 or the collector region 5 to be due to The band-to-band tunneling current effect caused by strong energy band bending, so compared with MOSFETs or TFETs devices, the gate-insulated tunneling enhancement transistor embedded in the groove has the advantage of low reverse leakage current.

Groove-embedded gate insulation tunneling enhancement transistor and its manufacturing method, using the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, by selecting an appropriate tunneling insulating material for the tunneling insulating layer 7 , and properly adjust the sidewall height, sidewall and bottom thickness of the tunneling insulating layer 7, the tunneling insulating layer 7 can realize the high-resistance state and the low-resistance state within a very small range of the gate electrode potential change. The conversion can achieve better switching characteristics.

The gate insulation tunneling enhancement transistor is embedded in the groove, and the gate insulation tunneling current flows to the base region through the conductive layer 6, and then passes through the emission region for signal enhancement, and ordinary TFETs only use a small amount of semiconductor interband tunneling current as the conduction of the device Compared with the current, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary TFETs devices, the gate insulation tunneling enhancement transistor embedded in the groove can achieve higher forward conduction current.

A gate-insulated tunneling enhancement transistor is embedded in the groove, and the base region 4 has a groove-shaped geometric feature. The emitter region 3 and the collector region 5 are formed above the two sides of the groove in the base region 4. Compared with the ordinary planar structure, the groove The embedded gate insulation tunneling enhanced transistor avoids the sequential arrangement of the emitter region 3 , the base region 4 and the collector region 5 along the horizontal direction, thus saving chip area and achieving higher integration.

The specific manufacturing process steps of the unit and array of the embedded gate insulation tunneling enhancement transistor in the groove proposed by the present invention on the SOI wafer are as follows:

Step 1. Provide an SOI wafer, the bottom of the SOI wafer is the single crystal silicon substrate 1 of the SOI wafer, and the middle of the SOI wafer is the wafer insulating layer 2. The monocrystalline silicon thin film is doped to form an impurity layer.

Step 2. Doping the single crystal silicon thin film above the SOI wafer by ion implantation or diffusion process again, and forming impurity on the upper surface of the wafer which is opposite to the impurity type in step 1 and whose concentration is not lower than 10 ¹⁹ per cubic centimeter. heavily doped region.

Step 3, forming a cuboid single crystal silicon island array region on the provided SOI wafer by photolithography, etching and other processes.

Step 4: After depositing an insulating medium on the wafer, the surface is planarized to expose the single crystal silicon film, and a blocking insulating layer 11 is preliminarily formed.

Step 5. Etching a groove-shaped region on the single crystal silicon film in the base region through an etching process, wherein the heavily doped regions on both sides of the top of the groove are the emitter region 3 and the collector region 5 respectively, and the remaining part is base area 4.

Step 6. Deposit metal or heavily doped polysilicon with the same impurity type as the base region 4 above the wafer, so that the inside of the groove formed by the emitter region 3, the collector region 5 and the base region 4 in step 5 is completely After being filled, the surface is planarized to expose the emitter region 3 and the collector region 5, and the conductive layer 6 is initially formed.

Step 7. Etching the metal deposited in step 6 or the heavily doped polysilicon having the same impurity type as the base region 4 through an etching process to further form the conductive layer 6 .

Step 8. Deposit a tunneling insulating layer dielectric on the wafer, so that the area surrounded by the three sides of the inner wall of the conductive layer 6 formed in step 7 is completely filled, and then planarize the surface to expose the conductive layer 6, and initially form a tunnel. Wear insulation 7.

Step 9: Etching the tunneling insulating layer dielectric deposited in step 8 through an etching process to further form a tunneling insulating layer 7 with a U-shaped geometric feature.

Step 10. Deposit metal material or heavily doped polysilicon on the wafer, so that the area surrounded by the three sides of the inner wall of the tunneling insulating layer 7 formed in step 9 is completely filled, and then planarize the surface to expose the emitter region 3 , the collector region 5 , the conductive layer 6 and the top of the tunneling insulating layer 7 to initially form a gate electrode 8 .

Step 11: Etching away the upper parts of the conductive layer 6 on both sides by an etching process, so that the tops of both sides of the conductive layer 6 are lower than the tops of the two sides of the base region 4 , and further form the conductive layer 6 .

Step 12: Deposit an insulating dielectric layer on the wafer, and planarize the surface to expose the emitter region 3 , collector region 5 , tunnel insulating layer 7 and the top of the gate electrode 8 , and further form a blocking insulating layer 11 .

Step 13: Etch away the parts above the wafer on both sides of the tunneling insulating layer 7 through an etching process, so that the tops of both sides of the tunneling insulating layer 7 are not higher than the top of the conductive layer 6 formed in step 11 , and further form a tunnel insulating layer 7 .

Step 14. Deposit an insulating dielectric layer on the wafer, so that the etched part of the tunneling insulating layer 7 in step 13 is completely filled with the insulating dielectric layer, and then planarize the surface to expose the gate electrode 8 , and further form a blocking insulating layer 11 .

Step 15: Etch the upper part of the gate electrode 8 on the wafer by an etching process, so that the top of the gate electrode 8 is not higher than the top of the tunnel insulating layer 7 formed in step 13, and further form the gate electrode 8.

Step 16. Deposit an insulating dielectric layer on the wafer, so that the etched part of the gate electrode 8 in step 15 is completely filled with the insulating dielectric layer, and then planarize the surface to further form a blocking insulating layer 11 .

Step 17: Etch through holes for forming the emitter 9 and the collector 10 inside the blocking insulating layer 11 above the emitter region 3 and the collector region 5, and deposit a metal layer on the upper surface of the wafer, The through hole is filled with metal, and then the metal layer is etched to form the emitter 9 and the collector 10 .

Claims (8)

1. A gate-insulated tunneling enhanced transistor embedded in a groove, characterized in that a bulk silicon wafer containing only a single-crystal silicon substrate (1) is used as the device substrate, or a bulk silicon wafer containing a single-crystal silicon substrate (1) is used at the same time ) and the SOI wafer of the wafer insulating layer (2) as the substrate for generating the device; the base region (4) is located on the single crystal silicon substrate (1) of the bulk silicon wafer or the wafer insulating layer (2) of the SOI wafer ) and has a groove; the emitter (3) and the collector (5) are respectively located on both sides of the upper end of the groove of the base (4); the emitter (9) is located above the emitter (3); the collector The electrode (10) is located above the collector area (5); the conductive layer (6) is located on the inner wall of the groove formed by the base area (4), surrounded by three sides of the base area (4); the tunneling insulating layer (7) is located on the conductive The inner wall of the layer (6) is surrounded on three sides by the conductive layer (6); the side and bottom of the gate electrode (8) are surrounded by the inner wall of the tunneling insulating layer (7) on three sides; the blocking insulating layer (11) is located in the groove embedded Between the gate insulation tunneling enhancement transistor units and above the gate insulation tunneling enhancement transistor embedded in a single groove; The conductive layer (6) is essentially the floating base of the gate-insulated tunneling enhancement transistor embedded in the groove, and when tunneling occurs in the tunneling insulating layer (7), the current flows from the gate electrode (8) through the tunneling insulating layer (7) flows to the conductive layer (6) and supplies power to the base area (4); There are opposite impurity types between the emitter region (3) and the base region (4), between the collector region (5) and the base region (4), and an ohmic contact is formed between the emitter region (3) and the emitter electrode (9) , an ohmic contact is formed between the collector region (3) and the collector electrode (10). 2. The in-groove embedded gate insulation tunneling enhanced transistor according to claim 1, characterized in that: adjacent base regions (4) are isolated by a blocking insulating layer (11); adjacent emitter regions (3) ) and the collector region (5) are isolated by a blocking insulating layer (11); the adjacent emitter (9) and collector (10) are isolated by a blocking insulating layer (11). 3. The gate-embedded insulated tunneling enhancement transistor in groove according to claim 1, characterized in that: a groove-shaped structure is composed of an emitter region (3), a base region (4) and a collector region (5). 4. The groove-embedded gate insulation tunneling enhancement transistor according to claim 1, characterized in that only the upper surface of the gate electrode (8), the tunneling insulating layer (7) and the conductive layer (6) are connected with the blocking insulating layer (11) are in contact with each other, and the top upper surfaces of the gate electrode (8), the tunneling insulating layer (7) and the conductive layer (6) are lower than the top upper surfaces of the groove sidewalls of the base region (4). 5. The groove-embedded gate insulation tunneling enhancement transistor according to claim 1, characterized in that: the gate electrode (8) is an electrode for controlling the tunneling effect of the tunneling insulating layer (7), and is used to control the opening and closing of the device. off electrodes. 6. The groove-embedded gate insulation tunneling enhancement transistor according to claim 1, characterized in that: the tunneling insulating layer (7) is an insulating material layer for generating gate electrode tunneling current, and its inner wall is in contact with the gate electrode (8) are in contact with each other, and its outer wall and the conductive layer (6) are in contact with each other. 7. The in-groove embedded gate insulation tunneling enhanced transistor according to claim 1, characterized in that: the outer wall of the conductive layer (6) forms an ohmic contact with the base region (4), and the conductive layer (6) is made of a metal material or It is a semiconductor material with the same impurity type as the base region (4) and with a doping concentration greater than 10 ¹⁹ per cubic centimeter. 8. A method for manufacturing a gate-insulated tunneling enhancement transistor embedded in a groove, characterized in that: the process steps are as follows: Step 1. Provide an SOI wafer. Below the SOI wafer is the single crystal silicon substrate (1) of the SOI wafer. In the middle of the SOI wafer is the wafer insulating layer (2). Through ion implantation or diffusion process, the The single crystal silicon film above the SOI wafer is doped to form an impurity layer; Step 2. Doping the single crystal silicon thin film above the SOI wafer by ion implantation or diffusion process again, and forming impurity on the upper surface of the wafer which is opposite to the impurity type in step 1 and whose concentration is not lower than 10 ¹⁹ per cubic centimeter. The heavily doped region; Step 3, forming a rectangular parallelepiped single crystal silicon island array region on the provided SOI wafer through photolithography and etching processes; Step 4, after depositing an insulating medium on the wafer, planarize the surface to expose the single crystal silicon film, and initially form a blocking insulating layer (11); Step 5. Etching a groove-shaped region on the single crystal silicon film in the base region through an etching process, in which the heavily doped regions on both sides of the top of the groove are the emitter region (3) and the collector region (5) , and the rest is the base area (4); Step 6. Deposit metal or heavily doped polysilicon with the same impurity type as the base region (4) on the wafer, so that in step 5, the emitter region (3), the collector region (5) and the base region (4) ) the inside of the groove formed is completely filled, and then the surface is planarized to expose the emitter region (3) and the collector region (5), and a conductive layer (6) is initially formed; Step 7. Etching the metal deposited in step 6 or heavily doped polysilicon having the same impurity type as the base region (4) through an etching process to further form a conductive layer (6); Step 8. Deposit a tunnel insulating layer dielectric on the wafer, so that the area surrounded by the three sides of the inner wall of the conductive layer (6) formed in step 7 is completely filled, and then planarize the surface to expose the conductive layer (6) , initially forming a tunneling insulating layer (7); Step 9: Etching the tunneling insulating layer dielectric deposited in step 8 through an etching process to further form a tunneling insulating layer (7) with U-shaped geometric features; Step 10. Deposit metal material or heavily doped polysilicon on the wafer, so that the area surrounded by the three sides of the inner wall of the tunneling insulating layer (7) formed in step 9 is completely filled, and then planarize the surface to expose the emission region (3), collector region (5), conductive layer (6) and the top of the tunnel insulating layer (7), initially forming a gate electrode (8); Step 11: Etch away the upper part of the conductive layer (6) on both sides by etching process on the wafer, so that the tops of both sides of the conductive layer (6) are lower than the tops of the two sides of the base region (4), further forming a conductive layer(6); Step 12, depositing an insulating dielectric layer on the wafer, and then planarizing the surface to expose the emitter region (3), the collector region (5), the tunnel insulating layer (7) and the top of the gate electrode (8), further forming a blocking insulating layer (11); Step 13: Etch away the upper parts of the two sides of the tunneling insulating layer (7) through an etching process on the wafer, so that the tops of both sides of the tunneling insulating layer (7) are not higher than the conductive layer formed in step 11. The top of the layer (6), further forming a tunneling insulating layer (7); Step 14. Deposit an insulating dielectric layer on the wafer, so that the etched part of the tunneling insulating layer (7) in step 13 is completely filled with the insulating dielectric layer, and then planarize the surface to expose the gate An electrode (8), further forming a blocking insulating layer (11); Step 15: Etching away the upper part of the gate electrode (8) on the wafer by an etching process, so that the top of the gate electrode (8) is not higher than the tunnel insulating layer (7) formed in step 13 On the top, a gate electrode (8) is further formed; Step 16. Deposit an insulating dielectric layer on the wafer, so that the etched part of the gate electrode (8) in step 15 is completely filled with the insulating dielectric layer, and then planarize the surface to further form barrier insulation layer(11); Step seventeen, etching through holes for forming emitter (9) and collector (10) inside the blocking insulating layer (11) above the emitter region (3) and collector region (5), and A metal layer is deposited on the upper surface of the wafer to fill the through hole with metal, and then the metal layer is etched to form an emitter (9) and a collector (10).