CN104064448B - Manufacturing method of SiGe source/drain region - Google Patents

Abstract

The invention discloses a kind of manufacture method of SiGe source /drain region, it includes providing the N-type chip silicon substrate for being formed with grid, and etches the groove for forming source/drain region；The deposited metal film on chip；Ge films are deposited on metallic film；Annealing process is carried out to chip, by metal-induced crystallization, makes the Ge atoms permeatings in Ge films to the interface between metallic film and silicon substrate and is combined with Si, SiGe film is formed；The metallic film on surface and Ge films are removed, the PMOS source drain region with SiGe is formed.The present invention can effectively reduce the temperature of generation SiGe film, and improve the quality of SiGe film, so that boost device yield and device performance.

Description

Manufacturing method of SiGe source/drain region

technical field

The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a method for manufacturing SiGe source/drain regions.

Background technique

With the development of semiconductor integrated circuits, the size reduction of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has continuously improved the speed, performance, density and functional unit cost of integrated circuits. After entering the 90nm technology era, with the substantial reduction in the size of integrated circuit devices, the junction depth of the source/drain (elevated source/drain) is getting shallower and shallower, and it is necessary to use selective epitaxy technology (selective epi SiGe, abbreviated as SEG) to increase The thick source/drain serves as a sacrificial layer for subsequent silicide reactions, thereby reducing series resistance.

For the 65/45nm technology process, a method to improve the performance of PMOS transistors is to etch the PMOS source/drain to form a source/drain region groove (that is, source/drain region U or Sigma shape, "U" or "Σ" shape), and then epitaxial SiGe layer inside the source/drain region (S/D) groove to introduce compressive stress to the channel, which causes the semiconductor crystal lattice to be distorted (stretched or compressed), Generate uniaxial stress in the channel region, which in turn affects the energy band arrangement and the charge transport performance of the semiconductor, and improves the mobility of holes by controlling the magnitude and distribution of stress in the final device ), thereby improving the performance of the device.

Embedded silicon germanium source-drain technology (embedded SiGe, abbreviated as eSiGe) is a strained silicon technology used to improve the performance of PMOS. It increases the hole mobility of PMOS by generating uniaxial compressive stress in the channel, thereby improving the current driving capability of the transistor, and is the core technology in the high-performance process of the 45nm and below technology generation.

At present, the method of selective epitaxial SiGe is mainly used to directly epitaxially epitaxial SiGe thin films in the source and drain regions (PSD) of PMOS. 1 and 2 show the manufacturing method of this prior art, which includes: providing an N-type substrate 201 formed with a gate 205, the gate 205 is protected by a sacrificial layer 204, and etched on the substrate 201 The groove 203 for the source and drain will be formed; the SiGe thin film 206 is epitaxially formed by the SEG method to form a PMOS source and drain region with SiGe.

The disadvantages of using the above-mentioned existing SEG method to form SiGe source/drain regions mainly include two aspects: (1) As the technology nodes gradually become smaller, the Ge content requirements are getting higher and higher, and the critical thickness of SiGe is getting thinner and thinner, resulting in the SEG method Defects in the deposited SiGe film increase sharply and the stress decreases, which is not conducive to the improvement of device performance; (2) The growth temperature of the SEG method is generally above 600 ° C, which brings challenges to the thermal budget of small-sized CMOS devices. Therefore, there is an urgent need for a process method with lower growth temperature of SiGe film and better film deposition quality to replace the existing SEG method to manufacture SiGe source/drain regions.

Contents of the invention

The purpose of the present invention is to make up for the above-mentioned deficiencies in the prior art, and to provide a method for manufacturing SiGe source/drain regions, which can effectively reduce the temperature for forming SiGe thin films, and can improve the quality of SiGe thin films, thereby improving device yield and device performance .

To achieve the above object, the invention provides a method for manufacturing a SiGe source/drain region, which comprises the following steps:

Step S01, providing an N-type wafer silicon substrate formed with a gate, the gate is protected by a sacrificial layer, and etching grooves for forming source/drain regions on the silicon substrate;

Step S02, depositing a metal film on the wafer;

Step S03, depositing a Ge thin film on the metal thin film;

Step S04, performing an annealing process on the wafer, through metal-induced crystallization, the Ge atoms in the Ge film diffuse to the interface between the metal film and the silicon substrate and combine with Si to form a SiGe film;

Step S05 , removing the metal thin film and the Ge thin film on the surface by wet etching to expose the gate and form a PMOS source and drain region with SiGe.

Further, the annealing process in step S04 is rapid thermal annealing (RTA) or laser annealing, the temperature of the rapid thermal annealing is 300-550°C, the annealing time is 10-90 minutes, the temperature of the laser annealing is 330-550°C, The annealing time is 3-20 minutes.

Further, the metal thin film in step S02 is made of a metal that can form metal-induced crystallization.

Further, the metal thin film adopts Al or Ni.

Further, the metal thin film is deposited by physical sputtering or chemical vapor deposition, and the deposition temperature is 20-300°C.

Further, step S03 deposits a Ge thin film by means of atomic vapor deposition, magnetron sputtering or chemical vapor deposition, and the deposition temperature is 20-300°C.

Further, the thickness of the Ge film is not less than the thickness of the metal film.

Further, the thickness of the Ge thin film is 1-3 times that of the metal thin film.

Further, the thickness of the Ge thin film is The thickness of the metal film is

Further, in step S05, the etching rate of SiN, SiO ₂ and SiGe is less than that of the reagent selected for wet etching

Further, the reagent is selected from one or more of nitric acid, sulfuric acid, acetic acid or organic acids.

The manufacturing method of the SiGe source/drain region provided by the present invention utilizes the principle of metal induced crystallization (Metal Induced Crystallization), and through the induction of the metal film, the Ge atoms in the Ge film are diffused to the metal film and the silicon substrate during the low-temperature annealing process. The interface between the bottom and the SiGe grain is combined with Si to form a continuous single-crystal SiGe film, which effectively reduces the temperature for forming the SiGe film and improves the quality of the SiGe film, thereby improving the device yield and device performance. Moreover, the process is simple and controllable, and the cost is low.

Description of drawings

In order to understand the purpose, features and advantages of the present invention more clearly, preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

Fig. 1 and Fig. 2 are the schematic diagrams of SiGe source/drain region manufacturing method in the prior art;

3 is a schematic flow chart of a method for manufacturing a SiGe source/drain region according to the first embodiment of the present invention;

4a to 4e are device cross-sectional views of each step of the method for manufacturing the SiGe source/drain region according to the first embodiment of the present invention.

detailed description

first embodiment

Please refer to FIG. 3, FIG. 4a to FIG. 4e. In this embodiment, the method for manufacturing the SiGe source/drain region is based on the 40nm technology generation, which includes the following steps:

Step S01, as shown in FIG. 4a, provides an N-type wafer silicon substrate 301 formed with a gate 305, and the gate 305 is protected by a SiN sacrificial layer 304. On the silicon substrate 301, the gate 305 and the shallow trench A groove 303 for forming a source/drain region is etched between the groove isolation 302;

Step S02, as shown in FIG. 4b, deposits a metal Al thin film 306 on the wafer through a physical sputtering process at room temperature, with a thickness of

In step S03, as shown in FIG. 4c, a Ge thin film 307 is deposited on the metal thin film by a magnetron sputtering process at room temperature, with a thickness of

Step S04, as shown in Figure 4d, annealing process is performed on the wafer, in the annealing heating environment, through the induction of metal Al, the Ge atoms in the Ge film diffuse to the interface between the metal film and the silicon substrate and combine with Si atoms , forming a SiGe film 308 with a thickness of

In step S05 , as shown in FIG. 4 e , the metal film and the Ge film on the surface are removed by wet etching to expose the gate 305 and form a PMOS source and drain region with SiGe.

Wherein, the annealing process in step S04 of this embodiment adopts a rapid thermal annealing process, the temperature is 400°C, and the annealing time is 30 minutes. In other embodiments, the annealing process can also use laser annealing, and the annealing temperature can be 300-550°C Between, the annealing time of rapid thermal annealing can be between 10-90 minutes, and the annealing time of laser annealing can be between 3-20 minutes. Al is selected as the metal thin film in this embodiment, and in other embodiments, other metals that can form metal-induced crystallization, such as Ni, can be selected. In this embodiment, the metal thin film is deposited by physical sputtering. In other embodiments, the metal thin film can be deposited by chemical vapor deposition, and the deposition temperature can be between 20-300°C. In this embodiment, the Ge thin film is deposited by magnetron sputtering. In other embodiments, the Ge thin film can be deposited by atomic vapor deposition or chemical vapor deposition, and the deposition temperature can be 20-300° C.

In the actual manufacturing process, the thickness of the formed SiGe film is the same as that of the Al film, and the formation of SiGe will consume a certain amount of Ge film. Therefore, in order to ensure the continuity of the growth of the single crystal SiGe film in the PSD region, it is necessary to ensure that the thickness of the Ge film is greater than that of the Al film. Thickness of the film. Preferably, the Ge film thickness is between 1-3 times of the Al film thickness, more preferably, the Ge film thickness is Al film thickness is

On the other hand, the Ge content in SiGe films can be adjusted by changing the annealing conditions. Because as the annealing temperature increases, the diffusion rate of Si atoms in the Al film is faster than that of Ge atoms, and the Ge content in the SiGe film will decrease.

In this embodiment, a mixed reagent of nitric acid and acetic acid is used in the wet etching process to remove the Al and Ge films without damaging the SiN protective layer on the gate surface and the SiO ₂ in the shallow trench isolation. In other embodiments, the reagent can also be other metal films and Ge films that can be removed, but the etching rate of SiN, SiO ₂ and SiGe is less than Reagents, such as sulfuric acid, some organic acids, etc.

Claims (11)

1. a manufacturing method of SiGe source/drain region, is characterized in that, it comprises the following steps: Step S01, providing an N-type wafer silicon substrate formed with a gate, the gate being protected by a sacrificial layer, and etching grooves for forming source/drain regions on the N-type wafer silicon substrate; Step S02, depositing a metal film on the wafer; Step S03, depositing a Ge thin film on the metal thin film; Step S04, performing an annealing process on the wafer, through metal-induced crystallization, the Ge atoms in the Ge film diffuse to the interface between the metal film and the silicon substrate and combine with Si to form a SiGe film; Step S05 , removing the metal thin film and the Ge thin film on the surface by wet etching to expose the gate and form a PMOS source and drain region with SiGe. 2. The method for manufacturing SiGe source/drain regions according to claim 1, characterized in that: the annealing process in step S04 is rapid thermal annealing or laser annealing, the temperature of the rapid thermal annealing is 300-550° C., and the annealing time is 10-90 minutes, the laser annealing temperature is 330-550° C., and the annealing time is 3-20 minutes. 3 . The method for manufacturing SiGe source/drain regions according to claim 2 , wherein the metal thin film in step S02 is made of a metal that can form metal-induced crystallization. 4 . 4. The method for manufacturing the SiGe source/drain region according to claim 3, characterized in that: the metal thin film is made of Al or Ni. 5 . The method for manufacturing SiGe source/drain regions according to claim 4 , wherein the metal thin film is deposited by physical sputtering or chemical vapor deposition, and the deposition temperature is 20-300° C. 6 . 6 . The method for manufacturing SiGe source/drain regions according to claim 2 , characterized in that: step S03 deposits a Ge thin film by atomic vapor deposition, magnetron sputtering or chemical vapor deposition, and the deposition temperature is 20-300° C. 7 . 7. The method for manufacturing SiGe source/drain regions according to claim 6, wherein the thickness of the Ge film is 1-3 times that of the metal film. 8. the manufacture method of SiGe source/drain region according to claim 7 is characterized in that: the thickness of this Ge thin film is The thickness of the metal film is 9. according to the manufacture method of the described SiGe source/drain region according to any one of claim 1 to 8, it is characterized in that: in the step S05, the reagent selected for wet etching is to SiN, SiO ₂ and SiGe etching rate is less than 10. The method for manufacturing SiGe source/drain regions according to claim 9, wherein the reagent is selected from one or more of nitric acid, sulfuric acid or organic acids. 11. The method for manufacturing SiGe source/drain regions according to claim 10, wherein the organic acid is acetic acid.