CN104241141A - Method for manufacturing embedded silicon-germanium strained PMOS (P-channel metal oxide semiconductor) device - Google Patents

Abstract

The invention discloses a method for manufacturing an embedded silicon-germanium strained PMOS device. Before adopting selective epitaxial growth of a strained silicon-germanium alloy stress layer in a PMOS source-drain groove, first epitaxially grows it on a planar semiconductor substrate. A silicon-germanium alloy layer and a single-crystal silicon layer, and then, using the silicon-germanium alloy layer as a substrate, a strained silicon-germanium alloy stress layer is continuously grown on it by a selective epitaxy method, which avoids the subsequent epitaxial growth of strained silicon The direct contact between germanium and the substrate silicon during the germanium alloy stress layer suppresses the formation of defects at the SiGe/Si interface, and while ensuring proper stress is applied to the channel of the PMOS device, it can also suppress the defects existing in the prior art. Due to the junction leakage phenomenon caused by defects at the SiGe/Si interface, the overall electrical performance of the PMOS device is improved, and it is well compatible with existing processes.

Description

A method for fabricating embedded silicon germanium strained PMOS devices

technical field

The invention relates to the technical field of integrated circuits, and more specifically, to a method for manufacturing an embedded silicon-germanium strained PMOS device.

Background technique

As the miniaturization of VLSI feature sizes continues, circuit elements are getting smaller and operating at faster speeds. How to improve the drive current of circuit components is increasingly important.

In the manufacturing technology of CMOS devices, conventionally, P-type Metal Oxide Semiconductor Field Effect (PMOS) transistors and N-type Metal Oxide Semiconductor Field Effect (NMOS) transistors are processed separately. For example, materials with compressive stress are used in the manufacturing process of PMOS devices, while materials with tensile stress are used in NMOS devices to apply appropriate stress to the channel region, thereby increasing the mobility of carriers. Among them, embedded silicon germanium technology (eSiGe) has become the mainstay of PMOS stress engineering by forming a strained silicon germanium alloy (SiGe) stress layer in the source and drain (S/D) regions of PMOS transistors, which can improve the mobility of channel holes. One of the techniques.

However, when embedded silicon germanium technology is required for epitaxial growth and other integration processes, defects can occur at the SiGe/Si interface, especially when the SiGe stress layer has a high atomic percentage of Ge hour. For example, when the embedded silicon germanium technology is applied in the epitaxial growth process, the method in the prior art is to directly deposit the SiGe layer on the Si substrate. Since the Si-Ge chemical bond has a larger lattice constant than the Si-Si chemical bond, a large stress concentration will occur at the SiGe/Si interface, and the grown film has a very high line dislocation density. At the same time, the source-drain (S/D) morphology has a great influence on the application of embedded silicon germanium technology, because the growth mechanism of SiGe thin film in different crystal orientations is different. The crystal orientation of SiGe on the sidewall of the source and drain is (110) crystal orientation, and the bottom of the source and drain is (001) crystal orientation, and the nucleation rate in the (110) crystal orientation direction is greater than that in the (001) crystal orientation direction s speed. Therefore, the flatness of SiGe in the direction of (110) crystal orientation will be relatively rough, resulting in more defects in the entire SiGe film.

These defects will weaken the stress in the channel, thereby affecting the performance of the PMOS transistor. Moreover, these defects will also increase the leakage current of the PN junction between the source-drain region and the N-well or the substrate, thereby further deteriorating the performance of the PMOS transistor.

At present, the main means to control the above defects are to control the content of Ge in SiGe and optimize the epitaxial process. Among them, although reducing the content of Ge can reduce defects, it will also reduce the stress exerted by the formed silicon germanium stress layer on the channel region, so that the effect of improving hole mobility cannot be achieved; and optimizing the epitaxy process can reduce defects. The effect is also very limited.

Therefore, in the existing silicon germanium epitaxial growth technology, while controlling the generation of defects at the SiGe/Si interface, it is impossible to ensure that the stress exerted by the strained silicon germanium alloy stress layer on the channel region of the PMOS device will not be adversely affected. In view of the above reasons, it is urgent to develop a method for fabricating an embedded silicon germanium strained PMOS device structure to solve the above problems.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned defects existing in the prior art, to provide a method for making an embedded silicon-germanium strained PMOS device, to control the generation of defects at the SiGe/Si interface when forming a strained silicon-germanium alloy stress layer, and It is ensured that the stress exerted by the formed strained silicon germanium alloy stress layer on the channel region of the PMOS device is not affected.

To achieve the above object, the technical scheme of the present invention is as follows:

A method for making an embedded silicon-germanium strained PMOS device, characterized in that it comprises:

Step 1: providing a planar semiconductor substrate, on which a silicon germanium alloy layer and a single crystal silicon layer are sequentially formed;

Step 2: forming shallow trench isolations, gates and sidewalls, the shallow trench isolations staying on the semiconductor substrate;

Step 3: forming PMOS source and drain grooves, the source and drain grooves stay in the silicon germanium alloy layer;

Step 4: Continue growing a silicon-germanium alloy layer in the source-drain groove to form a strained silicon-germanium alloy stress layer in the PMOS source-drain region.

Preferably, in step 1, the silicon germanium alloy layer and the single crystal silicon layer are sequentially deposited on the semiconductor substrate by using an epitaxial growth method.

Preferably, in step 1, the concentration of germanium in the silicon-germanium alloy is not greater than 15 atomic percent.

Preferably, in step 1, the thickness of the single crystal silicon layer is 400-700A.

Preferably, in step 3, the PMOS source-drain groove is formed in the single-crystal silicon layer by dry etching until the silicon-germanium alloy layer under the single-crystal silicon layer is exposed.

Preferably, in step 4, a silicon-germanium alloy layer is continuously deposited and grown in the PMOS source-drain groove by using a selective epitaxy method.

Preferably, in step 4, a silicon-germanium alloy layer is continuously deposited and grown in the PMOS source-drain groove by using a selective epitaxial method until the PMOS source-drain groove is filled.

Preferably, in step 4, the reaction gas of the selective epitaxy method is a mixed gas of silicon dichlorohydrogen, germane and hydrogen, and the process temperature is 610-740°C.

It can be seen from the above-mentioned technical scheme that the advantage of the present invention is that a layer of silicon-germanium alloy is epitaxially grown on a planar semiconductor substrate before adopting selective epitaxial growth of the strained silicon-germanium alloy stress layer in the PMOS source-drain groove. layer and single crystal silicon layer, and by controlling the content of germanium in the silicon-germanium alloy layer, the defects caused by the large stress concentration at the SiGe/Si interface and the growth of the silicon-germanium alloy layer in different crystal directions are avoided. The film-forming defects caused by the difference in speed; then, the PMOS source and drain grooves are formed by etching the single crystal silicon layer, and the silicon-germanium alloy layer below is exposed, and the silicon-germanium alloy layer is used as the substrate, on which The selective epitaxy method continues to grow the strained silicon-germanium alloy stress layer, avoiding direct contact between germanium and substrate silicon during the subsequent epitaxial growth of the strained silicon-germanium alloy stress layer, thereby suppressing the formation of defects at the SiGe/Si interface. Therefore, while ensuring proper stress is applied to the channel of the PMOS device, the present invention can suppress the junction leakage phenomenon existing in the prior art due to defects at the SiGe/Si interface, thereby improving the overall electrical performance of the PMOS device . In addition, the method of the present invention is well compatible with existing processes and can provide greater flexibility for process integration.

Description of drawings

Fig. 1 is a flow chart of a method for making an embedded silicon germanium strained PMOS device of the present invention;

2 to 5 are structural schematic diagrams of an embedded silicon germanium strained PMOS device manufactured by applying the manufacturing method of FIG. 1 in an embodiment of the present invention.

Detailed ways

The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

It should be noted that, in the following embodiments, the structure of the embedded silicon germanium strained PMOS device of the present invention is described in detail by using the schematic diagrams of FIGS. 2 to 5 . When describing the embodiments of the present invention in detail, for the convenience of illustration, the schematic diagrams are not drawn according to the general scale, and some parts are enlarged and omitted. Therefore, it should be avoided as a limitation of the present invention.

In this embodiment, please refer to FIG. 1. FIG. 1 is a flow chart of a method for manufacturing an embedded silicon germanium strained PMOS device according to the present invention; meanwhile, please refer to FIGS. It is a structural schematic diagram of an embedded silicon germanium strained PMOS device manufactured by applying the manufacturing method of FIG. 1 in an embodiment of the present invention. The device structures schematically shown in FIGS. 2 to 5 correspond to the manufacturing steps in FIG. 1 , so as to facilitate the understanding of the method of the present invention.

As shown in Fig. 1, the present invention provides a kind of method for making embedded SiGe strain PMOS device, comprising:

As shown in block 1, step 1: provide a planar semiconductor substrate, and sequentially form a silicon germanium alloy layer and a single crystal silicon layer on the semiconductor substrate.

Referring to FIG. 2 , a planar semiconductor substrate 100 is provided, and a silicon germanium alloy (SiGe) layer 101 and a single crystal silicon layer 102 are sequentially deposited on the semiconductor substrate 100 by epitaxial growth method. When depositing the silicon-germanium alloy layer 101, controlling the concentration of germanium in the silicon-germanium alloy to a lower content level not greater than 15 atomic percent can avoid serious lattice damage during the deposition of the silicon-germanium alloy layer 101, and Avoid the release of a large number of dislocations and defects during strain relaxation. At the same time, the silicon-germanium alloy layer 101 is epitaxially grown on the planar semiconductor substrate 100 first, so that the silicon-germanium alloy can be grown uniformly in the same crystal direction, thereby avoiding the need to directly grow the strained silicon-germanium alloy in the PMOS source-drain groove in the prior art When the silicon-germanium alloy layer grows differently in different crystal directions, the film-forming defects are caused. The semiconductor substrate 100 may be a silicon material substrate formed of monocrystalline silicon, polycrystalline silicon or amorphous silicon, or a silicon-on-insulator (SOI) substrate, or may be a substrate of other semiconductor materials or other structures. When depositing the single crystal silicon layer 102, the thickness of the single crystal silicon layer is 400˜700 Å.

As shown in box 2, step 2: forming shallow trench isolation, gate and sidewall, and the shallow trench isolation stays on the semiconductor substrate.

Referring to FIG. 3 , for example, a dry etching method is used to etch from the single crystal silicon layer 102 toward the semiconductor substrate 100 to form shallow trench isolations 103 , and stay on the semiconductor substrate 100 . Then, the gate 105 and the sidewall 104 are formed on the single crystal silicon layer 102 between the shallow trench isolations 103 , which can be realized by adopting a conventionally known manufacturing process.

As shown in block 3, Step 3: forming PMOS source and drain grooves, the source and drain grooves stay in the silicon germanium alloy layer.

Referring to FIG. 4 , the single crystal silicon layer 102 on both sides of the gate 105 is etched to form PMOS source-drain grooves 106 by plasma dry etching method, and stay in the silicon-germanium alloy layer 101 . As preferably, when etching the PMOS source and drain groove 106, when the silicon-germanium alloy layer 101 below the single crystal silicon layer 102 is exposed, the etching of the PMOS source and drain groove 106 can be stopped to avoid excessive etching. The etch causes the bottom of the source-drain groove 106 to open up with the substrate 100 . In order to ensure the depth of the source-drain groove 106, when depositing the single-crystal silicon layer 102, the thickness of the single-crystal silicon layer 102 should be kept at 400˜700 Å. As an example, a single crystal silicon layer 102 of 640A may be formed by deposition, and then source and drain grooves 106 are formed by etching. Stop after etching the depth of 20A (the bottom surface of the source-drain groove 106 shown in the figure is slightly lower than the upper surface of the silicon-germanium alloy layer 101), so that the depth of the PMOS source-drain groove 106 is about 660A.

As shown in box 4, Step 4: continue to grow a silicon-germanium alloy layer in the source-drain groove, so as to form a strained silicon-germanium alloy stress layer in the PMOS source-drain region.

Please refer to FIG. 5 , using a selective epitaxial method, continue to deposit and grow a silicon-germanium alloy layer 107 in the PMOS source-drain groove 106, and fill up the PMOS source-drain groove 106 (the silicon-germanium alloy layer 107 is shown in the figure). The upper surface of the upper surface of the source-drain groove 106 is flush with the opening surface of the source-drain groove 106), so as to form a strained silicon-germanium alloy stress layer in the source-drain region of the PMOS, so as to apply the necessary stress to the channel region. Preferably, the reaction gas during the process is a mixed gas of dichlorosilane (DCS), germane (GeH ₄ ) and hydrogen (H ₂ ), but not limited thereto; the process temperature is 610-740°C. For example, a selective epitaxy method can be used, using a mixed gas of dichlorohydrogen silicon (DCS), germane (GeH ₄ ) and hydrogen (H ₂ ) as a reaction gas, and at a process temperature of 680°C, the deposition and growth can be continued. strained SiGe alloy stress layer 107 .

After the fabrication of the above-mentioned embedded silicon germanium strained PMOS device is completed, other steps of forming the device can be continued. For example, metal silicides, such as NiPt, are formed on the source, drain, and gate to form interlayer dielectrics, etch contact holes and perform copper back-end processes. These process steps can be formed by methods familiar to those skilled in the art, and will not be repeated here.

It should be noted that, in the prior art, since the Si-Ge chemical bond has a larger lattice constant than the Si-Si chemical bond, if the conventional method is used to directly epitaxial on the Si substrate at the bottom of the PMOS source-drain groove Growing a strained SiGe layer will generate a large stress concentration at the SiGe/Si interface, thus forming defects at the interface. The thin film grown in this way has extremely high linear dislocation density and lacks the means to eliminate defects. The defect rate can only be reduced by controlling the content of Ge in SiGe and optimizing the epitaxy process. However, reducing the content of Ge will reduce the stress exerted by the formed silicon germanium stress layer on the channel region, so that the effect of improving hole mobility cannot be achieved; and the effect of optimizing the epitaxial process in reducing defects is also very limited. Moreover, the flatness of the SiGe thin film will be relatively rough, resulting in more defects in the entire SiGe thin film. These defects will weaken the stress in the channel, thereby affecting the performance of the PMOS transistor. Moreover, these defects will also increase the leakage current of the PN junction between the source-drain region and the N-well or the substrate, thereby further deteriorating the performance of the PMOS transistor.

Compared with the prior art, the present invention first epitaxially grows a silicon-germanium alloy layer and a single crystal silicon layer on a planar semiconductor substrate before using the selective epitaxial growth of the strained SiGe layer in the PMOS source and drain regions, and controls the silicon The content of germanium in the germanium alloy layer avoids the defects caused by the large stress concentration at the SiGe/Si interface, and the film-forming defects caused by the different growth rates of the silicon-germanium alloy layer in different crystal directions. Therefore, The silicon-germanium alloy layer is formed uniformly and has few defects; then, the PMOS source-drain groove is formed by etching the single-crystal silicon layer, and the silicon-germanium alloy layer below is exposed. The strained silicon-germanium alloy stress layer is continued to be grown by selective epitaxy, which avoids the direct contact between germanium and substrate silicon during the subsequent epitaxial growth of the strained silicon-germanium alloy stress layer, and only uses the reactive gas to directly grow the strained SiGe alloy layer. The new epitaxy The lattice constant of the Si-Ge chemical bond of the strained SiGe alloy layer is matched with the lattice constant of the Si-Ge chemical bond of the SiGe alloy layer as the substrate, and no misfit dislocations will be generated, thereby suppressing the original dislocation in SiGe/ The phenomenon of defect formation at the Si interface. Moreover, at this time, the new epitaxial strained SiGe alloy layer will preferentially grow uniformly on the flat SiGe alloy layer as the substrate, and the flatness of the entire SiGe film is better, so that the quality of the film is also guaranteed. Therefore, while ensuring proper stress is applied to the channel of the PMOS device, the present invention can suppress the junction leakage phenomenon existing in the prior art due to defects at the SiGe/Si interface, thereby improving the overall electrical performance of the PMOS device . In addition, the method of the present invention is well compatible with existing processes and can provide greater flexibility for process integration.

The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, all equivalent structural changes made by using the description and accompanying drawings of the present invention should be included in the same way. Within the protection scope of the present invention.

Claims (8)

1., for making a method for embedded SiGe strain PMOS device, it is characterized in that, comprise:

Step one: a planar semiconductor substrate is provided, described semiconductor base forms sige alloy layer and monocrystalline silicon layer successively;

Step 2: form shallow trench isolation from, grid and side wall, described shallow trench isolation is from resting on described semiconductor base;

Step 3: form PMOS source and leak groove, described source and drain groove rests on described sige alloy layer;

Step 4: continued growth sige alloy layer in described source and drain groove, to form strained silicon Germanium alloy stress layer at PMOS source drain region.

2. according to claim 1 for make embedded SiGe strain PMOS device method, it is characterized in that, in step one, adopt epitaxial growth method on described semiconductor base successively deposit form described sige alloy layer and described monocrystalline silicon layer.

3. the method for making embedded SiGe strain PMOS device according to claim 1 and 2, it is characterized in that, in step one, in described sige alloy, the concentration of germanium is not more than 15% atomic percentage.

4. the method for making embedded SiGe strain PMOS device according to claim 1 and 2, it is characterized in that, in step one, the thickness of described monocrystalline silicon layer is 400 ~ 700A.

5. the method for making embedded SiGe strain PMOS device according to claim 1, it is characterized in that, in step 3, adopt dry etching method to form described PMOS source at described monocrystalline silicon layer and leak groove, and until expose the described sige alloy layer below described monocrystalline silicon layer.

6. the method for making embedded SiGe strain PMOS device according to claim 1, is characterized in that, in step 4, adopts selective epitaxial method to leak in groove in described PMOS source and continues deposit growth sige alloy layer.

7. the method for making embedded SiGe strain PMOS device according to claim 6, it is characterized in that, in step 4, adopt selective epitaxial method to leak in groove in described PMOS source and continue deposit growth sige alloy layer, until fill up described PMOS source to leak groove.

8. the method for making embedded SiGe strain PMOS device according to claim 6 or 7, it is characterized in that, in step 4, the reacting gas of described selective epitaxial method is the mist of dichloro hydrogen silicon, germane and hydrogen, and technological temperature is 610 ~ 740 DEG C.