CN104752182B - A method of making NiSiGe material using Ti insertion layer - Google Patents
A method of making NiSiGe material using Ti insertion layer Download PDFInfo
- Publication number
- CN104752182B CN104752182B CN201310746120.1A CN201310746120A CN104752182B CN 104752182 B CN104752182 B CN 104752182B CN 201310746120 A CN201310746120 A CN 201310746120A CN 104752182 B CN104752182 B CN 104752182B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- present
- film
- nisi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明提供一种利用Ti插入层制作NiSiGe材料的方法,至少包括以下步骤:1)提供一Si1‑ xGex层,于所述Si1‑xGex层表面形成Ti金属薄膜,其中,0.05≤x≤0.9;2)于所述Ti掺入层表面形成Ni金属层;3)采用快速退火工艺使所述Ni金属穿过所述Ti金属薄膜与所述Si1‑xGex层反应生成NiSi1‑xGex层,其中,0.05≤x≤0.9。本发明具有以下有益效果:由于特定温度可以提供Ni与Si1‑ xGex层反应所需的热激活能,并使只有极少量的Ti与Si1‑xGex反应并保持在Si1‑xGex层与NiSi1‑ xGex层的界面处,产生几个原子层的缺陷聚集区,隔断了表层薄膜应力的释放向底层的传递,同时使Ni与Si1‑xGex的反应以较缓慢的速度进行。因此,本发明对于保持Si1‑xGex的应变起到了一定的作用,可以获得连续、均一、稳定的NiSiGe材料。
The present invention provides a method for making NiSiGe material by using a Ti insertion layer, which at least includes the following steps: 1) providing a Si 1- x Ge x layer, and forming a Ti metal film on the surface of the Si 1-x Ge x layer, wherein, 0.05≤x≤0.9; 2) forming a Ni metal layer on the surface of the Ti-doped layer; 3) using a rapid annealing process to make the Ni metal pass through the Ti metal thin film to react with the Si 1-x Ge x layer A NiSi 1-x Ge x layer is generated, where 0.05≤x≤0.9. The present invention has the following beneficial effects: due to the specific temperature, the thermal activation energy required for the reaction of Ni with the Si 1- x Ge x layer can be provided, and only a very small amount of Ti can react with the Si 1-x Ge x and be kept at the Si 1 -x Ge x level. At the interface between the x Ge x layer and the NiSi 1‑ x Ge x layer, several atomic layers of defect accumulation areas are generated, which block the release of the surface film stress from the transfer to the bottom layer, and at the same time enable the reaction between Ni and Si 1‑x Ge x . Do it at a slower pace. Therefore, the present invention plays a certain role in maintaining the strain of Si 1-x Ge x , and a continuous, uniform and stable NiSiGe material can be obtained.
Description
技术领域technical field
本发明涉及一种半导体器件的制作方法,特别是涉及一种利用Ti插入层制作NiSiGe材料的方法。The present invention relates to a method for fabricating a semiconductor device, in particular to a method for fabricating NiSiGe material using a Ti insertion layer.
背景技术Background technique
传统晶体管的源漏区域,其电极一般采用半导体和金属电极之间直接接触,接触电阻很大,形成的肖特基势垒很高,从而影响了器件的性能。因此,人们不停地寻找一种能够降低电极接触电阻的方法,其中,一种效果良好的结构基本完全取代了半导体和金属电极直接接触的技术,这种效果良好的结构是采用金属和Si材料反应生成金属硅化物来作为接触材料,从而可以大幅度降低接触电阻和肖特基势垒,并得到了广泛的应用。后来,金属硅化物的金属元素历经了从Ti到Co,再到Ni的发展过程。并且Ni的硅化物凭借其优异的的性能及良好的加工工艺获得了广泛的应用。目前在Intel和AMD等厂家生产的MOSFET晶体管源漏区域,都采用了NiSi作为接触材料。In the source and drain regions of traditional transistors, the electrodes generally use direct contact between semiconductor and metal electrodes, and the contact resistance is large, resulting in a high Schottky barrier, which affects the performance of the device. Therefore, people are constantly looking for a method that can reduce the contact resistance of electrodes, in which a structure with good effect basically completely replaces the technology of direct contact between semiconductor and metal electrodes. This structure with good effect is made of metal and Si materials. The reaction generates metal silicide as a contact material, which can greatly reduce the contact resistance and Schottky barrier, and has been widely used. Later, the metal elements of metal silicides went through the development process from Ti to Co, and then to Ni. And Ni silicide has been widely used due to its excellent performance and good processing technology. At present, NiSi is used as the contact material in the source and drain regions of MOSFET transistors produced by manufacturers such as Intel and AMD.
随着半导体材料及工艺的进步,Si1-xGex作为一种新型的高迁移率材料,是未来Si材料的重要补充。然而,在Ni和Si1-xGex发生合金化反应的时候,由于Ge与Si、Ge会生成反应热不同的硅化物和锗化物,易造成Ni和Si、Ge原子的反应次序不一致,不容易形成连续、均一、稳定的NiSi1-xGex薄膜。此外,由于Ge的析出扩散,产生过量的晶界最终导致形成的NiSi1-xGex薄膜电学性能不好,很大程度上影响了NiSi1-xGex薄膜作为源漏接触的应用。With the advancement of semiconductor materials and processes, Si 1-x Ge x , as a new type of high mobility material, is an important supplement to Si materials in the future. However, when Ni and Si 1-x Ge x undergo an alloying reaction, since Ge and Si and Ge will generate silicides and germanides with different reaction heats, it is easy to cause inconsistent reaction sequences of Ni, Si, and Ge atoms. It is easy to form continuous, uniform and stable NiSi 1-x Ge x thin films. In addition, due to the precipitation and diffusion of Ge, excessive grain boundaries eventually lead to poor electrical properties of the formed NiSi 1-x Ge x film, which largely affects the application of the NiSi 1-x Ge x film as a source-drain contact.
鉴于以上缺点,本发明的目的在于提供一种制作连续、均一、稳定的Ni Si1-xGex材料的方法。In view of the above shortcomings, the purpose of the present invention is to provide a method for producing continuous, uniform and stable Ni Si 1-x Ge x materials.
发明内容SUMMARY OF THE INVENTION
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种利用Ti插入层制作NiSiGe材料的方法,用于解决现有技术中不容易形成连续、均一、稳定的Ni(Si1-xGex)材料的问题。In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for making NiSiGe materials by using a Ti insertion layer, which is used to solve the problem that it is not easy to form continuous, uniform and stable Ni(Si 1-x ) in the prior art. Ge x ) material problem.
为实现上述目的及其他相关目的,本发明提供一种利用Ti插入层制作NiSiGe材料的方法,至少包括以下步骤:In order to achieve the above-mentioned purpose and other related purposes, the present invention provides a method for making NiSiGe material by utilizing Ti insertion layer, which at least comprises the following steps:
1)提供一Si1-xGex层,于所述Si1-xGex层表面形成Ti金属薄膜,其中,0.05≤x≤0.9;1) Provide a Si 1-x Ge x layer, and form a Ti metal film on the surface of the Si 1-x Ge x layer, wherein 0.05≤x≤0.9;
2)于所述Ti金属薄膜表面形成Ni金属层;2) forming a Ni metal layer on the surface of the Ti metal film;
3)采用快速退火工艺使所述Ni金属穿过所述Ti金属薄膜与所述Si1-xGex层反应生成NiSi1-xGex层,其中,0.05≤x≤0.9。3) Using a rapid annealing process, the Ni metal passes through the Ti metal thin film and reacts with the Si 1-x Ge x layer to form a NiSi 1-x Ge x layer, where 0.05≤x≤0.9.
作为本发明的利用Ti插入层制作NiSiGe材料的方法的一种优选方案,步骤3)的反应过程中,于所述NiSi1-xGex层表面还会形成TiNiSi1-xGex层及非晶薄膜,其中,0.05≤x≤0.9。As a preferred solution of the method for producing a NiSiGe material using a Ti insertion layer of the present invention, in the reaction process of step 3), a TiNiSi 1-x Ge x layer and a non-ferrous oxide layer will also be formed on the surface of the NiSi 1-x Ge x layer. crystalline thin film, wherein, 0.05≤x≤0.9.
进一步地,该方法还包括步骤:采用选择性腐蚀工艺去除所述非晶薄膜。Further, the method further includes the step of: removing the amorphous thin film by a selective etching process.
作为本发明的利用Ti插入层制作NiSiGe材料的方法的一种优选方案,所述快速退火工艺的退火温度范围为300~800℃。As a preferred solution of the method for producing NiSiGe material by using a Ti insertion layer of the present invention, the annealing temperature range of the rapid annealing process is 300-800°C.
作为本发明的利用Ti插入层制作NiSiGe材料的方法的一种优选方案,所述快速退火工艺的退火时间范围为30~120s。As a preferred solution of the method for producing NiSiGe material by using the Ti insertion layer of the present invention, the annealing time of the rapid annealing process ranges from 30 to 120 s.
作为本发明的利用Ti插入层制作NiSiGe材料的方法的一种优选方案,所述Ti金属薄膜的厚度为1~5nm。As a preferred solution of the method for producing a NiSiGe material using a Ti insertion layer of the present invention, the thickness of the Ti metal thin film is 1-5 nm.
作为本发明的利用Ti插入层制作NiSiGe材料的方法的一种优选方案,所述Ni金属层的厚度为5~100nm。As a preferred solution of the method for producing a NiSiGe material by using a Ti insertion layer of the present invention, the thickness of the Ni metal layer is 5-100 nm.
作为本发明的利用Ti插入层制作NiSiGe材料的方法的一种优选方案,采用蒸镀工艺或溅射工艺形成所述Ti金属薄膜及Ni金属层。As a preferred solution of the method for producing a NiSiGe material using a Ti insertion layer of the present invention, the Ti metal thin film and the Ni metal layer are formed by an evaporation process or a sputtering process.
作为本发明的利用Ti插入层制作NiSiGe材料的方法的一种优选方案,所述Si1- xGex层外延于硅衬底表面。As a preferred solution of the method for producing NiSiGe material by using the Ti insertion layer of the present invention, the Si 1- x Ge x layer is epitaxially formed on the surface of the silicon substrate.
如上所述,本发明提供一种利用Ti插入层制作NiSiGe材料的方法,至少包括以下步骤:1)提供一Si1-xGex层,于所述Si1-xGex层表面形成Ti金属薄膜,其中,0.05≤x≤0.9;2)于所述Ti掺入层表面形成Ni金属层;3)采用快速退火工艺使所述Ni金属穿过所述Ti金属薄膜与所述Si1-xGex层反应生成NiSi1-xGex层,其中,0.05≤x≤0.9。本发明具有以下有益效果:由于特定温度可以提供Ni与Si1-xGex层反应所需的热激活能,并使只有极少量的Ti与Si1- xGex反应并保持在Si1-xGex层与NiSi1-xGex层的界面处,产生几个原子层的缺陷聚集区,隔断了表层薄膜应力的释放向底层的传递,同时使Ni与Si1-xGex的反应以较缓慢的速度进行。因此,本发明对于保持Si1-xGex的应变起到了一定的作用,可以获得连续、均一、稳定的NiSiGe材料。As described above, the present invention provides a method for making NiSiGe material using a Ti insertion layer, which at least includes the following steps: 1) providing a Si 1-x Ge x layer, and forming Ti metal on the surface of the Si 1-x Ge x layer film, wherein, 0.05≤x≤0.9; 2) a Ni metal layer is formed on the surface of the Ti-doped layer; 3) a rapid annealing process is used to make the Ni metal pass through the Ti metal film and the Si 1-x The Ge x layer reacts to form a NiSi 1-x Ge x layer, where 0.05≤x≤0.9. The present invention has the following beneficial effects: due to the specific temperature, the thermal activation energy required for the reaction of Ni with the Si 1-x Ge x layer can be provided, and only a very small amount of Ti can react with the Si 1- x Ge x and remain at the Si 1- x Ge x . At the interface between the x Ge x layer and the NiSi 1-x Ge x layer, several atomic layers of defect accumulation areas are generated, which block the release of the surface film stress and transfer to the bottom layer, and at the same time make the reaction between Ni and Si 1-x Ge x . Do it at a slower pace. Therefore, the present invention plays a certain role in maintaining the strain of Si 1-x Ge x , and can obtain a continuous, uniform and stable NiSiGe material.
附图说明Description of drawings
图1~图2显示为本发明的利用Ti插入层制作NiSiGe材料的方法中的步骤1)所呈现的结构示意图。1 to 2 are schematic structural diagrams presented in step 1) of the method for fabricating a NiSiGe material by using a Ti insertion layer of the present invention.
图3显示为本发明的利用Ti插入层制作NiSiGe材料的方法中的步骤2)所呈现的结构示意图。FIG. 3 shows a schematic structural diagram of step 2) of the method for fabricating NiSiGe material by using a Ti insertion layer of the present invention.
图4~图5显示为本发明的利用Ti插入层制作NiSiGe材料的方法中的步骤3)所呈现的结构示意图。4 to 5 are schematic structural diagrams presented in step 3) of the method for fabricating NiSiGe material by using a Ti insertion layer of the present invention.
元件标号说明Component label description
101 硅衬底101 Silicon substrate
102 Si1-xGex层102 Si 1-x Ge x layer
103 Ti金属薄膜103 Ti metal film
104 Ni金属层104 Ni metal layer
105 NiSi1-xGex层105 NiSi 1-x Ge x layer
106 TiNiSi1-xGex层106 TiNiSi 1-x Ge x layer
107 非晶薄膜107 Amorphous thin film
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1~图5。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。Please refer to Figure 1 to Figure 5. It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, and the drawings only show the components related to the present invention rather than the number, shape and number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complicated.
如图1~图5所示,本实施例提供一种利用Ti插入层制作NiSiGe材料的方法,至少包括以下步骤:As shown in FIG. 1 to FIG. 5 , this embodiment provides a method for fabricating NiSiGe material by using a Ti insertion layer, which at least includes the following steps:
如图1~图2所示,首先进行步骤1),提供一Si1-xGex层102,于所述Si1-xGex层102表面形成Ti金属薄膜103,其中,0.05≤x≤0.9。As shown in FIGS. 1 to 2 , step 1) is first performed, a Si 1-x Ge x layer 102 is provided, and a
作为示例,首先提供一硅衬底101,采用外延工艺于所述硅衬底101表面形成具有应力的Si1-xGex层102,接着采用蒸镀工艺或溅射工艺于所述Si1-xGex层102表面形成Ti金属薄膜103,在本实施例中,所述Ti金属薄膜103的厚度为1~5nm。As an example, a
如图3所示,然后进行步骤2),于所述Ti金属薄膜103表面形成Ni金属层104。As shown in FIG. 3 , then step 2) is performed to form a
作为示例,采用蒸镀工艺或溅射工艺于所述Ti金属薄膜103表面形成Ni金属层104,所述Ni金属层104的厚度为5~100nm。As an example, a
如图4所示,最后进行步骤3),采用快速退火工艺使所述Ni金属穿过所述Ti金属薄膜103与所述Si1-xGex层102反应生成NiSi1-xGex层105,其中,0.05≤x≤0.9。As shown in FIG. 4 , step 3) is finally performed, and a rapid annealing process is used to make the Ni metal pass through the
作为示例,于300~800℃的温度下对上述结构进行快速退火,所述快速退火的退火时间为30s~120s,使所述Ni金属穿过所述Ti金属薄膜103与所述Si1-xGex层反应生成NiSi1-xGex层105,其中,0.05≤x≤0.9。具体过程为,在快速退火的过程中,由于温度为300~800℃,足以提供Ni与Si1-xGex层的反应所需的热激活能,而尚未达到Ti与Si1-xGex层的反应所需的热激活能,因此,只有极少量的Ti会与Si1-xGex层反应,而且所述Ti金属薄膜103厚度较小,Ni金属可以穿过该Ti金属薄膜103与所述Si1-xGex层反应生成NiSi1-xGex层105,且反应速度相对较缓慢,最终获得可以获得连续、均一、稳定的NiSiGe材料。As an example, the above structure is subjected to rapid annealing at a temperature of 300-800°C, and the annealing time of the rapid annealing is 30s-120s, so that the Ni metal passes through the
另外,如图4所示,步骤3)的反应过程中,于所述NiSi1-xGex层105表面可能还会形成TiNiSi1-xGex层106(0.05≤x≤0.9)及非晶薄膜107,甚至还会有少量的Ti金属薄膜103残留,所述TiNiSi1-xGex层106及少量的Ti金属薄膜103对NiSiGe材料的性能影响较少,可以保留,也可以通过选择性腐蚀工艺去除,而所述非晶薄膜107对NiSiGe材料的性能影响较大,故在本实施例中,还包括采用选择性腐蚀工艺将所述非晶薄膜107去除的步骤,如图5所示。In addition, as shown in FIG. 4 , in the reaction process of step 3), a TiNiSi 1-x Ge x layer 106 (0.05≤x≤0.9) and an amorphous layer may also be formed on the surface of the NiSi 1-x Ge x layer 105 The
在一个具体的应用过程中,所述Si1-xGex层102为Si0.95Ge0.05层,所述Ti金属薄膜103的厚度为1nm,所述Ni金属层104的厚度为5nm,所采用的退火温度为300℃,退火时间为30s,以获得性能良好的NiSi0.95Ge0.05材料。In a specific application process, the Si 1-x Ge x layer 102 is a Si 0.95 Ge 0.05 layer, the thickness of the
在另一具体的应用过程中,所述Si1-xGex层102为Si0.5Ge0.5层,所述Ti金属薄膜103的厚度为3nm,所述Ni金属层104的厚度为50nm,所采用的退火温度为600℃,退火时间为60s,以获得性能良好的NiSi0.5Ge0.5材料。In another specific application process, the Si 1-x Ge x layer 102 is a Si 0.5 Ge 0.5 layer, the thickness of the
在另一具体的应用过程中,所述Si1-xGex层102为Si0.1Ge0.9层,所述Ti金属薄膜103的厚度为5nm,所述Ni金属层104的厚度为100nm,所采用的退火温度为800℃,退火时间为120s,以获得性能良好的NiSi0.1Ge0.9材料。In another specific application process, the Si 1-x Ge x layer 102 is a Si 0.1 Ge 0.9 layer, the thickness of the
如上所述,本发明提供一种利用Ti插入层制作NiSiGe材料的方法,至少包括以下步骤:1)提供一Si1-xGex层,于所述Si1-xGex层表面形成Ti金属薄膜103,其中,0.05≤x≤0.9;2)于所述Ti掺入层表面形成Ni金属层104;3)采用快速退火工艺使所述Ni金属穿过所述Ti金属薄膜103与所述Si1-xGex层102反应生成NiSi1-xGex层105,其中,0.05≤x≤0.9。本发明具有以下有益效果:由于特定温度可以提供Ni与Si1-xGex层反应所需的热激活能,并使只有极少量的Ti与Si1-xGex反应并保持在Si1-xGex层与NiSi1-xGex层的界面处,产生几个原子层的缺陷聚集区,隔断了表层薄膜应力的释放向底层的传递,同时使Ni与Si1-xGex的反应以较缓慢的速度进行。因此,本发明对于保持Si1-xGex的应变起到了一定的作用,可以获得连续、均一、稳定的NiSiGe材料。所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。As described above, the present invention provides a method for making NiSiGe material using a Ti insertion layer, which at least includes the following steps: 1) providing a Si 1-x Ge x layer, and forming Ti metal on the surface of the Si 1-x Ge x layer film 103, wherein, 0.05≤x≤0.9; 2) forming a
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310746120.1A CN104752182B (en) | 2013-12-30 | 2013-12-30 | A method of making NiSiGe material using Ti insertion layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310746120.1A CN104752182B (en) | 2013-12-30 | 2013-12-30 | A method of making NiSiGe material using Ti insertion layer |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104752182A CN104752182A (en) | 2015-07-01 |
CN104752182B true CN104752182B (en) | 2020-01-07 |
Family
ID=53591697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310746120.1A Active CN104752182B (en) | 2013-12-30 | 2013-12-30 | A method of making NiSiGe material using Ti insertion layer |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104752182B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105551938B (en) * | 2015-12-22 | 2018-11-27 | 上海工程技术大学 | A method of making NiGeSn material |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102468124A (en) * | 2010-11-04 | 2012-05-23 | 中国科学院上海微系统与信息技术研究所 | Method for epitaxially growing NiSiGe material by using Al insertion layer |
US8580686B1 (en) * | 2012-04-23 | 2013-11-12 | Globalfoundries Inc. | Silicidation and/or germanidation on SiGe or Ge by cosputtering Ni and Ge and using an intralayer for thermal stability |
CN104254905A (en) * | 2012-02-27 | 2014-12-31 | 于利奇研究中心有限公司 | Method for producing a monocrystalline metal/semiconductor compound |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7205234B2 (en) * | 2004-02-05 | 2007-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming metal silicide |
JP3879003B2 (en) * | 2004-02-26 | 2007-02-07 | 国立大学法人名古屋大学 | Method for producing silicide film |
-
2013
- 2013-12-30 CN CN201310746120.1A patent/CN104752182B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102468124A (en) * | 2010-11-04 | 2012-05-23 | 中国科学院上海微系统与信息技术研究所 | Method for epitaxially growing NiSiGe material by using Al insertion layer |
CN104254905A (en) * | 2012-02-27 | 2014-12-31 | 于利奇研究中心有限公司 | Method for producing a monocrystalline metal/semiconductor compound |
US8580686B1 (en) * | 2012-04-23 | 2013-11-12 | Globalfoundries Inc. | Silicidation and/or germanidation on SiGe or Ge by cosputtering Ni and Ge and using an intralayer for thermal stability |
Non-Patent Citations (1)
Title |
---|
Formation of ternary Ni-silicide on relaxed and strained SiGe layers;Q.T. Zhao et.al;《Microelectronic Engineering》;20040814;第76卷(第1-4期);摘要及实验部分 * |
Also Published As
Publication number | Publication date |
---|---|
CN104752182A (en) | 2015-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Shen et al. | The trend of 2D transistors toward integrated circuits: scaling down and new mechanisms | |
Toko et al. | High-hole mobility polycrystalline Ge on an insulator formed by controlling precursor atomic density for solid-phase crystallization | |
CN103208425B (en) | A kind of manufacture method of high-K metal gate Ge base MOS device of Graphene modulation | |
Wang et al. | Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method | |
CN102683217B (en) | A kind of preparation method of the double grids MOSFET based on Graphene | |
CN109727846B (en) | Method and application of large-area preparation of two-dimensional molybdenum telluride in-plane heterojunction in which metal phase is in contact with semiconductor | |
TW202016985A (en) | Method of forming two-dimensional material layer, field effect transistor and fabricating method thereof | |
US9741568B2 (en) | Sulfur doping method for graphene | |
CN103943512B (en) | A kind of method reducing Graphene and Electrodes | |
JP2009076753A5 (en) | ||
JP2020520119A (en) | Method for manufacturing TFT substrate | |
Yuan et al. | Stacking transfer of wafer-scale graphene-based van der Waals superlattices | |
CN103903973A (en) | Method for developing high K medium on graphene through spin coating of liquid metal seed layer | |
CN104752182B (en) | A method of making NiSiGe material using Ti insertion layer | |
CN102468123B (en) | Method for growing NiSiGe material by utilizing NiAl alloy epitaxy | |
CN107768432A (en) | A kind of two-dimentional molybdenum disulfide bottom gate type TFT device architectures and preparation method thereof | |
CN104064448A (en) | Manufacturing method of SiGe source/drain region | |
CN105448690B (en) | A method of being inserted into layer epitaxially grown metal/semiconductor material using graphene | |
WO2012058947A1 (en) | EPITAXIAL GROWTH METHOD FOR NiSiGe USING INSERTED Al LAYER | |
CN103915326B (en) | The forming method and semiconductor devices of self-aligned metal silicate | |
Hsu et al. | Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate | |
CN104392915B (en) | Method for epitaxial growth of NiGe material by using NiTi alloy | |
CN103489787B (en) | Improve the method for source and drain contact and silicon nitride film adhesive force | |
CN113707560A (en) | Method for improving electrical contact of two-dimensional transition metal chalcogenide by inserting two-dimensional semiconductor indium selenide nanosheets | |
CN104409321B (en) | Method utilizing NiTi alloy for epitaxial growth NiSiGe material |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |