CN103959189B - 基于电感的并行放大器相位补偿 - Google Patents
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- H02M3/00—Conversion of DC power input into DC power output
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- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H02M1/00—Details of apparatus for conversion
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02M1/00—Details of apparatus for conversion
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Abstract
公开一种直流(DC)-DC转换器,其包括并行放大器和开关电源。所述开关电源包括开关电路、第一电感元件以及第二电感元件。所述并行放大器有反馈输入和并行放大器输出。所述开关电路具有开关电路输出。所述第一电感元件耦接在所述开关电路输出与所述反馈输入之间。所述第二电感元件耦接在所述反馈输入与所述并行放大器输出之间。
Description
相关申请
本申请是要求于2011年10月26日提交的美国临时专利申请第61/551,596号和于2011年11月22日提交的美国临时专利申请第61/562,493号的权益,上述申请以其全文引入本文作为参考。
技术领域
本发明是涉及直流(DC)-DC转换器和使用DC-DC转换器的电路。
发明背景
DC-DC转换器通常包括开关电源,所述开关电源可以基于开关介于DC电压源与接地之间的能量存储元件(如电感器)中的至少一端。因此,来自DC-DC转换器的输出电压可以具有因与能量存储元件关联的开关引起的纹波电压。通常,纹波电压不是所期望的,并且在大小和成本允许的情况下尽可能地最小化。因此,需要使用最小化大小和成本的技术来最小化纹波电压。
发明概述
本发明的实施方案涉及一种直流(DC)-DC转换器,其包括并行放大器和开关电源。开关电源包括开关电路、第一电感元件以及第二电感元件。并行放大器有反馈输入和并行放大器输出。开关电路具有开关电路输出。第一电感元件耦接在开关电路输出与反馈输入之间。第二电感元件耦接在反馈输入与并行放大器输出之间。
在DC-DC转换器的一个实施方案中,并行放大器基于电压设定值经由并行放大器输出来部分提供第一电源输出信号。开关电源经由第一电感元件和第二电感元件来部分提供第一电源输出信号。比起并行放大器,开关电源可以更有效地提供电力。然而,比起开关电源,并行放大器可以更准确地提供第一电源输出信号的电压。因此,在DC-DC转换器的一个实施方案中,并行放大器基于第一电源输出信号的电压设定值来调节第一电源输出信号的电压。另外,开关电源调节第一电源输出信号以最小化来自并行放大器的输出电流,从而最大化效率。就此而言,并行放大器的行为类似电压源,并且开关电源的行为类似电流源。
在开关电源的一个实施方案中,连接节点被提供在第一电感元件与第二电感元件彼此连接的地方。连接节点将电压提供给反馈输入。另外,在并行放大器的一个实施方案中,并行放大器在高于频率阈值的频率下具有有限开环增益。在此类频率下,并行放大器中的群延迟可能通常限制并行放大器的准确调节第一电源输出信号的电压的能力。然而,通过将来自连接节点的电压而不是来自第一电源输出信号的电压反馈到反馈输入,第二电感元件上形成的相移至少部分补偿并行放大器在高于频率阈值的频率下的有限开环增益,从而改进并行放大器的准确调节第一电源输出信号的电压的能力。
在结合附图阅读以下详细说明后,本领域的技术人员将会了解本发明的范围并意识到其另外的方面。
附图简述
并入本说明书并且形成本说明书的一部分的附图示出本公开的若干方面,并与描述一起用于解释本公开的原理。
图1示出根据本公开的一个实施方案的直流(DC)-DC转换器。
图2示出根据DC-DC转换器的替代实施方案的DC-DC转换器。
图3示出根据本公开的一个实施方案的射频(RF)通信系统。
图4示出根据RF通信系统的替代实施方案的RF通信系统。
图5示出根据RF通信系统的附加实施方案的RF通信系统。
图6示出根据RF通信系统的另一实施方案的RF通信系统。
具体实施方式
下文所阐述的实施方案呈现使得本领域的技术人员能够实践本发明的必要信息并且示出实践本发明的最佳模式。在结合附图阅读以下说明后,本领域的技术人员将会理解本公开的概念并且将认识到这些概念的未在本文具体描述的应用。应当理解,这些概念和应用都在本公开和所附权利要求书的范围内。
图1示出根据本公开的一个实施方案的直流(DC)-DC转换器10。DC-DC转换器10包括开关电源12和并行放大器14。开关电源12包括开关电路16、第一电感元件L1以及第二电感元件L2。并行放大器14具有反馈输入FBI和并行放大器输出PAO。开关电路16具有开关电路输出SCO。第一电感元件L1耦接在开关电路输出SCO与反馈输入FBI之间。第二电感元件L2耦接在反馈输入FBI与并行放大器输出PAO之间。
在DC-DC转换器10的一个实施方案中,并行放大器14基于电压设定值经由并行放大器输出PAO来部分提供第一电源输出信号PS1。开关电源12经由第一电感元件L1和第二电感元件L2来部分提供第一电源输出信号PS1。确切地说,开关电源12经由第一电感元件L1和第二电感元件L2的串联组合来部分提供第一电源输出信号PS1。比起并行放大器14,开关电源12可以更有效地提供电力。然而,比起开关电源12,并行放大器14可以更准确地提供第一电源输出信号PS1的电压。因此,在DC-DC转换器10的一个实施方案中,并行放大器14基于第一电源输出信号PS1的电压设定值来调节第一电源输出信号PS1的电压(称作第一电压V1)。另外,开关电源12调节第一电源输出信号PS1来最小化来自并行放大器14的输出电流(称作并行放大器输出电流IP)以最大化效率。就此而言,并行放大器14的行为类似电压源,并且开关电源12的行为类似电流源。另外,开关电路16经由开关电路输出SCO将开关输出电压VS和电感器电流IL提供给第一电感元件L1。
在开关电源12的一个实施方案中,连接节点18被提供在第一电感元件L1与第二电感元件L2彼此连接的地方。连接节点18经由反馈输入FBI将第二电压V2提供给并行放大器14。另外,在并行放大器14的一个实施方案中,并行放大器14在高于频率阈值的频率下具有有限开环增益。在此类频率下,并行放大器14中的群延迟可能通常限制并行放大器14的准确调节第一电源输出信号PS1的第一电压V1的能力。然而,通过将第二电压V2而不是第一电压V1反馈到反馈输入FBI,跨第二电感元件L2形成的相移至少部分补偿并行放大器14在高于频率阈值的频率下的有限开环增益,从而改进并行放大器14的准确调节第一电压V1的能力。就此而言,在DC-DC转换器10的一个实施方案中,并行放大器14基于电压设定值经由并行放大器输出PAO来部分提供第一电源输出信号PS1,并从第一电感元件L1与第二电感元件L2之间的连接节点18将电压反馈到反馈输入FBI。
在DC-DC转换器10的一个实施方案中,DC-DC转换器10接收DC电源信号VDC,使得并行放大器14使用DC电源信号VDC来部分提供第一电源输出信号PS1,并且开关电源12使用DC电源信号VDC来部分提供第一电源输出信号PS1。
图2示出根据DC-DC转换器10的替代实施方案的DC-DC转换器10。图2中所示DC-DC转换器10类似于图1中所示DC-DC转换器10,除了图2所示DC-DC转换器10进一步包括电源控制电路20和偏移电容元件CO。另外,开关电源12进一步包括滤波电容元件CF。电源控制电路20接收DC电源信号VDC并耦接到并行放大器14和开关电路16。第一电感元件L1和第二电感元件L2经由连接节点18提供第二电源输出信号PS2。
偏移电容元件CO耦接在并行放大器输出PAO与第二电感元件L2之间,使得并行放大器14基于电压设定值经由并行放大器输出PAO和偏移电容元件CO来部分提供第一电源输出信号PS1。偏移电容元件CO允许第一电压V1高于并行放大器输出PAO处的电压。因此,即使第一电压V1大于并行放大器输出PAO处的来自并行放大器14的最大输出电压,并行放大器14也可适当调节第一电压V1。
通常,滤波电容元件CF耦接在并行放大器输出PAO与接地之间。在图2所示DC-DC转换器10的一个实施方案中,滤波电容元件CF通过偏移电容元件CO耦接在并行放大器输出PAO与接地之间。在DC-DC转换器10的替代实施方案中,省略偏移电容元件CO,使得滤波电容元件CF直接耦接在并行放大器输出PAO与接地之间。第一电感元件L1、第二电感元件L2以及滤波电容元件CF形成具有第一截止频率的第一低通滤波器22。第二电感元件L2和滤波电容元件CF形成具有第二截止频率的第二低通滤波器24。第二截止频率可以,明显高于第一截止频率。因此,第一低通滤波器22可以主要用来滤波通常是方波的开关输出电压VS。然而,第二低通滤波器24可以用于靶向特定高的频率,如开关输出电压VS的某些谐波。
在第一低通滤波器22和第二低通滤波器24的第一实施方案中,第二截止频率是第一截止频率的至少10倍。在第一低通滤波器22和第二低通滤波器24的第二实施方案中,第二截止频率是第一截止频率的至少100倍。在第一低通滤波器22和第二低通滤波器24的第三实施方案中,第二截止频率是第一截止频率的至少500倍。在第一低通滤波器22和第二低通滤波器24的第四实施方案中,第二截止频率是第一截止频率的至少1000倍。在第一低通滤波器22和第二低通滤波器24的第五实施方案中,第二截止频率是第一截止频率的不到1000倍。在第一低通滤波器22和第二低通滤波器24的第六实施方案中,第二截止频率是第一截止频率的不到5000倍。
第一电感元件L1具有第一电感,并且第二电感元件L2具有第二电感。在第一电感元件L1和第二电感元件L2的第一实施方案中,第一电感的量值是第二电感的量值的至少10倍。在第一电感元件L1和第二电感元件L2的第二实施方案中,第一电感的量值是第二电感的量值的至少100倍。在第一电感元件L1和第二电感元件L2的第三实施方案中,第一电感的量值是第二电感的量值的至少500倍。在第一电感元件L1和第二电感元件L2的第四施方案中,第一电感的量值是第二电感的量值的至少1000倍。在第一电感元件L1和第二电感元件L2的第五施方案中,第一电感的量值是第二电感的量值的不到1000倍。在第一电感元件L1和第二电感元件L2的第六施方案中,第一电感的量值是第二电感的量值的不到5000倍。
图3示出根据本公开的一个实施方案的射频(RF)通信系统26。RF通信系统26包括RF发射器电路28、RF系统控制电路30、RF前端电路32、RF天线34以及DC电源36。RF发射器电路28包括发射器控制电路38、RF功率放大器(PA)40、DC-DC转换器10以及PA偏置电路42。DC-DC转换器10起包络跟踪电源的作用。在RF通信系统26的替代实施方案中,DC电源36在RF通信系统26外部。
在RF通信系统26的一个实施方案中,RF前端电路32经由RF天线34接收RF接收信号RFR、对其进行处理并将其转发到RF系统控制电路30。RF系统控制电路30将电源控制信号VRMP和发射器配置信号PACS提供给发射器控制电路38。RF系统控制电路30将RF输入信号RFI提供给RFPA40。DC电源36将DC电源信号VDC提供给DC-DC转换器10。在DC电源36的一个实施方案中,DC电源36是电池。在电源控制信号VRMP的一个实施方案中,电源控制信号VRMP是包络电源控制信号。
发射器控制电路38耦接到DC-DC转换器10和PA偏置电路42。DC-DC转换器10基于电源控制信号VRMP将第一电源输出信号PS1提供给RFPA40。因此,第一电源输出信号PS1是第一包络电源信号。DC电源信号VDC将功率提供给DC-DC转换器10。因此,第一电源输出信号PS1基于DC电源信号VDC。电源控制信号VRMP表示第一电源输出信号PS1的电压设定值。因此,电压设定值基于电源控制信号VRMP。RFPA40接收并且放大RF输入信号RFI,以使用第一包络电源信号(其为第一电源输出信号PS1)提供RF发射信号RFT。第一包络电源信号将用于放大的功率提供到RFPA40。RF前端电路32经由RF天线34接收、处理并且发射RF发射信号RFT。在RF发射器电路28的一个实施方案中,发射器控制电路38基于发射器配置信号PACS来配置RF发射器电路28。
PA偏置电路42将PA偏置信号PAB提供给RFPA40。就此而言,PA偏置电路42经由PA偏置信号PAB偏置RFPA40。在PA偏置电路42的一个实施方案中,PA偏置电路42基于发射器配置信号PACS来偏置RFPA40。在RF前端电路32的一个实施方案中,RF前端电路32包括至少一个RF开关、至少一个RF放大器、至少一个RF滤波器、至少一个RF双工器、至少一个RF共用器(diplexer)、至少一个RF放大器等等或其任何组合。在RF系统控制电路30的一个实施方案中,RF系统控制电路30是RF收发器电路,其可包括RF收发器IC、基带控制器电路等等或其任何组合。在RF发射器电路28的一个实施方案中,第一包络电源信号提供用于放大的功率,并且包络跟踪RF发射信号RFT。
图4示出根据RF通信系统26的替代实施方案的RF通信系统26。图4所示RF通信系统26类似图3所示RF通信系统26,除了在图4所示RF通信系统26中,RF发射器电路28进一步包括耦接在发射器控制电路38与数字通信总线46之间的数字通信接口44。数字通信总线46还耦接到RF系统控制电路30。因此,RF系统控制电路30经由数字通信总线46和数字通信接口44将电源控制信号VRMP(图3)和发射器配置信号PACS(图3)提供到发射器控制电路38。
图5示出根据DC-DC转换器10的一个实施方案的图3所示DC-DC转换器10的细节。DC-DC转换器10包括电源控制电路20、并行放大器14以及开关电源12。电源控制电路20控制并行放大器14和开关电源12。并行放大器14和开关电源12提供第一电源输出信号PS1,使得并行放大器14部分提供第一电源输出信号PS1并且开关电源12部分提供第一电源输出信号PS1。
图6示出根据RF通信系统26的另一实施方案的RF通信系统26。图6所示RF通信系统26类似图3所示RF通信系统26,除了在图6所示RF通信系统26中,省略PA偏置电路42(图3),并且RFPA40包括驱动器级48和耦接到驱动器级48的末级50。DC-DC转换器10基于电源控制信号VRMP将第二电源输出信号PS2(其为第二包络电源信号)提供到驱动器级48。另外,DC-DC转换器10基于电源控制信号VRMP将第一电源输出信号PS1(其为第一包络电源信号)提供到末级50。驱动器级48接收并且放大RF输入信号RFI,以使用提供用于放大的功率的第二包络电源信号提供驱动器级输出信号DSO。类似地,末级50接收并且放大驱动器级输出信号DSO,以使用提供用于放大的功率的第一包络电源信号提供RF发射信号RFT。
呈现对图2所示DC-DC转换器10的改进纹波消除性能的分析。通常,第一电源输出信号PS1被馈送到具有负载电阻RL的负载(未示出),如RFPA40(图3)。开关输出电压VS具有DC分量(称作DC电压VD)和纹波分量(称作AC电压VA),如等式1所给出,如下所示。
等式1:VS=VD+VA。
另外,电感器电流IL具有DC电流ID和AC电流IA,如等式2所给出,如下所示。
等式2:IL=ID+IA。
DC-DC转换器10将DC电压VD调节成约等于电压设定值。第一电感元件L1和第二电感元件L2近似显现为到DC分量的短路。另外,滤波电容元件CF近似显现为到DC分量的开路。因此,DC电压VD近似被施加到负载电阻RL,如所预期。因此,DC电流ID基于DC电压VD和负载电阻RL,如以下等式3所示。
等式3:ID=VD/RL。
开关输出电压VS中的大多数纹波分量通过第一低通滤波器22和第二低通滤波器24从第一电压V1中被过滤出。因此,多数AC电压VA在第一电感元件L1和第二电感元件L2的串联组合上。第一电感元件L1具有第一电感l1,并且第二电感元件L2具有第二电感l2。因此,AC电流IA基于AC电压VA、第一电感l1以及第二电感l2,其中s=j2πf,j=√-1,并且f=频率,如以下等式4所示。
等式4:IA=VA/[s(l1+l2)]。
更多剩余纹波分量通过并行放大器14从第一电压V1中被消除。然而,就并行放大器14无法完全消除剩余纹波分量的情况而言,第一电压V1具有第一残余纹波电压VR1并且第二电压V2具有第二残余纹波电压VR2。纹波消除的两种方法将彼此进行比较。在第一种方法中,DC-DC转换器10是图2中所示DC-DC转换器10,使得第二电压V2被馈送到反馈输入FBI,如图所示。就此而言,第二残余纹波VR2驱动并行放大器14以提供纹波消除电流(其为并行放大器输出电流IP)。在第二种方法中,DC-DC转换器10类似图2所示DC-DC转换器10,除了第一电压V1而非第二电压V2被馈送到反馈输入FBI,使得第一残余纹波电压VR1驱动并行放大器14以提供纹波消除电流(其为并行放大器输出电流IP)。
在以下分析中,并行放大器14具有DC开环增益GO和开环带宽因子T。因此,并行放大器14具有增益G,如以下等式5所示。
等式5:G=GO/(1+sT)。
因此,在明显低于并行放大器14的开环带宽的频率下,开环带宽因子T比1小,使得增益G接近DC开环增益GO。相反,在明显高于并行放大器14的开环带宽的频率下,开环带宽因子T比1大,使得增益G接近GO/sT。
在上述第一种方法中,其中第二残余纹波电压VR2驱动并行放大器14并且处于明显高于并行放大器14的开环带宽的频率,并行放大器输出电流IP基于第二残余纹波电压VR2,如以下等式6所示。
等式6:IP=G*VR2≈(GO*VR2)/sT。
在上述第二种方法中,当第一残余纹波电压VR1驱动并行放大器14并且处于明显高于并行放大器14的开环带宽的频率时,并行放大器输出电流IP基于第一残余纹波电压VR1,如以下等式7所示。
等式7:IP=G*VR1≈(GO*VR1)/sT。
然而,第一残余纹波电压VR1与第二残余纹波电压VR2之间的差基于AC电流IA和第二电感l2,如以下等式8和等式9所示。
等式8:(VR2–VR1)=(s)(IA)(l2),或
等式9:VR2=(s)(IA)(l2)+VR1。
将等式9替代到等式6中提供等式10和等式11,如下所示。
等式10:IP≈(GO)(VR1)/sT+(GO)(s)(IA)(l2)/sT,或
等式11:IP≈(GO)(VR1)/sT+(GO)(IA)(l2)/T。
等式11代表第一种方法,并且等式7代表第二种方法。作为剩余部分,在第一种方法中,第二残余纹波电压VR2驱动并行放大器14,并且在第二种方法中,第一残余纹波电压VR1驱动并行放大器14。在两个等式中,较小的第一残余纹波电压VR1呈现更好纹波消除性能。出于比较目的,假定两种方法提供相同量值的并行放大器输出电流IP。然而,在第二种方法中,并行放大器输出电流IP以约90度从第一残余纹波电压VR1相移。因此,并行放大器输出电流IP以约90度从其试图消除的纹波电流相移,从而降低纹波消除性能。然而,在第一种方法中,根据等式11,并行放大器输出电流IP具有两个项,即(GO)(VR1)/sT项和(GO)(IA)(l2)/T项。(GO)(VR1)/sT项具有与第二种方法中的相同的相位对准缺点。但是(GO)(IA)(l2)/T项将并行放大器输出电流IP与其试图消除的纹波电流进行相位对准。总体来说,第一种方法中的相位对准优于第二种方法。另外,就(GO)(VR1)/sT项小于(GO)(IA)(l2)/T项的情况而言,第一残余纹波电压VR1减少,从而改进纹波消除。就此而言,如果(GO)(IA)(l2)/T项等于等式7中的(GO)(VR1)/sT项,那么在等式11中的(GO)(VR1)/sT项中,第一残余纹波电压VR1等于约零,使得第一种方法大大优于第二种方法。
前述电路中的一些可以使用离散电路、集成电路、可编程的电路、非易失性电路、易失性电路、计算硬件上的软件执行指令、计算硬件上的固件执行指令等等或其任何组合。计算硬件可以包括主机、微处理器、微控制器、DSP等等或其任何组合。
本公开的实施方案并不意图限制本公开的任何其它实施方案的范围。本公开的任何实施方案中的任何或所有可与本公开的任何其它实施方案中的任何或所有组合,以形成本公开的新的实施方案。
本领域技术人员将认识到本公开的实施方案的改进和修改。所有此类改进和修改都被认为是在本文所公开的概念和所附权利要求书的范围内。
Claims (27)
1.电路,其包括:
·并行放大器,所述并行放大器具有反馈输入和并行放大器输出;以及
·开关电源,所述开关电源包括:
·开关电路,所述开关电路具有开关电路输出;
·第一电感元件,所述第一电感元件耦接在所述开关电路输出与所述反馈输入之间;以及
·第二电感元件,所述第二电感元件耦接在所述反馈输入与所述并行放大器输出之间,其中第一电感元件具有第一电感并且第二电感元件具有第二电感,使得所述第一电感的量值是所述第二电感的量值的至少10倍。
2.电路,其包括:
·并行放大器,所述并行放大器具有反馈输入和并行放大器输出,并且适于基于电压设定值经由所述并行放大器输出来部分提供第一电源输出信号;以及
·开关电源,所述开关电源包括:
·开关电路,所述开关电路具有开关电路输出;
·第一电感元件,所述第一电感元件耦接在所述开关电路输出与所述反馈输入之间;以及
·第二电感元件,所述第二电感元件耦接在所述反馈输入与所述并行放大器输出之间,其中所述开关电源适于经由所述第一电感元件和所述第二电感元件来部分提供所述第一电源输出信号。
3.如权利要求2所述的电路,其中所述电压设定值基于电源控制信号。
4.如权利要求2所述的电路,其中:
·所述并行放大器进一步适于基于所述电压设定值来调节所述第一电源输出信号的电压;以及
·所述开关电源进一步适于调节所述第一电源输出信号以最小化来自所述并行放大器的输出电流。
5.如权利要求2所述的电路,其中所述第二电感元件上的相移至少部分补偿所述并行放大器在高于频率阈值的频率下的有限开环增益。
6.如权利要求2所述的电路,其进一步包括射频(RF)功率放大器(PA),其中:
·所述第一电源输出信号是第一包络电源信号;以及
·所述射频功率放大器适于接收并且放大射频输入信号,以使用所述第一包络电源信号提供射频发射信号。
7.如权利要求6所述的电路,其中所述第一包络电源信号将用于放大的功率提供到所述射频功率放大器。
8.如权利要求6所述的电路,其中所述射频功率放大器包括末级,所述末级适于使用所述第一包络电源信号提供所述射频发射信号。
9.如权利要求6所述的电路,其中:
·所述第一电感元件和所述第二电感元件在连接节点处彼此连接;
·所述第一电感元件和所述第二电感元件适于经由所述连接节点提供第二电源输出信号;
·所述第二电源输出信号是第二包络电源信号;
·所述射频功率放大器包括驱动器级和耦接到所述驱动器级的末级;
·所述驱动器级接收并且放大所述射频输入信号,以使用所述第二包络电源信号提供驱动器级输出信号;以及
·所述末级接收并且放大所述驱动器级输出信号,以使用所述第一包络电源信号提供所述射频发射信号。
10.如权利要求2所述的电路,其中:
·DC电源适于将DC电源信号提供到所述并行放大器和所述开关电源;
·所述并行放大器进一步适于使用所述DC电源信号部分提供所述第一电源输出信号;以及
·所述开关电源进一步适于使用所述DC电源信号部分提供所述第一电源输出信号。
11.如权利要求10所述的电路,其中所述DC电源是电池。
12.如权利要求10所述的电路,其进一步包括所述DC电源。
13.如权利要求2所述的电路,其中:
·所述第一电感元件和所述第二电感元件在连接节点处彼此连接;以及
·所述第一电感元件和所述第二电感元件适于经由所述连接节点提供第二电源输出信号。
14.如权利要求1所述的电路,其中所述开关电源进一步包括耦接在所述并行放大器输出与所述第二电感元件之间的偏移电容元件,使得所述并行放大器进一步适于基于电压设定值经由所述并行放大器输出和所述偏移电容元件来部分提供第一电源输出信号。
15.如权利要求1所述的电路,其中所述第一电感元件具有第一电感,并且所述第二电感元件具有第二电感,使得所述第一电感的量值是所述第二电感的量值的至少100倍。
16.如权利要求1所述的电路,其中所述第一电感元件具有第一电感,并且所述第二电感元件具有第二电感,使得所述第一电感的量值是所述第二电感的量值的至少500倍。
17.如权利要求1所述的电路,其中所述第一电感元件具有第一电感,并且所述第二电感元件具有第二电感,使得所述第一电感的量值是所述第二电感的量值的至少1000倍。
18.如权利要求1所述的电路,其中所述第一电感元件具有第一电感,并且所述第二电感元件具有第二电感,使得所述第一电感的量值是所述第二电感的量值的不到1000倍。
19.如权利要求1所述的电路,其中所述第一电感元件具有第一电感,并且所述第二电感元件具有第二电感,使得所述第一电感的量值是所述第二电感的量值的不到5000倍。
20.如权利要求1所述的电路,其中所述开关电源进一步包括耦接在所述并行放大器输出与接地之间的滤波电容元件。
21.电路,其包括:
·并行放大器,所述并行放大器具有反馈输入和并行放大器输出;以及
·开关电源,所述开关电源包括:
·开关电路,所述开关电路具有开关电路输出;
·第一电感元件,所述第一电感元件耦接在所述开关电路输出与所述反馈输入之间;以及
·第二电感元件,所述第二电感元件耦接在所述反馈输入与所述并行放大器输出之间,其中:
·所述开关电源进一步包括滤波电容元件,所述滤波电容元件耦接在所述并行放大器输出与接地之间;
·所述第一电感元件、所述第二电感元件以及所述滤波电容元件形成具有第一截止频率的第一低通滤波器;以及
·所述第二电感元件和所述滤波电容元件形成具有第二截止频率的第二低通滤波器。
22.如权利要求21所述的电路,其中所述第二截止频率是所述第一截止频率的至少10倍。
23.如权利要求21所述的电路,其中所述第二截止频率是所述第一截止频率的至少100倍。
24.如权利要求21所述的电路,其中所述第二截止频率是所述第一截止频率的至少500倍。
25.如权利要求21所述的电路,其中所述第二截止频率是所述第一截止频率的至少1000倍。
26.如权利要求21所述的电路,其中所述第二截止频率是所述第一截止频率的不到1000倍。
27.如权利要求22所述的电路,其中所述第二截止频率是所述第一截止频率的不到5000倍。
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