CN103594315B - A kind of plasma processing device - Google Patents
A kind of plasma processing device Download PDFInfo
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- CN103594315B CN103594315B CN201310342269.3A CN201310342269A CN103594315B CN 103594315 B CN103594315 B CN 103594315B CN 201310342269 A CN201310342269 A CN 201310342269A CN 103594315 B CN103594315 B CN 103594315B
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- 238000012545 processing Methods 0.000 title claims abstract description 72
- 238000006243 chemical reaction Methods 0.000 claims abstract description 17
- 230000005284 excitation Effects 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims description 51
- 239000003507 refrigerant Substances 0.000 claims description 43
- 239000002826 coolant Substances 0.000 claims description 27
- 239000007789 gas Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 9
- 239000010453 quartz Substances 0.000 claims description 9
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 230000001939 inductive effect Effects 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 5
- 238000001816 cooling Methods 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 229910010293 ceramic material Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 107
- 238000001179 sorption measurement Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007743 anodising Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000005686 electrostatic field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000110 cooling liquid Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Analytical Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a kind of plasma processing device, comprise reaction chamber, upper excitation radio frequency power source, direct current power source and wafer support, described upper excitation radio frequency power source produces the energy of plasma in order to provide; Described wafer support is located in described reaction chamber, and it comprises for the pallet of bearing wafer and the chuck for carrying described pallet; Be provided with pallet electrode in pallet, in chuck, be provided with chuck electrode, pallet and chuck electrically insulated from one another, and with plasma electric insulation, direct current power source be used between pallet electrode and chuck electrode and between pallet electrode and wafer, produce voltage difference respectively; And the first electric capacity is formed between wafer and pallet electrode, between pallet electrode and chuck electrode, form the second electric capacity, the first electric capacity and the second Capacitance parallel connection.This plasma apparatus cavity structure, not only functional, reliability is high, and structure is simple, with low cost.
Description
Technical Field
The invention belongs to the field of semiconductor processing, and relates to plasma processing equipment.
Background
ICP plasma dry etching equipment is a common equipment for processing semiconductor devices. In order to process a plurality of wafers simultaneously, the plurality of wafers are usually placed on a surface of a tray having a large size, and then the tray is placed on a carrying surface of a chuck of a plasma processing chamber to be processed.
In actual processing, the plasma can cause the temperature of the wafer to exceed the temperature required by the process, and thus, the temperature of the wafer needs to be controlled. The conventional way of controlling the temperature is to blow a coolant gas (e.g., helium gas) on the back surface of the wafer (the surface opposite to the processed surface of the wafer) and adjust the temperature of the wafer by the coolant gas. In order to fix the wafer and prevent the refrigerant gas from leaking, a pressing unit is used to apply a force toward the chuck at the edge of the wafer. This type of fixing is not only cumbersome to implement, but also has poor stability, which affects the cooling effect. In addition, the pressing unit needs to occupy the processing surface of the wafer, reducing the effective processing area of the wafer.
To this end, related art has developed ways of holding the wafer using electrostatic force (alternatively referred to as coulomb force). Fig. 1 is a schematic cross-sectional view illustrating an example of fixing a wafer by electrostatic force according to the related art. As shown in fig. 1, the tray 102 is placed on the carrying surface of the tray support table 101, and the wafer S is placed on the carrying surface of the tray 102. An electrode 106 is provided in the tray 102, and the electrode 106 is electrically connected to an ESC power supply 105 through a spring terminal. After the power is turned on, the processed surface of the wafer S induces a charge layer with a polarity opposite to that of the electrode 106, so that a voltage difference is generated between the wafer S and the electrode 106, and the wafer S is fixed on the carrying surface of the tray 106. The cover plate 103 is used to cover the area of the tray 106 not covered by the wafer S. The tray 102 is a bearing surface fixed to the tray support table 101 by a mechanical press ring 104.
The method of fixing the wafer S by electrostatic force is fixed on the surface of the tray 102, but the tray 102 still needs the mechanical press ring 104 for fixing, which not only has complex structure, high cost and troublesome operation, but also the mechanical parts are easy to be damaged, and the maintenance work will affect the use efficiency of the plasma processing apparatus.
Disclosure of Invention
To solve at least one of the above problems, the present invention provides a plasma processing apparatus, in which a chuck and a tray have simple structures, low cost, and are easy to use and not easily damaged.
The technical scheme adopted for solving the technical problems is to provide plasma processing equipment which comprises a reaction chamber, an upper excitation radio frequency power source, a direct current power source and a wafer supporting device, wherein the upper excitation radio frequency power source is used for providing energy for generating plasma;
the wafer supporting device is arranged in the reaction chamber and comprises a tray for bearing a wafer and a chuck for bearing the tray;
a tray electrode is arranged in the tray, a chuck electrode is arranged in the chuck, the tray and the chuck are mutually electrically insulated and are electrically insulated from the plasma, and the direct current power source is used for respectively generating voltage differences between the tray electrode and the chuck electrode and between the tray electrode and the wafer; and forming a first capacitance between the wafer and the tray electrode and a second capacitance between the tray electrode and the chuck electrode, the first capacitance and the second capacitance being connected in parallel.
The direct current power source comprises a direct current power supply, the direct current power supply comprises a positive electrode output end and a negative electrode output end, the positive electrode output end is electrically connected with the tray electrode, the negative electrode output end is grounded, and the chuck electrode is grounded; or the negative electrode output end is electrically connected with the tray electrode, the positive electrode output end is grounded, and the chuck electrode is grounded.
The direct current power source comprises a direct current power source, the direct current power source comprises a positive output end, a negative output end and a public end, the tray electrode is electrically connected with the positive output end of the direct current power source or the negative output end of the direct current power source, the public end is grounded, and the chuck electrode is grounded.
The direct current power source comprises a direct current power source, the direct current power source comprises a positive electrode output end and a common end, the positive electrode output end is electrically connected with the tray electrode, the common end is grounded, and the chuck electrode is grounded;
or the direct current power supply comprises a negative output end and a public end, the negative output end is electrically connected with the tray electrode, the public end is grounded, and the chuck electrode is grounded.
Wherein a filter circuit is connected in series between the tray electrode and the DC power supply.
The filter circuit is a high-frequency resistor.
The filter circuit is a filter circuit with radio frequency attenuation smaller than-10 dB.
The filter circuit comprises n inductors and n capacitors, wherein the n inductors are connected in series, the n capacitors are connected in parallel, the capacitors are connected in parallel with the inductors, one end of each capacitor is grounded, and n is an integer larger than or equal to 1.
The direct-current power source comprises a first direct-current power source and a second direct-current power source, the first direct-current power source and the second direct-current power source respectively comprise a positive output end, a negative output end and a public end, the tray electrode is electrically connected with the positive output end or the negative output end of the first direct-current power source, the chuck electrode is electrically connected with the positive output end or the negative output end of the second direct-current power source, and the public end of the first direct-current power source and the public end of the second direct-current power source are both grounded.
Wherein, filter circuits are respectively connected in series between the tray electrode and the DC power source and between the chuck electrode and the DC power source.
The filter circuit is a high-frequency resistor.
The filter circuit is a filter circuit with radio frequency attenuation smaller than-10 dB.
The filter circuit comprises n inductors and n capacitors, wherein the n inductors are connected in series, the n capacitors are connected in parallel, the capacitors are connected in parallel with the inductors, one end of each capacitor is grounded, and n is an integer larger than or equal to 1.
The tray comprises a tray body and an insulating layer, wherein the tray body is made of a conductive material, the insulating layer coats the outer surface of the tray body, and the tray body is used as the tray electrode;
the chuck comprises a chuck body and an insulating layer, wherein the chuck body is made of a conductive material, the insulating layer coats the outer surface of the chuck body, and the chuck body serves as a chuck electrode.
The insulating layer is obtained by spraying an insulating material; or an aluminum oxide layer obtained by means of anodic oxidation.
Wherein the insulating material comprises quartz or a ceramic or metal oxide.
The chuck is internally provided with a first chuck refrigerant channel, and the first cooling medium cools the chuck by means of the first chuck refrigerant channel.
The first refrigerant medium is refrigerant liquid.
Wherein the refrigerant liquid is fluorine cooling liquid.
The chuck is internally provided with a second chuck refrigerant channel penetrating through the chuck in the thickness direction, a chuck annular groove is arranged on the bearing surface of the chuck, and the chuck annular groove is communicated with the second chuck refrigerant channel;
the wafer cooling device comprises a tray, a tray ring groove, a chuck ring groove, a tray refrigerant channel and a tray cooling medium channel, wherein the tray refrigerant channel penetrating through the thickness direction of the tray is arranged in the tray, the lower surface of the tray is provided with the tray ring groove, the tray ring groove is opposite to the chuck ring groove in position, the tray refrigerant channel is communicated with the chuck ring groove, and the second cooling medium is supplied to the back of a wafer through the second chuck refrigerant channel, the chuck ring groove, the tray ring groove and the tray refrigerant channel in sequence so as to cool the wafer.
The second refrigerant medium is refrigerant gas.
Wherein, the refrigerant gas is helium.
Wherein, the size of the lower surface of the tray is not less than the size of the bearing surface of the chuck.
The top of the reaction chamber is provided with a dielectric window, the upper electrode comprises an inductive coupling coil, and the inductive coupling coil is arranged above the dielectric window.
The plasma processing device comprises a lower radio frequency power source, wherein the lower radio frequency power source is connected with a chuck electrode and used for generating direct current self bias voltage on the surface of a wafer so as to attract plasma to process the surface of the wafer.
The upper excitation radio frequency power source and the lower excitation radio frequency power source are two independent radio frequency power sources, or two independent radio frequency powers output by one radio frequency power source.
The bearing surface of the tray is provided with a boss, and the wafer is arranged at the top end of the boss;
the wafer processing device is characterized by further comprising a cover plate, wherein the cover plate is stacked on the bearing surface of the tray, a positioning hole is formed in the cover plate, the positioning hole is opposite to the boss, and the processed surface of the wafer is exposed to the plasma through the positioning hole.
Wherein, the cover plate is made of quartz or ceramic material.
Wherein the plasma processing equipment is an ICP plasma dry etching machine or ITO physical vapor deposition equipment.
Wherein, the material of the wafer is sapphire, silicon or silicon oxide.
The invention has the following beneficial effects:
according to the plasma processing equipment provided by the invention, a tray electrode is arranged in a tray, a chuck electrode is arranged in the chuck, voltage differences are respectively generated between the tray electrode and the chuck electrode and between the tray electrode and a wafer through a direct current power source, and electrostatic adsorption force is generated between the tray and the chuck due to the voltage difference between the tray electrode and the chuck electrode, so that the tray is fixed on a bearing surface of the chuck; the voltage difference between the tray electrode and the wafer enables electrostatic adsorption force to be generated between the tray and the wafer, and therefore the wafer is fixed on the carrying surface of the tray; namely, the wafer and the tray are respectively fixed on the tray and the chuck in an electrostatic adsorption mode, so that a mechanical pressure ring is avoided, the design is simple, the structure is simplified, and the manufacturing cost of the plasma processing equipment is reduced; the operation is simple, and the processing efficiency of the plasma processing equipment can be improved; and the secondary reliability is high, the damage is not easy to occur, the maintenance cost is reduced, and the utilization rate of the plasma processing equipment can be improved. In addition, the wafer and the tray are fixed in an electrostatic adsorption mode, so that the refrigerant gas can be effectively prevented from leaking, and the temperature of the wafer is effectively managed. In addition, the first capacitor and the second capacitor are connected in parallel, so that the power of a direct current power source can be effectively utilized, the electrostatic adsorption force between the tray and the wafer and the electrostatic adsorption force between the tray and the chuck can be maximized, on one hand, the adsorption effect of the wafer and the tray is improved, the wafer and the tray are better fixed, and the refrigerant gas is prevented from leaking; on the other hand, lower voltage is needed to generate the same amount of electrostatic adsorption force, so that the voltage withstanding grade of the tray and the chuck is reduced, and the cost of the tray and the chuck is further reduced.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating an example of a conventional wafer fixing device using electrostatic force;
FIG. 2 is a schematic sectional view showing a partial structure of a plasma processing apparatus according to an embodiment of the present invention;
FIG. 3 is a schematic sectional view showing a partial structure of a plasma processing apparatus according to another embodiment of the present invention;
fig. 4 is a schematic structural view of a plasma processing apparatus according to still another embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view of an electrostatic chuck, etc., according to the present invention;
FIG. 6 is a schematic diagram of another filter circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another filter circuit according to an embodiment of the present invention
Fig. 8 is a schematic diagram of two dc electrode plates with opposite charges.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the plasma processing apparatus provided by the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 2 is a schematic cross-sectional view of a part of a plasma processing apparatus according to an embodiment of the present invention. As shown in fig. 2, the plasma processing apparatus includes a reaction chamber 16, and a chamber wall of the reaction chamber 16 is grounded. A chuck base 8 is provided at the bottom inside the reaction chamber 16, the chuck 6 is fixed to the top end of the chuck base 8, and a tray 5 is placed on a carrying surface (shown as the upper surface of the chuck) of the chuck 6, the tray 5 being used to carry the wafer 3. A dielectric window 17 is arranged at the top end of the reaction chamber 16, the inductive coupling coil 15 is arranged above the dielectric window 17, and the inductive coupling coil 15 is electrically connected with the upper excitation radio frequency power source 10 through the upper matcher 9. The upper excitation radio frequency power source 10, the upper matcher 9 and the inductive coupling coil 15 form an upper electrode, and the upper electrode is used for exciting the process gas in the reaction chamber 16 to ionize to form the plasma 11. A dc power source 14 is used to provide power for holding the wafer 3 and the tray 8. The lower excitation power source 12 is connected to the chuck 6 through the lower matching device 11, and the lower excitation rf power source 12, the lower matching device 11 and the chuck 6 constitute a lower electrode for generating a dc self-bias voltage on the surface of the wafer 3 and attracting plasma to process the surface of the wafer 3. An excitation rf power source 13 and a dc power source 24 may also be disposed within the reaction chamber 20.
The chuck 6 includes a chuck body and an insulating layer, and the chuck body is used as a chuck electrode (or chuck electrostatic adsorption electrode) made of a conductive material such as metal, e.g., copper or aluminum. The insulating layer is made of an insulating material, such as quartz, ceramic or metal oxide, which covers the outer surface of the chuck body. The insulating layer may be formed on the outer surface of the chuck body by spraying, anodizing, or the like. The insulating layer is to electrically insulate the chuck 6 from the tray 5, and to electrically insulate the chuck 6 from the plasma 1 in the reaction chamber 16.
The tray 5 comprises a tray body and an insulating layer, and the insulating layer coats the outer surface of the tray body. The tray body is used as a tray electrode (or called as an electrostatic adsorption electrode) and is made of conductive materials such as metal and the like, such as copper and aluminum. The insulating layer is made of insulating materials, such as quartz and ceramics, and can be formed on the surface of the conductive material by spraying, anodizing or the like. Insulating layer to insulate the tray 5, to electrically insulate the tray 5 from the chuck 6, and to electrically insulate the tray 5 from the plasma 10 in the reaction chamber 16.
The tray 5 and the chuck 6 may be of other configurations as long as it is ensured that the tray 5 and the chuck 6 are electrically insulated from each other and from the plasma.
In this embodiment, the dc power source 14 is a dc power source, and the dc power source 14 includes a positive output terminal (HV +), a negative output terminal (HV-), and a common terminal (or called middle point CT), where the common terminal is grounded, or the common terminal is connected to the casing and then grounded. The tray electrode is electrically connected with the negative output end of the direct current power supply, and the chuck electrode is directly grounded (or grounded through a filter circuit). Of course, the tray electrode may also be electrically connected to the positive output terminal of the dc power supply 14, and the tray electrode may be electrically connected to the common terminal of the dc power supply 14 (the common terminal is grounded).
It should be noted that the dc power supply 14 may also include only the positive output terminal and the common terminal, only the negative output terminal and the common terminal, or only the positive output terminal and the negative output terminal. When the direct current power supply only comprises the anode output end and the public end, the tray electrode is connected with the anode output end, the public end is grounded, and the chuck electrode is grounded. When the direct current power supply only comprises the negative output end and the common end, the tray electrode is connected with the negative output end, the common end is grounded, and the chuck electrode is grounded (or grounded through a filter circuit). When the direct-current power supply only comprises a positive output end and a negative output end, the positive output end is electrically connected with the tray electrode, the negative output end is grounded, and the chuck electrode is grounded (or grounded through a filter circuit); or the negative output end is electrically connected with the tray electrode, the positive output end is grounded, and the chuck electrode is grounded (or grounded through a filter circuit).
In a plasma environment, a charge layer (so-called DC self-bias) is formed on the processed surface (upper surface of the wafer in the figure) of the wafer 3, when the DC power source 14 supplies electricity to the tray electrode, a voltage difference exists between the tray and the wafer 3, an electrostatic field is formed, an electrostatic attraction force (different according to the type of the wafer and the position of the voltage difference is formed) is formed between the tray 5 and the wafer 3, when the back of the wafer is a semiconductor (such as Si) or a conductor material (such as metal), the tray electrode is electrified, the back of the wafer induces a charge with the opposite polarity of the tray electrode, the voltage difference is the charge layer induced by the tray electrode and the back of the wafer, when the back of the wafer is an insulating material (such as sapphire), the voltage difference is the charge layer (so-called DC self-bias) formed by the tray electrode and the upper surface of the wafer, the electrostatic attraction holds the wafer 3 on the carrying surface of the tray 5. At the same time, a voltage difference is also generated between the tray 5 and the chuck 6 to form an electrostatic field, and an electrostatic attraction force is formed between the tray and the chuck, which attracts the tray 5 to the carrying surface of the chuck 6.
The magnitude of the electrostatic attraction between the tray 5 and the wafer 3 and the electrostatic attraction between the tray 5 and the chuck 6 will be described.
As shown in fig. 8, in vacuum, two dc electrode plates with opposite charges are schematically shown, and according to coulomb's law, the calculation formula of the electrostatic attraction between the two electrode plates is:
wherein,
f-electrostatic attraction;
k-dielectric constant of the insulating layer;
0-a vacuum dielectric constant;
a-area of the DC electrode layer;
voltage difference between V-DC electrodes;
d-distance between direct current electrodes.
The tray electrode is communicated with the negative output end (HV-) of the direct current power supply 14, and if E is the voltage value of the negative output end (HV-) of the direct current power supply 14 to the middle point of the direct current voltage, the middle point (CT) is connected with the shell, and the shell is grounded, so that the voltage value of the negative output end (HV-) of the direct current power supply 14 to the ground is E, and the voltage value of the tray electrode to the Ground (GND) or the shell is also E.
For the wafer with semiconductor and conductor material on the back, after the tray electrode is electrified, a charge layer is induced on the back of the wafer, and the voltage value of the charge layer on the back of the wafer to the ground or the chassis is set as E1The insulation distance between the tray electrode and the wafer charge layer is set as d1The equivalent capacitance formed by the tray electrode and the wafer is set as C1Then, according to the above formula for calculating the electrostatic attraction, the electrostatic attraction between the wafer 3 and the tray 5 is:
for a wafer with an insulating material on the back, after plasma ignition, a charge layer is formed on the top surface of the wafer, i.e. DC self-bias, and the chargeThe voltage value of the layer to the ground or the shell is set as E2The insulation distance between the tray electrode and the wafer charge layer is set as d2The equivalent capacitance formed by the tray electrode and the wafer is set as C2. Then, according to the above formula for calculating the electrostatic attraction, the electrostatic attraction between the wafer 3 and the tray 5 is:
in addition, the value E of the DC self-bias voltage is relative to the voltage E to ground of the negative output terminal (HV-) of the DC power supply2The voltage to ground is very small and almost negligible, so the electrostatic attraction between the wafer 3 and the tray 5 can be approximated by:
the chuck electrode is grounded through a filter circuit or connected with the shell, namely, the chuck electrode is grounded through direct current, and the insulating distance between the chuck electrode and the tray electrode is set as d3The equivalent capacitance value of the tray electrode and the chuck electrode is set as C3Then, the electrostatic attraction force F between the tray 5 and the chuck 6 is calculated based on the above1Comprises the following steps:
electrostatic attraction force F between the tray electrode and the wafer S2Comprises the following steps:
two equivalent capacitors are respectively formed between the wafer 3 and the tray electrode and between the tray electrode and the chuck electrode, and the capacitor formed between the wafer 3 and the tray electrode is called as a first capacitor, and the capacitor formed between the tray electrode and the chuck electrode is called as a second capacitor. The first capacitor and the second capacitor are connected in parallel. The first capacitor and the second capacitor are connected in parallel, so that the voltage difference between the chuck electrode and the tray electrode and the voltage difference between the tray electrode and the wafer are respectively approximately equal to or greater than a voltage value E (HV-) at the negative output end of the direct current power supply 14, and the electrostatic attraction between the chuck electrode and the tray electrode and the electrostatic attraction between the tray electrode and the wafer are maximized in the voltage value distribution mode. Or, if the same electrostatic attraction is to be obtained, when the first capacitor and the second capacitor are connected in parallel, the required output voltage value provided by the dc power supply 14 is minimized, so that the withstand voltage level of the chuck and the tray can be effectively reduced, the design difficulty of the dc power supply is reduced, and the manufacturing cost of the plasma processing equipment can be reduced.
A filter circuit 13a may be connected in series between the dc power source 14 and the tray electrode to prevent rf energy from being attenuated due to rf energy leaking out of the loop and to prevent rf interference to other devices. The filter circuit 13a includes a first inductor L1 and a first capacitor C1, one end of the first inductor L1 is connected to the tray 5 as a first output terminal of the filter circuit, and the other end is connected to a negative output terminal (HV-) of the dc power supply 14 as a second output terminal of the filter circuit. One end of the first capacitor C1 is connected to ground or the casing, and the other end is connected to the second output terminal of the filter circuit and the negative output terminal (HV-) of the dc power source 14. A filter circuit 13b is connected in series between the chuck electrode and ground or the chassis, the filter circuit 13b is composed of an inductor L2, and the filter circuit 13b is also used to prevent rf energy from leaking out through the loop to cause rf energy attenuation and to prevent rf interference to other devices.
The filter circuit 13a may also adopt other filter circuits capable of avoiding attenuation of radio frequency energy and resisting radio frequency interference. As shown in fig. 6, the filter circuit 13a includes a first inductor L1, a second inductor L2, a first capacitor C1, and a second capacitor C2, wherein the first inductor L1 and the second inductor L2 are connected in series, and the other ends of the first inductor L1 and the second inductor L2 are respectively used as a first output end and a second output end of the filter circuit. The first capacitor C1 and the second capacitor C2 are connected in parallel, one end of the first capacitor C1 and one end of the second capacitor C2 are grounded, and the other end of the first capacitor C1 and the other end of the second capacitor C2 are connected with the second output end of the filter circuit.
Although the filter circuit 13a of two structures is exemplified here, the structure of the filter circuit 13a is not limited to this. In practice, the filter circuit may include n inductors and n capacitors, where n is an integer greater than or equal to 1. The inductors and the capacitors are connected in a way that n inductors are connected in series, n capacitors are connected in parallel, then n capacitors are connected in parallel with n inductors, and one end of each capacitor is grounded. Of course, the filter circuit 13a may be formed by any combination of inductors, resistors and capacitors, such as a high frequency resistor. The filter circuit 13a may be applied to the present invention as long as it can prevent the rf energy from leaking out through the loop. In practical applications, the filter circuit 13a is a filter circuit capable of satisfying radio frequency attenuation less than-10 dB.
The filter circuit 13b may also adopt other filter circuits capable of avoiding attenuation of radio frequency energy and resisting radio frequency interference. As shown in fig. 4, the filter circuit 13b includes a first inductor L3 and a second inductor L4. The first inductor L3 and the second inductor L3 are connected in series, and the other ends of the first inductor L1 and the second inductor L2 are respectively used as a first output end and a second output end of the filter circuit.
Although the filter circuit 13b of two structures is exemplified here, the structure of the filter circuit 13b is not limited to this. In practice, the filter circuit may include n inductors, where n is an integer greater than or equal to 1. As long as n inductors will be connected in series. Of course, the filter circuit 13b may be formed by any combination of inductors and resistors, such as a high frequency resistor. The filter circuit 13b may be applied to the present invention as long as it can prevent the rf energy from leaking out through the loop. In practical applications, the filter circuit 13b is a filter circuit capable of satisfying radio frequency attenuation less than-10 dB.
During the process, the temperatures of the wafer 3, the tray 5, and the chuck 6 are easily increased by the plasma to affect the quality of the mask and the lifetime of the tray 5 and the chuck 6. Therefore, it is necessary to adjust the temperatures of the wafer 3, the tray 5, and the chuck 6 using a refrigerant medium.
As shown in fig. 2, a first chuck coolant channel 7 for cooling the chuck 6 and the tray 5 is provided in the chuck 6, and the chuck 6 and the tray 5 can be cooled by introducing a first coolant into the first chuck coolant channel 7. The first refrigerant medium is a refrigerant liquid, such as Galden (fluorine coolant) liquid.
Still be equipped with the second chuck refrigerant passageway 4B that runs through its thickness direction in chuck 6, still be equipped with the tray refrigerant passageway 4a that runs through its thickness direction in tray 5, be equipped with chuck annular groove A at loading end (upper surface) of chuck 6, be equipped with tray annular groove B at the lower surface of tray, tray annular groove B is relative with chuck annular groove A's position, chuck annular groove A, tray annular groove B communicate second chuck refrigerant passageway 4B and tray refrigerant passageway 4 a. The chuck base 8 is provided with a refrigerant passage 4c penetrating the thickness direction thereof as an inlet for the refrigerant gas to enter the refrigerant gas passage. Be equipped with chuck annular groove D at the lower surface of chuck, be equipped with annular groove C at chuck base upper surface, chuck annular groove D is relative with base annular groove C's position, and chuck annular groove D, base annular groove C communicate second chuck refrigerant passageway 4b and chuck base refrigerant passageway 4C.
The second cooling medium is conveyed to the back of the wafer 3 in sequence through the chuck base cooling medium channel 4C, the chuck base annular groove C, the chuck annular groove D, the second chuck cooling medium channel 4B, the chuck annular groove a, the tray annular groove B and the tray cooling medium channel 4a, and finally cools the wafer 3. The second refrigerant medium is a refrigerant gas, such as an inert gas like helium.
Preferably, a plurality of second chuck refrigerant channels 4b communicated with the chuck annular groove a are arranged in the chuck 6, a plurality of tray refrigerant channels 4a are arranged in the tray 5, and the plurality of second chuck refrigerant channels 4b and the tray refrigerant channels 4a can not only effectively adjust the temperature, but also improve the uniformity of the temperature.
When the wafer 3 is placed on the carrying surface of the tray 5, the wafer 3 cannot completely shield the carrying surface of the tray 5. In the process, the carrying surface of the tray 5 which is not shielded by the wafer S is etched by the plasma 1, which affects the service life of the tray 5. For this purpose, the plasma processing apparatus further includes a cover plate 2 made of a ceramic or quartz material, and positioning holes 2a penetrating the thickness of the cover plate are formed in the cover plate 2, and one wafer 3 can be placed in each positioning hole 2 a. The cover plate 2 is stacked on the carrying surface of the tray 5 and fixed to the tray 5 by screws (not shown), which are also made of quartz or ceramic material. The wafer 3 is fitted into the positioning hole 2a, and the processed surface of the wafer 3 is exposed to plasma through the positioning hole 2 a. The positioning holes 2a provided on the cover plate 2 are advantageous for improving the loading efficiency of the wafer 3. It will be understood that the inner diameter of the positioning hole 2a is equal to or slightly larger than the outer diameter of the wafer 3. Preferably, the outer diameter of the cover plate 2 is equal to or slightly larger than the outer diameter of the tray 5, so that the tray 5 exposed to the plasma 1 can be partially shielded, thereby preventing the plasma 1 from etching the tray 5.
The carrying surface of the tray 5 is further provided with a boss 5a, the boss 5a is opposite to the positioning hole 2a, and the wafer 3 is placed at the top end of the boss 5 a. In order to support a plurality of wafers 3 on the tray 5, a plurality of bosses 5a are provided on the supporting surface of the tray 5, and a plurality of positioning holes 2a are correspondingly provided in the cover plate, the number of the positioning holes 2a being equal to the number of the bosses 5 a.
Preferably, the diameter of the lower surface of the tray 5 is equal to or slightly larger than that of the carrying surface of the chuck 6, i.e., the size of the lower surface of the tray 5 is not smaller than that of the carrying surface of the chuck 6, so as to enable reliable sealing between the tray 5 and the chuck 6 and prevent plasma from damaging the carrying surface of the chuck 6.
As shown in fig. 2, the upper electrode includes an inductive coupling coil 15 disposed above a dielectric window 17, and the dielectric window 17 is disposed at the top of the reaction chamber 16. The dielectric window 17 is made of quartz or ceramic material. The inductive coupling coil is connected with an upper excitation radio frequency power source 10 through an upper matcher 9, and a lower bias radio frequency power source 12 is electrically connected with the chuck 6, namely a conductive part of the chuck 6, through a lower matcher 11.
It should be noted that the upper and lower excitation rf power sources 10 and 12 are two independent rf power sources. However, the present invention is not limited thereto, and the upper driving rf power source 10 and the lower driving rf power source 12 may also share one rf power source, i.e. one rf power source generates two independent rf power outputs.
The plasma processing equipment provided by the embodiment can be used as an ICP (inductively coupled plasma) dry etching machine, and is particularly suitable for etching a patterned sapphire substrate (PSS-patterned sapphire substrate); or as an ITO (indium tin oxide) physical vapor deposition device for preparing an ITO film.
In order to improve the processing efficiency of the plasma processing apparatus, a plurality of wafers 3 are generally disposed on the tray 5. The carrying surface of the tray 5 is provided with a plurality of bosses 5a, the cover plate 2 is also provided with positioning holes 2a equal in number to the wafers 3, and the positioning holes 2a are provided at positions opposite to the bosses 5 a. When in use, each boss 5a corresponds to one wafer 3, and each positioning hole 2a corresponds to one wafer 3.
Fig. 4 is a schematic structural view of a plasma processing apparatus according to still another embodiment of the present invention. As shown in fig. 4, in the present embodiment, the dc power supply 14 includes a first dc power supply 14a and a second dc power supply 14b, and the first dc power supply 14a and the second dc power supply 14b include a positive output terminal (HV +), a negative output terminal (HV-) and a Common Terminal (CT), respectively. The tray electrode is electrically connected to the negative output terminal (HV-) of the first DC power supply' 14a, and the Common Terminal (CT) of the first DC power supply 14a is grounded. The chuck electrode is electrically connected to the negative output terminal (HV-) of the second DC power supply 14b, and the Common Terminal (CT) of the second DC power supply 14b is grounded. Alternatively, the tray electrode is electrically connected to the positive output terminal (HV +) of the first dc power supply 14a, and the Common Terminal (CT) of the first dc power supply 14a is grounded. The chuck electrode is electrically connected to a positive output terminal (HV +) or a negative output terminal (HV-) of the second dc power supply 14b, and a Common Terminal (CT) of the second dc power supply 14b is grounded. The structural design of the double direct current power supplies can generate electrostatic attraction between the tray and the wafer and between the tray and the chuck as long as the output values of the direct current power supplies of the two power supplies are respectively controlled to ensure that certain voltage differences exist between the tray electrode and the wafer and between the tray electrode and the chuck electrode.
The first filter circuit 13a is arranged between the tray electrode and the first direct current power supply 14a, the second filter circuit 13b is connected between the chuck electrode and the second direct current power supply 14b in series, and the first filter circuit 13a and the second filter circuit 13b can prevent radio frequency energy from leaking through a loop to cause radio frequency energy attenuation and avoid causing radio frequency interference to other devices. The first filter circuit 14a and the second filter circuit 13b may also adopt filter circuits of other structures described in the above embodiments. The structures of other components not mentioned in this embodiment are the same as those of components corresponding to the above embodiments, and all of the components can be used in this embodiment, and are not described herein again.
In the plasma processing apparatus provided in the above embodiment, a tray electrode is disposed in the tray, a chuck electrode is disposed in the chuck, voltage differences are respectively generated between the tray electrode and the chuck electrode and between the tray electrode and the wafer by a dc power supply, and an electrostatic attraction is generated between the tray and the chuck by the voltage difference between the tray electrode and the chuck electrode, so that the tray is fixed on the carrying surface of the chuck; the voltage difference between the tray electrode and the wafer causes the electrostatic attraction between the tray and the wafer, so that the wafer is fixed on the carrying surface of the tray; namely, the wafer and the tray are respectively fixed on the tray and the chuck in an electrostatic adsorption mode, so that a mechanical pressure ring is avoided, the design is simple, the structure is simplified, and the manufacturing cost of the plasma processing equipment is reduced; the operation is simple, and the processing efficiency of the plasma processing equipment can be improved; and the secondary reliability is high, the damage is not easy to occur, the maintenance cost is reduced, and the utilization rate of the plasma processing equipment can be improved. In addition, the wafer and the tray are fixed in an electrostatic adsorption mode, so that the refrigerant gas can be effectively prevented from leaking, and the temperature of the wafer is effectively managed. In addition, the first capacitor and the second capacitor are connected in parallel, so that the power of a direct current power supply can be effectively utilized, the electrostatic attraction between the tray and the wafer and the electrostatic attraction between the tray and the chuck can be maximized, on one hand, the adsorption effect of the wafer and the tray is improved, the wafer and the tray are better fixed, and the leakage of refrigerant gas is prevented; on the other hand, the electrostatic attraction of the same magnitude is generated, and the voltage provided by the direct current power supply is required to be minimized, so that the voltage-resistant grade of the tray and the chuck is reduced, and the cost of the tray and the chuck is further reduced.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (30)
1. A plasma processing apparatus includes a reaction chamber, an upper excitation RF power source for providing energy for generating a plasma, a DC power source, and a wafer support device;
the wafer supporting device is arranged in the reaction chamber and comprises a tray for bearing a wafer and a chuck for bearing the tray;
the plasma processing device is characterized in that a tray electrode is arranged in the tray, the chuck electrode is grounded, the chuck electrode is arranged in the chuck, the tray and the chuck are mutually electrically insulated and are electrically insulated from plasma, and the direct-current power source is used for respectively generating voltage differences between the tray electrode and the chuck electrode and between the tray electrode and the wafer; and forming a first capacitor between the wafer and the tray electrode, and a second capacitor between the tray electrode and the chuck electrode, the first capacitor and the second capacitor being connected in parallel, thereby fixing the tray to the upper surface of the chuck.
2. The plasma processing apparatus as recited in claim 1 wherein said dc power source comprises a dc power source, said dc power source including a positive output terminal and a negative output terminal, said positive output terminal being electrically connected to said tray electrode, said negative output terminal being connected to ground; or the negative electrode output end is electrically connected with the tray electrode, and the positive electrode output end is grounded.
3. The plasma processing apparatus as recited in claim 1 wherein said dc power source comprises a dc power source, said dc power source including a positive output terminal, a negative output terminal, and a common terminal, said tray electrode being electrically connected to said positive output terminal of said dc power source or said negative output terminal of said dc power source, said common terminal being connected to ground.
4. The plasma processing apparatus as recited in claim 1 wherein said dc power source comprises a dc power source, said dc power source including a positive output terminal and a common terminal, said positive output terminal being electrically connected to said tray electrode, said common terminal being grounded;
or the direct current power supply comprises a negative output end and a public end, the negative output end is electrically connected with the tray electrode, and the public end is grounded.
5. The plasma processing apparatus as claimed in any of claims 2 to 4, wherein a filter circuit is connected in series between the tray electrode and the DC power supply.
6. The plasma processing apparatus of claim 5, wherein the filter circuit is a high frequency resistor.
7. The plasma processing apparatus of claim 5, wherein the filter circuit is a filter circuit having a radio frequency attenuation of less than-10 dB.
8. The plasma processing apparatus as claimed in claim 7, wherein the filter circuit comprises n inductors and n capacitors, wherein n of the inductors are connected in series, n of the capacitors are connected in parallel, the capacitors are connected in parallel with the inductors, and one end of the capacitors is grounded, wherein n is an integer greater than or equal to 1.
9. The plasma processing apparatus of claim 1 wherein said dc power source comprises a first dc power source and a second dc power source, said first dc power source and said second dc power source each comprising a positive output, a negative output, and a common terminal, said tray electrode being electrically connected to said positive output or said negative output of said first dc power source, said chuck electrode being electrically connected to said positive output or said negative output of said second dc power source, said common terminal of said first dc power source and said common terminal of said second dc power source both being grounded.
10. The plasma processing apparatus as recited in claim 9 wherein filter circuits are connected in series between said tray electrode and said dc power source and between said chuck electrode and said dc power source, respectively.
11. The plasma processing apparatus of claim 10 wherein the filter circuit is a high frequency resistor.
12. The plasma processing apparatus as recited in claim 10 wherein said filter circuit is a filter circuit having a radio frequency attenuation of less than-10 dB.
13. The plasma processing apparatus as recited in claim 12 wherein said filter circuit comprises n inductors and n capacitors, wherein n of said inductors are connected in series and n of said capacitors are connected in parallel, wherein said capacitors are connected in parallel with said inductors, and wherein one end of said capacitors is grounded, and wherein n is an integer greater than or equal to 1.
14. The plasma processing apparatus as claimed in claim 1, wherein the tray comprises a tray body and an insulating layer, the tray body is made of a conductive material, the insulating layer covers an outer surface of the tray body, and the tray body serves as the tray electrode;
the chuck comprises a chuck body and an insulating layer, wherein the chuck body is made of a conductive material, the insulating layer coats the outer surface of the chuck body, and the chuck body serves as a chuck electrode.
15. The plasma processing apparatus as claimed in claim 14, wherein the insulating layer is obtained by spraying an insulating material; or an aluminum oxide layer obtained by means of anodic oxidation.
16. The plasma processing apparatus of claim 15, wherein the insulating material comprises quartz or a ceramic or metal oxide.
17. The plasma processing apparatus as recited in claim 1 wherein a first chuck coolant passage is provided in said chuck, said first coolant medium cooling said chuck via said first chuck coolant passage.
18. The plasma processing apparatus as recited in claim 17 wherein said first coolant medium is a coolant liquid.
19. The plasma processing apparatus as recited in claim 18 wherein said coolant liquid is a fluorine coolant.
20. The plasma processing apparatus as claimed in claim 1, wherein a second chuck coolant passage is further provided in the chuck through a thickness direction thereof, and a chuck ring groove is provided on a carrying surface of the chuck, the chuck ring groove communicating with the second chuck coolant passage;
the wafer cooling device comprises a tray, a tray ring groove, a chuck ring groove, a tray refrigerant channel and a tray cooling medium channel, wherein the tray refrigerant channel penetrating through the thickness direction of the tray is arranged in the tray, the lower surface of the tray is provided with the tray ring groove, the tray ring groove is opposite to the chuck ring groove in position, the tray refrigerant channel is communicated with the chuck ring groove, and the second cooling medium is supplied to the back of a wafer through the second chuck refrigerant channel, the chuck ring groove, the tray ring groove and the tray refrigerant channel in sequence so as to cool the wafer.
21. The plasma processing apparatus as recited in claim 20 wherein said second coolant medium is a coolant gas.
22. The plasma processing apparatus as recited in claim 21 wherein said coolant gas is helium.
23. The plasma processing apparatus of claim 1, wherein the lower surface of the tray has a dimension that is no less than a dimension of the load-bearing surface of the chuck.
24. The plasma processing apparatus of claim 1, wherein a dielectric window is disposed at a top of the reaction chamber, and the upper electrode comprises an inductive coupling coil disposed above the dielectric window.
25. The plasma processing apparatus of claim 1 including a lower rf power source coupled to said chuck electrode for generating a dc self-bias voltage on the wafer surface to attract plasma for processing the wafer surface.
26. The plasma processing apparatus of claim 25 wherein said upper excitation rf power source and said lower rf power source are two separate rf power sources or two separate rf powers output by one rf power source.
27. The plasma processing apparatus as claimed in claim 1, wherein the carrying surface of the tray is provided with a boss, and the wafer is placed on a top end of the boss;
the wafer processing device is characterized by further comprising a cover plate, wherein the cover plate is stacked on the bearing surface of the tray, a positioning hole is formed in the cover plate, the positioning hole is opposite to the boss, and the processed surface of the wafer is exposed to the plasma through the positioning hole.
28. The plasma processing apparatus of claim 27, wherein the cover plate is fabricated from a quartz or ceramic material.
29. The plasma processing apparatus according to claim 1, wherein the plasma processing apparatus is an ICP plasma dry etcher or an ITO physical vapor deposition apparatus.
30. The plasma processing apparatus as recited in claim 1 wherein said wafer is made of sapphire, silicon or silicon oxide.
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| KR20160145070A (en) * | 2014-04-08 | 2016-12-19 | 플라스마 이그나이터, 엘엘씨 | Dual signal coaxial cavity resonator plasma generation |
| US9355776B2 (en) * | 2014-04-09 | 2016-05-31 | Applied Materials, Inc. | Capacitor assemblies for coupling radio frequency (RF) and direct current (DC) energy to one or more common electrodes |
| CN105088167B (en) * | 2014-05-20 | 2018-01-09 | 北京北方华创微电子装备有限公司 | Bogey, reaction chamber and semiconductor processing equipment |
| CN106531679B (en) * | 2015-09-10 | 2019-10-08 | 北京北方华创微电子装备有限公司 | Bogey and reaction chamber |
| CN106548969B (en) * | 2015-09-22 | 2019-08-23 | 北京北方华创微电子装备有限公司 | Clamping device and semiconductor processing equipment |
| WO2019036525A2 (en) | 2017-08-14 | 2019-02-21 | Component Re-Engineering Company, Inc. | Method for joining quartz pieces and quartz electrodes and other devices of joined quartz |
| CN110416144B (en) * | 2018-04-27 | 2020-11-10 | 北京北方华创微电子装备有限公司 | Electrostatic chuck, process chamber and semiconductor processing equipment |
| CN110491819B (en) * | 2018-05-14 | 2021-11-12 | 北京北方华创微电子装备有限公司 | Method for balancing electrostatic force and electrostatic chuck |
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Also Published As
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| CN103594315A (en) | 2014-02-19 |
| TWI521639B (en) | 2016-02-11 |
| WO2014026593A1 (en) | 2014-02-20 |
| TW201407714A (en) | 2014-02-16 |
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Address after: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |