TW201407714A - Plasma processing apparatus - Google Patents
Plasma processing apparatus Download PDFInfo
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- TW201407714A TW201407714A TW102128618A TW102128618A TW201407714A TW 201407714 A TW201407714 A TW 201407714A TW 102128618 A TW102128618 A TW 102128618A TW 102128618 A TW102128618 A TW 102128618A TW 201407714 A TW201407714 A TW 201407714A
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- tray
- chuck
- electrode
- processing apparatus
- plasma processing
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- 238000012545 processing Methods 0.000 title claims abstract description 52
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 230000005284 excitation Effects 0.000 claims abstract description 10
- 239000003507 refrigerant Substances 0.000 claims description 52
- 239000003990 capacitor Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 32
- 239000011810 insulating material Substances 0.000 claims description 22
- 238000001816 cooling Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000007743 anodising Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 2
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims 1
- 229910000457 iridium oxide Inorganic materials 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 79
- 238000001179 sorption measurement Methods 0.000 description 18
- 238000000034 method Methods 0.000 description 14
- 239000007789 gas Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Analytical Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
本發明屬於半導體加工領域,具體涉及一種等離子體加工設備。 The invention belongs to the field of semiconductor processing, and in particular relates to a plasma processing apparatus.
等離子體加工設備是加工半導體器件的常用設備。而且,為了提高等離子體加工設備的加工效率,常將多片尺寸較小的晶片放置在尺寸較大的托盤表面,再將托盤放入等離子體處理腔室的卡盤的上表面,以對晶片進行加工處理。 Plasma processing equipment is a common device for processing semiconductor devices. Moreover, in order to improve the processing efficiency of the plasma processing apparatus, a plurality of wafers having a small size are often placed on the surface of the larger-sized tray, and then the tray is placed on the upper surface of the chuck of the plasma processing chamber to face the wafer. Processing.
在實際加工過程中,等離子體容易使晶片的溫度超過工藝所需的溫度,因此需要對晶片的溫度進行控制。傳統的溫度控制方式是向晶片的背面(即,與晶片的被加工面相對的那一面)吹送諸如氦氣等的冷媒氣體,並借助冷媒氣體對晶片的溫度進行調節。通常,為了將晶片固定在托盤上並防止冷媒氣體洩漏,一般是在晶片的被加工面上的邊緣區域內設置按壓單元,使其對晶片的邊緣區域施加朝向卡盤方向的作用力。然而在實際應用中,這種方法存在著實施麻煩、穩定性差、冷卻效果不理想等問題;另外,按壓單元需要佔據晶片的被加工面上的部分空間,這將減小晶片的有效加工面積。 In actual processing, the plasma tends to cause the temperature of the wafer to exceed the temperature required for the process, so the temperature of the wafer needs to be controlled. The conventional temperature control method is to blow a refrigerant gas such as helium gas to the back surface of the wafer (that is, the side opposite to the surface to be processed of the wafer), and adjust the temperature of the wafer by the refrigerant gas. Generally, in order to fix the wafer on the tray and prevent leakage of the refrigerant gas, a pressing unit is generally provided in the edge region of the surface to be processed of the wafer to apply a force toward the chuck region to the edge region of the wafer. However, in practical applications, this method has problems such as troublesome implementation, poor stability, and unsatisfactory cooling effect; in addition, the pressing unit needs to occupy a part of the space on the processed surface of the wafer, which will reduce the effective processing area of the wafer.
為此,相關技術人員開發了利用靜電吸附作用 來固定晶片的方法。圖1為現有的一種利用靜電吸附作用來固定晶片的等離子體加工設備的部分結構的剖面示意圖。如圖1所示,托盤102放置在托盤支撐台101的上表面,晶片S放置在托盤102的上表面。在托盤102內設有靜電吸附電極106,靜電吸附電極106通過彈簧式端子與ESC(ElectroStatic Chuck,靜電卡盤)用供電電源105電連接。在等離子體環境中,對靜電吸附電極106供電,在晶片S的上表面會形成一層導電層,使得晶片S和靜電吸附電極106之間存在電壓差,從而將晶片S固定在托盤102的上表面。在托盤102的上表面上的未被晶片S覆蓋的區域覆蓋有蓋板103。在蓋板103的上表面設置有機械壓環104,借助於該機械壓環104而將托盤102固定在托盤支撐台101的上表面。 To this end, the relevant technicians have developed the use of electrostatic adsorption. The method of fixing the wafer. 1 is a schematic cross-sectional view showing a part of a structure of a plasma processing apparatus for fixing a wafer by electrostatic adsorption. As shown in FIG. 1, the tray 102 is placed on the upper surface of the tray support table 101, and the wafer S is placed on the upper surface of the tray 102. The electrostatic adsorption electrode 106 is provided in the tray 102, and the electrostatic adsorption electrode 106 is electrically connected to the ESC (ElectroStatic Chuck) power supply source 105 via a spring type terminal. In the plasma environment, the electrostatic adsorption electrode 106 is supplied with power, and a conductive layer is formed on the upper surface of the wafer S such that a voltage difference exists between the wafer S and the electrostatic adsorption electrode 106, thereby fixing the wafer S to the upper surface of the tray 102. . An area on the upper surface of the tray 102 that is not covered by the wafer S is covered with a cover plate 103. A mechanical pressure ring 104 is provided on the upper surface of the cover plate 103, and the tray 102 is fixed to the upper surface of the tray support table 101 by means of the mechanical pressure ring 104.
儘管上述等離子體加工設備採用了靜電吸附方式將晶片S固定在托盤102的表面,但托盤102的固定卻仍需要採用機械壓環104,因此,圖1所示等離子體加工設備所用的晶片固定方式仍然不可避免地存在下述問題:結構複雜、製作成本高、操作麻煩、機械部件易損壞並因維修工作而影響等離子體加工設備的加工效率,等等。 Although the plasma processing apparatus uses the electrostatic adsorption method to fix the wafer S on the surface of the tray 102, the fixing of the tray 102 still requires the use of the mechanical pressure ring 104. Therefore, the wafer fixing method used in the plasma processing apparatus shown in FIG. Inevitably, there are problems in that the structure is complicated, the manufacturing cost is high, the operation is troublesome, the mechanical parts are easily damaged, and the processing efficiency of the plasma processing equipment is affected by the maintenance work, and the like.
為至少解決上述問題之一,本發明提供一種等離子體加工設備,其固定晶片和托盤的結構簡單,成本低,而且不易損壞。 In order to at least solve one of the above problems, the present invention provides a plasma processing apparatus which has a simple structure, a low cost, and is not easily damaged.
解決上述技術問題的所採用的技術方案是提供一種等離子體加工設備,包括反應腔室、激勵射頻電源、 直流電源,上電極以及與所述上電極彼此相對地設置在反應腔室內的晶片支撐裝置,所述上電極與所述激勵射頻電源連接以在所述反應腔室內產生等離子體,所述晶片支撐裝置包括承載晶片的托盤以及卡盤,在所述托盤內設有托盤電極,所述托盤放置於所述卡盤上且二者之間電絕緣,且所述托盤和所述卡盤均與等離子體電絕緣,所述托盤電極與所述直流電源的正極輸出端或負極輸出端電連接,所述卡盤內設有卡盤電極,所述卡盤電極接地,以使所述托盤和所述卡盤之間以及所述托盤和所述晶片之間均存在電壓差。 The technical solution adopted to solve the above technical problems is to provide a plasma processing apparatus, including a reaction chamber, an excitation RF power source, a DC power source, an upper electrode, and a wafer supporting device disposed opposite to the upper electrode in the reaction chamber, the upper electrode being coupled to the excitation RF power source to generate a plasma in the reaction chamber, the wafer support The apparatus includes a tray carrying a wafer and a chuck, wherein a tray electrode is disposed in the tray, the tray is placed on the chuck and electrically insulated therebetween, and the tray and the chuck are both plasma-assisted Electrically insulated, the tray electrode is electrically connected to a positive output terminal or a negative output terminal of the DC power source, a chuck electrode is disposed in the chuck, and the chuck electrode is grounded to make the tray and the There is a voltage difference between the chucks and between the tray and the wafer.
其中,所述直流電源包括正極輸出端、負極輸出端和公共端,所述公共端接地;或者,所述直流電源包括正極輸出端和公共端,所述公共端接地;或者,所述直流電源包括負極輸出端和公共端,所述公共端接地。 The DC power source includes a positive output terminal, a negative output terminal, and a common terminal, and the common terminal is grounded; or the DC power supply includes a positive output terminal and a common terminal, and the common terminal is grounded; or the DC power supply A negative output terminal and a common terminal are included, and the common terminal is grounded.
其中,所述直流電源包括正極輸出端和負極輸出端,所述托盤電極與所述直流電源的正極輸出端電連接,所述負極輸出端接地;或者,所述托盤電極與所述直流電源的負極輸出端電連接,所述正極輸出端接地。 The DC power supply includes a positive output terminal and a negative output terminal, the tray electrode is electrically connected to a positive output terminal of the DC power source, and the negative output terminal is grounded; or the tray electrode and the DC power source are The negative output terminal is electrically connected, and the positive output terminal is grounded.
其中,在所述托盤電極和所述直流電源之間串接有濾波電路;和/或,在所述卡盤電極與地之間串接有濾波電路。 Wherein, a filter circuit is connected in series between the tray electrode and the DC power source; and/or a filter circuit is connected in series between the chuck electrode and the ground.
其中,所述濾波電路為高頻高壓電阻。 Wherein, the filter circuit is a high frequency high voltage resistor.
其中,所述濾波電路為射頻衰減小於-10dB的濾波電路。 The filter circuit is a filter circuit with a radio frequency attenuation of less than -10 dB.
其中,包括n個電感和n個電容,所述n個電 感串聯,所述n個電容並聯,所述n個電感串聯後再與所述n個電容並聯,並且所述n個電容並聯後的一端接地,n1的整數。 Wherein, comprising n inductors and n capacitors, the n inductors are connected in series, the n capacitors are connected in parallel, the n inductors are connected in series and then connected in parallel with the n capacitors, and the n capacitors are connected in parallel One end is grounded, n An integer of 1.
其中,所述托盤採用導電材料製作,並在所述導電材料的表面包覆絕緣材料,所述導電材料作為所述托盤電極;所述卡盤採用導電材料製作,並在所述導電材料的表面包覆絕緣材料,所述導電材料作為所述卡盤電極。 Wherein the tray is made of a conductive material, and the surface of the conductive material is coated with an insulating material as the tray electrode; the chuck is made of a conductive material and is on the surface of the conductive material An insulating material is coated, the conductive material serving as the chuck electrode.
其中,所述絕緣材料在所述導電材料的表面形成絕緣層。 Wherein the insulating material forms an insulating layer on a surface of the conductive material.
其中,所述絕緣層是通過噴塗或陽極氧化的方式形成於導電材料表面。 Wherein, the insulating layer is formed on the surface of the conductive material by spraying or anodizing.
其中,所述托盤採用絕緣材料製作,並在所述絕緣材料內部埋設托盤電極,所述托盤電極採用導電材料製作;所述卡盤採用絕緣材料製作,並在所述絕緣材料內部埋設卡盤電極,所述卡盤電極採用導電材料製作。 Wherein the tray is made of an insulating material, and a tray electrode is embedded inside the insulating material, the tray electrode is made of a conductive material; the chuck is made of an insulating material, and a chuck electrode is embedded inside the insulating material. The chuck electrode is made of a conductive material.
其中,在所述卡盤內設有用於冷卻卡盤的第一卡盤冷媒通道,在所述第一卡盤冷媒通道內通入第一冷媒介質對所述卡盤進行冷卻。 Wherein, a first chuck refrigerant passage for cooling the chuck is disposed in the chuck, and the chuck is cooled by passing a first cold medium in the first chuck refrigerant passage.
其中,在所述卡盤內還設有貫穿其厚度方向的第二卡盤冷媒通道,在所述卡盤的上表面設有卡盤環形凹槽,所述卡盤環形凹槽與所述第二卡盤冷媒通道連通;在所述托盤內設有貫穿其厚度方向的托盤冷媒通道,所述托盤冷媒通道與所述卡盤環形凹槽連通,第二冷媒介質依次經由第二卡盤冷媒通道、卡盤環形凹槽以及托盤冷媒通道供給到晶片的背面,以對晶片進行冷卻。 The second chuck refrigerant passage extending through the thickness direction thereof is further disposed in the chuck, and a chuck annular groove is disposed on the upper surface of the chuck, the chuck annular groove and the first The two chucks are connected to the refrigerant passage; the tray is provided with a tray refrigerant passage extending through the thickness direction thereof, the tray refrigerant passage is in communication with the chuck annular groove, and the second cold medium is sequentially passed through the second chuck refrigerant passage The chuck annular groove and the tray refrigerant channel are supplied to the back side of the wafer to cool the wafer.
其中,離子體加工設備還包括蓋板,所述蓋板置於所述托盤的承載面上,在所述蓋板內設有貫穿其厚度的定位孔,所述蓋板用於保護托盤承載面上未放置晶片的區域免受等離子體的轟擊;在所述托盤的承載面且與所述定位孔相對位置設有凸台,所述晶片設置在所述凸台的頂端。 Wherein, the ion processing apparatus further includes a cover plate, the cover plate is disposed on the bearing surface of the tray, and a positioning hole penetrating the thickness thereof is disposed in the cover plate, and the cover plate is used for protecting the tray bearing surface The area on which the wafer is not placed is protected from plasma bombardment; a boss is provided on the carrying surface of the tray and opposite to the positioning hole, and the wafer is disposed at the top end of the boss.
其中,所述等離子體加工設備為LED刻蝕機或者ITO物理氣相沉積設備。 Wherein, the plasma processing equipment is an LED etching machine or an ITO physical vapor deposition equipment.
其中,所述晶片的材質為藍寶石、矽或氧化矽。 Wherein, the material of the wafer is sapphire, ruthenium or ruthenium oxide.
本發明具有以下有益效果:本發明提供的等離子體加工設備,將托盤放置於卡盤的上表面,托盤和卡盤之間電絕緣,且托盤和卡盤均與等離子體電絕緣,在所述托盤內設有托盤電極,所述卡盤內設有卡盤電極,托盤電極與直流電源的正極輸出端或負極輸出端電連接,卡盤電極接地,以使托盤和卡盤之間存在電壓差,即,在托盤和卡盤之間產生靜電吸附力,從而將托盤固定於卡盤的上表面;以及使托盤和晶片之間存在電壓差,即,在托盤和晶片之間產生靜電吸附力,從而將晶片固定在托盤的上表面,這種固定晶片和托盤的方式不僅容易操作、可靠性高,而且還具有結構簡單、成本低、不易損壞等優點。 The present invention has the following beneficial effects: the plasma processing apparatus provided by the present invention places a tray on the upper surface of the chuck, electrically insulated between the tray and the chuck, and the tray and the chuck are electrically insulated from the plasma, A tray electrode is disposed in the tray, and the chuck electrode is provided in the chuck, the tray electrode is electrically connected to the positive output terminal or the negative output terminal of the DC power source, and the chuck electrode is grounded to cause a voltage difference between the tray and the chuck , that is, an electrostatic attraction force is generated between the tray and the chuck to fix the tray to the upper surface of the chuck; and a voltage difference exists between the tray and the wafer, that is, electrostatic attraction is generated between the tray and the wafer, Thereby, the wafer is fixed on the upper surface of the tray, and the method of fixing the wafer and the tray is not only easy to operate, but also has high reliability, and has the advantages of simple structure, low cost, and not easy to be damaged.
10‧‧‧等離子體 10‧‧‧ Plasma
12‧‧‧第一匹配器 12‧‧‧First matcher
13‧‧‧激勵射頻電源 13‧‧‧Incentive RF power supply
17‧‧‧第二匹配器 17‧‧‧Second matcher
18‧‧‧偏壓射頻電源 18‧‧‧Bias RF power supply
20‧‧‧反應腔室 20‧‧‧Reaction chamber
21‧‧‧托盤 21‧‧‧Tray
21a‧‧‧托盤冷媒通道 21a‧‧‧Tray refrigerant channel
21c‧‧‧凸台 21c‧‧‧ boss
23‧‧‧卡盤 23‧‧‧ chuck
23a‧‧‧第一卡盤冷媒通道 23a‧‧‧First Chuck Refrigerant Channel
23b‧‧‧第二卡盤冷媒通道 23b‧‧‧Second chuck refrigerant channel
24‧‧‧直流電源 24‧‧‧DC power supply
25‧‧‧蓋板 25‧‧‧ Cover
25a‧‧‧定位孔 25a‧‧‧Positioning holes
27‧‧‧介質窗 27‧‧‧Media window
30、30’、30”‧‧‧濾波電路 30, 30', 30" ‧ ‧ filter circuit
101‧‧‧托盤支撐台 101‧‧‧Tray support table
102‧‧‧托盤 102‧‧‧Tray
103‧‧‧蓋板 103‧‧‧ Cover
104‧‧‧機械壓環 104‧‧‧Mechanical pressure ring
105‧‧‧ESC用供電電源 105‧‧‧ESC power supply
106‧‧‧靜電吸附電極 106‧‧‧Electrostatic adsorption electrode
A‧‧‧卡盤環形凹槽 A‧‧‧ chuck ring groove
B‧‧‧托盤環形凹槽 B‧‧‧Tray ring groove
S‧‧‧晶片 S‧‧‧ wafer
L21‧‧‧第一濾波電感 L21‧‧‧First filter inductor
C21‧‧‧第一濾波電容 C21‧‧‧First filter capacitor
L22‧‧‧第二濾波電感 L22‧‧‧Second filter inductor
C22‧‧‧第二濾波電容 C22‧‧‧Second filter capacitor
圖1為現有的一種利用靜電吸附作用來固定晶片的等離子體加工設備的部分結構的剖面示意圖; 圖2為本發明實施例提供的等離子體加工設備的部分結構的剖面示意圖;圖3為本發明實施例提供的另一濾波電路的原理圖;圖4為本發明另一實施例提供的等離子體加工設備的部分結構的剖面示意圖。 1 is a schematic cross-sectional view showing a part of a structure of a plasma processing apparatus for fixing a wafer by electrostatic adsorption; 2 is a schematic cross-sectional view showing a part of a structure of a plasma processing apparatus according to an embodiment of the present invention; FIG. 3 is a schematic diagram of another filter circuit according to an embodiment of the present invention; A schematic cross-sectional view of a portion of the structure of the processing equipment.
為使本領域的技術人員更好地理解本發明的技術方案,下面結合附圖對本發明實施例提供的等離子體加工設備進行詳細描述。 In order to enable those skilled in the art to better understand the technical solutions of the present invention, the plasma processing apparatus provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
請參閱圖2,其為本發明實施例提供的等離子體加工設備的部分結構的剖面示意圖。如圖2所示,該等離子體加工設備包括反應腔室20,反應腔室20接地。在反應腔室20內的底部設有卡盤23,用於承載晶片S的托盤21放置在卡盤23的上表面。在反應腔室20的外部設有直流電源24和激勵射頻電源,其中,激勵射頻電源用於激發等離子體10,直流電源24用於提供固定晶片S和托盤21的能量。 Please refer to FIG. 2 , which is a cross-sectional view showing a partial structure of a plasma processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the plasma processing apparatus includes a reaction chamber 20 to which the reaction chamber 20 is grounded. A chuck 23 is provided at the bottom in the reaction chamber 20, and a tray 21 for carrying the wafer S is placed on the upper surface of the chuck 23. A DC power source 24 and an excitation RF power source are provided outside the reaction chamber 20, wherein the RF power source is energized for exciting the plasma 10, and the DC power source 24 is used to supply energy for fixing the wafer S and the tray 21.
在本實施例中,卡盤23主要採用金屬等導電材料製作,且在導電材料的表面形成有絕緣層。導電材料作為卡盤電極(或稱卡盤靜電吸附電極)使用。絕緣層由絕緣材料製作,絕緣層可以通過噴塗或陽極氧化等方式形成於導電材料表面。在導電材料的表面設置絕緣材料的目的是為了實現卡盤23與托盤21之間電絕緣,以及使卡盤23與反應腔室20內的等離子體10之間電絕緣。 In the present embodiment, the chuck 23 is mainly made of a conductive material such as metal, and an insulating layer is formed on the surface of the conductive material. The conductive material is used as a chuck electrode (or a chuck electrostatic adsorption electrode). The insulating layer is made of an insulating material, and the insulating layer can be formed on the surface of the conductive material by spraying or anodizing. The purpose of providing an insulating material on the surface of the electrically conductive material is to achieve electrical insulation between the chuck 23 and the tray 21 and to electrically insulate the chuck 23 from the plasma 10 within the reaction chamber 20.
托盤21主要採用金屬等導電材料製作,且在 導電材料的表面形成有絕緣層。絕緣層由絕緣材料製作,絕緣層可以通過噴塗或陽極氧化等方式形成於導電材料表面。導電材料作為托盤電極(或稱托盤靜電吸附電極)使用。與卡盤23類似,在導電材料的表面設置絕緣材料的目的是為了實現托盤21與卡盤23之間電絕緣,以及使托盤21與反應腔室20內的等離子體10之間電絕緣。 The tray 21 is mainly made of a conductive material such as metal, and The surface of the conductive material is formed with an insulating layer. The insulating layer is made of an insulating material, and the insulating layer can be formed on the surface of the conductive material by spraying or anodizing. The conductive material is used as a tray electrode (or a tray electrostatic adsorption electrode). Similar to the chuck 23, the purpose of providing an insulating material on the surface of the conductive material is to achieve electrical insulation between the tray 21 and the chuck 23, and to electrically insulate the tray 21 from the plasma 10 in the reaction chamber 20.
在另一實施例中,卡盤23也可以主要採用絕緣材料製作,並在絕緣材料內部埋設由金屬等導電材料製作而成的卡盤電極。類似地,托盤21也可以主要採用絕緣材料製作,並在絕緣材料內部埋設由金屬等導電材料製作而成的托盤電極。 In another embodiment, the chuck 23 may be mainly made of an insulating material, and a chuck electrode made of a conductive material such as metal may be embedded in the insulating material. Similarly, the tray 21 may be mainly made of an insulating material, and a tray electrode made of a conductive material such as metal may be embedded in the insulating material.
其中,上述實施例中的卡盤靜電吸附電極和托盤靜電吸附電極所採用的導電材料可以是鋁等金屬材料,絕緣材料可以是石英或陶瓷等。 The conductive material used for the chuck electrostatic adsorption electrode and the tray electrostatic adsorption electrode in the above embodiment may be a metal material such as aluminum, and the insulating material may be quartz or ceramic.
在本實施例中,直流電源24包括正極接線端、負極接線端以及公共端(或稱之為中間點CT),而且公共端直接接地,或者公共端經由機殼而接地。托盤電極與直流電源24的負極接線端電連接;卡盤電極與直流電源24的公共端電連接,或者直接接地。當然,托盤電極也可以與直流電源24的正極接線端電連接;卡盤與直流電源24的公共端電連接,或者直接接地。 In the present embodiment, the DC power source 24 includes a positive terminal, a negative terminal, and a common terminal (or referred to as an intermediate point CT), and the common terminal is directly grounded, or the common terminal is grounded via the casing. The tray electrode is electrically connected to the negative terminal of the DC power source 24; the chuck electrode is electrically connected to the common terminal of the DC power source 24, or directly grounded. Of course, the tray electrode can also be electrically connected to the positive terminal of the DC power source 24; the chuck is electrically connected to the common terminal of the DC power source 24, or directly grounded.
在等離子體環境中,晶片S的表面形成一層導電層,直流電源24向托盤電極提供電能,以使托盤21和晶片S之間存在電壓差,並在托盤21和晶片S之間產生靜電吸附力,以將晶片S固定於托盤21的上表面。同時,使 托盤21和卡盤23之間存在電壓差,並在托盤21和卡盤23之間產生靜電吸附力,以將托盤21固定於卡盤23的上表面。 In the plasma environment, the surface of the wafer S forms a conductive layer, and the DC power source 24 supplies electric power to the tray electrodes to cause a voltage difference between the tray 21 and the wafer S, and electrostatic attraction between the tray 21 and the wafer S. To fix the wafer S to the upper surface of the tray 21. At the same time, make There is a voltage difference between the tray 21 and the chuck 23, and an electrostatic attraction force is generated between the tray 21 and the chuck 23 to fix the tray 21 to the upper surface of the chuck 23.
本實施例在直流電源24與托盤電極之間還可以串接一濾波電路30,用以避免射頻能量通過回路外泄而造成射頻能量衰減,以及避免對其他器件造成射頻干擾。該濾波電路30具有第一接線端和第二接線端,其中,該濾波電路30的第一接線端指的是該濾波電路30與托盤電極相連接的那一端;濾波電路30的第二接線端指的是該濾波電路30與直流電源24相連接的那一端。如圖2所示,該濾波電路30包括第一濾波電感L21和第一濾波電容C21,第一濾波電感L21的一端作為濾波電路30的第一接線端與托盤電極連接,另一端作為濾波電路30的第二接線端與直流電源24的負極連接。第一濾波電容C21的一端接地,另一端與濾波電路的第二接線端及直流電源24的負極相連接。 In this embodiment, a filter circuit 30 can be connected in series between the DC power source 24 and the tray electrode to avoid RF energy attenuation caused by leakage of RF energy through the loop, and to avoid radio frequency interference to other devices. The filter circuit 30 has a first terminal and a second terminal, wherein the first terminal of the filter circuit 30 refers to the end of the filter circuit 30 connected to the tray electrode; the second terminal of the filter circuit 30 It refers to the end of the filter circuit 30 that is connected to the DC power source 24. As shown in FIG. 2, the filter circuit 30 includes a first filter inductor L21 and a first filter capacitor C21. One end of the first filter inductor L21 is connected to the tray electrode as a first terminal of the filter circuit 30, and the other end serves as a filter circuit 30. The second terminal is connected to the negative terminal of the DC power source 24. One end of the first filter capacitor C21 is grounded, and the other end is connected to the second terminal of the filter circuit and the cathode of the DC power source 24.
類似地,本實施例中也可以在卡盤電極和地(或者直流電源24的公共端)之間串接一濾波電路30’,該濾波電路30’具有第一接線端和第二接線端,其中,該濾波電路30’的第一接線端指的是該濾波電路30’與卡盤電極相連接的那一端;濾波電路30’的第二接線端指的是該濾波電路30’與地(或者直流電源24)相連接的那一端。如圖2所示,該濾波電路30’包括第二濾波電感L22和第二濾波電容C22,並且第二濾波電感L22和第二濾波電容C22與卡盤電極和地(或者直流電源24的公共端)的連接 方式類似于上文介紹的第一濾波電感L21和第一濾波電容C21與托盤電極和直流電源24的負極的連接方式,在此不再贅述。 Similarly, in the embodiment, a filter circuit 30' may be connected in series between the chuck electrode and the ground (or the common end of the DC power source 24), and the filter circuit 30' has a first terminal and a second terminal. Wherein, the first terminal of the filter circuit 30' refers to the end of the filter circuit 30' connected to the chuck electrode; the second terminal of the filter circuit 30' refers to the filter circuit 30' and the ground ( Or the end of the DC power supply 24). As shown in FIG. 2, the filter circuit 30' includes a second filter inductor L22 and a second filter capacitor C22, and a second filter inductor L22 and a second filter capacitor C22 are coupled to the chuck electrode and the ground (or the common terminal of the DC power source 24). )Connection The manner is similar to the manner in which the first filter inductor L21 and the first filter capacitor C21 are connected to the negative electrode of the tray electrode and the DC power source 24, and details are not described herein again.
在另一實施例中,可以採用圖3所示的濾波電路30”來替代圖2中的濾波電路30。該濾波電路30”同樣具有第一接線端和第二接線端,其中,該濾波電路30”的第一接線端指的是該濾波電路30”與托盤電極相連接的那一端;濾波電路30”的第二接線端指的是該濾波電路30”與直流電源24相連接的那一端。如圖3所示,本實施例中的濾波電路30”包括第一濾波電感L21、第二濾波電感L22、第一濾波電容C21和第二濾波電容C22,其中,第一濾波電感L21和第二濾波電感L22串聯,並且第一濾波電感L21和第二濾波電感L22彼此不互相連接的那一端分別作為該濾波電路30”的第一接線端和第二接線端,並分別連接托盤電極和直流電源24的負極。第一濾波電容C21和第二濾波電容C22並聯,第一濾波電容C21和第二濾波電容C22的一端接地,另一端連接濾波電路30”的第二接線端。實際上,只要濾波電路包括n個電感和n個電容,n為1的整數,而且,n個電感串聯,n個電容並聯,並且n個電感串聯後再與n個電容並聯,且n個電容並聯後的一端接地,這種結構的濾波電路就均可用於防止射頻能量外泄。換言之,在實際應用中,可以採用這樣的濾波電路來替代圖2中的濾波電路30,即,該濾波電路包括n個電感和n個電容,且n個電感串聯,n個電容並聯,並且n個電感串聯後再與n個電容並聯,n個電容並聯後的一端接地, 其中,n為大於等於1的整數。 In another embodiment, the filter circuit 30" shown in FIG. 3 may be used instead of the filter circuit 30 of FIG. 2. The filter circuit 30" also has a first terminal and a second terminal, wherein the filter circuit The first terminal of 30" refers to the end of the filter circuit 30" that is connected to the tray electrode; the second terminal of the filter circuit 30" refers to the end of the filter circuit 30" that is connected to the DC power supply 24 . As shown in FIG. 3, the filter circuit 30" in this embodiment includes a first filter inductor L21, a second filter inductor L22, a first filter capacitor C21, and a second filter capacitor C22, wherein the first filter inductor L21 and the second The filter inductors L22 are connected in series, and the ends of the first filter inductor L21 and the second filter inductor L22 that are not connected to each other are respectively used as the first terminal and the second terminal of the filter circuit 30", and respectively connect the tray electrode and the DC power source. The negative pole of 24. The first filter capacitor C21 and the second filter capacitor C22 are connected in parallel. One end of the first filter capacitor C21 and the second filter capacitor C22 are grounded, and the other end is connected to the second terminal of the filter circuit 30". Actually, as long as the filter circuit includes n Inductance and n capacitors, n is An integer of 1 and, in addition, n inductors are connected in series, n capacitors are connected in parallel, and n inductors are connected in series and then connected in parallel with n capacitors, and one end of the parallel connection of n capacitors is grounded. The filter circuit of this structure can be used to prevent Radio frequency energy is leaked. In other words, in practical applications, a filter circuit may be employed instead of the filter circuit 30 of FIG. 2, that is, the filter circuit includes n inductors and n capacitors, and n inductors are connected in series, n capacitors are connected in parallel, and n The inductors are connected in series and then connected in parallel with n capacitors. One end of the n capacitors connected in parallel is grounded, where n is an integer greater than or equal to 1.
在實際應用中,上述實施例所採用的濾波電路需要滿足射頻衰減小於-10dB的條件。並且,儘管上文僅列舉了兩種形式的濾波電路:濾波電路30與濾波電路30’的組合以及濾波電路30”,但是本發明可採用的濾波電路並不局限於上述兩種形式,而是可以被構造成電感、電阻和電容的任意組合形式。當然,濾波電路也可以採用高頻高壓電阻。事實上,凡是能夠避免射頻能量通過回路外泄的濾波電路均可以應用于本發明。 In practical applications, the filter circuit used in the above embodiments needs to meet the condition that the radio frequency attenuation is less than -10 dB. Also, although only two types of filter circuits are listed above: the combination of the filter circuit 30 and the filter circuit 30' and the filter circuit 30", the filter circuit that can be employed in the present invention is not limited to the above two forms, but It can be constructed in any combination of inductance, resistance and capacitance. Of course, the filter circuit can also use high-frequency high-voltage resistors. In fact, any filter circuit capable of avoiding leakage of RF energy through the loop can be applied to the present invention.
在等離子體加工工藝過程中,晶片S、托盤21和卡盤23的溫度容易升高而影響薄膜的品質,因此,這就需要利用冷媒介質調節晶片S、托盤21和卡盤23的溫度。其中,冷媒介質既可以是冷媒液體,又可以是冷媒氣體。 During the plasma processing process, the temperatures of the wafer S, the tray 21, and the chuck 23 are easily increased to affect the quality of the film, and therefore, it is necessary to adjust the temperatures of the wafer S, the tray 21, and the chuck 23 by using a cold medium. Among them, the cold medium can be either a refrigerant liquid or a refrigerant gas.
在本實施例中,在卡盤23內設有用於冷卻卡盤23的第一卡盤冷媒通道23a。該第一卡盤冷媒通道23a可以設置成多個沿卡盤23的厚度方向延伸的盲孔的形式,並且所述盲孔的開口設置於卡盤23的底面;或者,該第一卡盤冷媒通道23a也可以設置成一個聯通的環形凹槽或者螺旋線形凹槽的形式。在工藝過程中,可以在第一卡盤冷媒通道23a內通入第一冷媒介質以對卡盤23進行冷卻。第一冷媒介質可以為冷媒液體,具體地,該冷媒液體可以是氟冷卻液。 In the present embodiment, a first chuck refrigerant passage 23a for cooling the chuck 23 is provided in the chuck 23. The first chuck refrigerant passage 23a may be disposed in the form of a plurality of blind holes extending in the thickness direction of the chuck 23, and the opening of the blind hole is disposed on the bottom surface of the chuck 23; or, the first chuck refrigerant The passage 23a can also be provided in the form of a communicating annular groove or a spiral groove. During the process, the first cold medium may be introduced into the first chuck refrigerant passage 23a to cool the chuck 23. The first cold medium may be a refrigerant liquid, and specifically, the refrigerant liquid may be a fluorine coolant.
在另一實施例中,在卡盤23內還設有多個沿厚度方向貫穿卡盤23且用作第二卡盤冷媒通道23b的卡盤通孔。並且,在托盤21內還設有多個沿厚度方向貫穿托盤 21且用作托盤冷媒通道21a的托盤通孔,在卡盤23的上表面(即,用於承載托盤21的承載面)形成有卡盤環形凹槽A,第二卡盤冷媒通道23b和托盤冷媒通道21a分別沿卡盤23的厚度方向和托盤21的厚度方向而延伸至該卡盤環形凹槽A,即,卡盤環形凹槽A將第二卡盤冷媒通道23b和托盤冷媒通道21a連通。這樣,在實際工藝過程中,第二冷媒介質依次經由第二卡盤冷媒通道23b、卡盤環形凹槽A以及托盤冷媒通道21a而供給到晶片S的背面,從而對晶片S進行冷卻。第二冷媒介質為冷媒氣體,冷媒氣體可以為氦氣等惰性氣體。 In another embodiment, a plurality of chuck through holes that penetrate the chuck 23 in the thickness direction and serve as the second chuck refrigerant passage 23b are provided in the chuck 23. Moreover, a plurality of trays are penetrated in the thickness direction in the tray 21 21 and used as a tray through hole of the tray refrigerant passage 21a, on the upper surface of the chuck 23 (i.e., the bearing surface for carrying the tray 21), a chuck annular groove A, a second chuck refrigerant passage 23b and a tray are formed. The refrigerant passages 21a extend to the chuck annular groove A in the thickness direction of the chuck 23 and the thickness direction of the tray 21, respectively, that is, the chuck annular groove A connects the second chuck refrigerant passage 23b and the tray refrigerant passage 21a. . Thus, in the actual process, the second cold medium is sequentially supplied to the back surface of the wafer S via the second chuck refrigerant passage 23b, the chuck annular groove A, and the tray refrigerant passage 21a, thereby cooling the wafer S. The second cold medium is a refrigerant gas, and the refrigerant gas may be an inert gas such as helium.
優選地,在托盤21的下表面形成有托盤環形凹槽B,托盤環形凹槽B與卡盤環形凹槽A相對,借助卡盤環形凹槽A和托盤環形凹槽B可以確保第二卡盤冷媒通道23b和托盤冷媒通道21a連通,並使第二冷媒介質更順利地進入托盤冷媒通道21a。 Preferably, a tray annular groove B is formed on the lower surface of the tray 21, the tray annular groove B is opposite to the chuck annular groove A, and the second chuck can be ensured by the chuck annular groove A and the tray annular groove B The refrigerant passage 23b communicates with the tray refrigerant passage 21a, and allows the second refrigerant medium to enter the tray refrigerant passage 21a more smoothly.
優選地,在卡盤23內設有多個與卡盤環形凹槽A連通的第二卡盤冷媒通道23b,在托盤21內設有多個托盤冷媒通道21a,這樣,借助多個第二卡盤冷媒通道23b和托盤冷媒通道21a,不僅可以更高效地調節溫度,而且可以提高卡盤23、托盤21及晶片S各自的溫度的均勻性。 Preferably, a plurality of second chuck refrigerant passages 23b communicating with the annular groove A of the chuck are provided in the chuck 23, and a plurality of tray refrigerant passages 21a are provided in the tray 21, so that a plurality of second cards are provided The disk refrigerant passage 23b and the tray refrigerant passage 21a can not only adjust the temperature more efficiently, but also improve the uniformity of the temperature of each of the chuck 23, the tray 21, and the wafer S.
在對晶片加工的過程中,裸露在等離子體10中的托盤21的表面部分(即,托盤21上的未被晶片S覆蓋的部分)容易受等離子體10的腐蝕。為此,本實施例提供的等離子體加工設備還包括蓋板25,蓋板25採用陶瓷或石英材料製作,其疊置在托盤21的承載面,並通過螺釘(圖 中未示出)與托盤21固定,螺釘採用陶瓷材料製作。在蓋板25內設有貫穿其厚度的定位孔25a,晶片S被嵌置在定位孔25a內。需要說明的是,由於蓋板25與托盤21疊置,定位孔25a的位置即為晶片S在托盤21表面的位置,因此設置在蓋板25上的定位孔25a有利於提高晶片S的裝載效率。不難理解,定位孔25a的內徑尺寸應等於或略大於晶片S的外徑尺寸。優選地,蓋板25的外徑尺寸等於或略大於托盤21的外徑尺寸,這樣可以將至少是托盤21的承載面中的裸露在等離子體10環境中的那一部分遮擋,從而避免等離子體10腐蝕托盤21。 The surface portion of the tray 21 exposed in the plasma 10 (i.e., the portion of the tray 21 not covered by the wafer S) is susceptible to corrosion by the plasma 10 during wafer processing. To this end, the plasma processing apparatus provided in this embodiment further includes a cover plate 25 made of ceramic or quartz material, which is stacked on the bearing surface of the tray 21 and passed through the screw (Fig. Not shown) is fixed to the tray 21, and the screw is made of a ceramic material. A positioning hole 25a penetrating the thickness thereof is provided in the cap plate 25, and the wafer S is embedded in the positioning hole 25a. It should be noted that, since the cover plate 25 is overlapped with the tray 21, the position of the positioning hole 25a is the position of the wafer S on the surface of the tray 21. Therefore, the positioning hole 25a disposed on the cover plate 25 is advantageous for improving the loading efficiency of the wafer S. . It is not difficult to understand that the inner diameter of the positioning hole 25a should be equal to or slightly larger than the outer diameter of the wafer S. Preferably, the outer diameter of the cover plate 25 is equal to or slightly larger than the outer diameter of the tray 21, so that at least a portion of the bearing surface of the tray 21 exposed in the plasma 10 environment can be blocked, thereby avoiding the plasma 10. The tray 21 is etched.
本實施例中,在托盤21的承載面上還設有凸台21c,凸台21c與定位孔25a相對,晶片S放置在凸台21c的頂端。為了使托盤21能夠承載多個晶片S,在托盤21的承載面設有多個凸台21c,對應地,在蓋板25內設置多個定位孔25a,定位孔25a的數量與凸台21c的數量相等。 In the present embodiment, a boss 21c is provided on the carrying surface of the tray 21, the boss 21c is opposed to the positioning hole 25a, and the wafer S is placed on the top end of the boss 21c. In order to enable the tray 21 to carry a plurality of wafers S, a plurality of bosses 21c are provided on the bearing surface of the tray 21. Correspondingly, a plurality of positioning holes 25a are provided in the cover plate 25, and the number of the positioning holes 25a and the boss 21c are The number is equal.
在本實施例中,托盤21下表面的直徑等於或略大於卡盤23上表面的直徑,以使托盤21能夠完全覆蓋住卡盤23並和卡盤23之間可靠密封,這樣不僅可以防止冷媒介質洩露,而且可以防止等離子體損傷卡盤23的上表面。 In the present embodiment, the diameter of the lower surface of the tray 21 is equal to or slightly larger than the diameter of the upper surface of the chuck 23, so that the tray 21 can completely cover the chuck 23 and be reliably sealed with the chuck 23, so that not only the refrigerant can be prevented. The medium leaks and the plasma is prevented from damaging the upper surface of the chuck 23.
在本實施例中,如圖2所示,上電極包括電感耦合線圈(圖中未示出),電感耦合線圈設置在介質窗27的上方,介質窗27設置在反應腔室20的頂部。電感耦合線圈通過第一匹配器12與激勵射頻電源13連接,偏壓射頻電源18通過第二匹配器17與卡盤23連接,激勵射頻電 源13向反應腔室20內輸入射頻能量,使工藝氣體被電離形成等離子體10。偏壓射頻電源18用於在晶片S表面產生射頻偏壓以吸引離子對晶片S的表面進行加工。 In the present embodiment, as shown in FIG. 2, the upper electrode includes an inductive coupling coil (not shown), the inductive coupling coil is disposed above the dielectric window 27, and the dielectric window 27 is disposed at the top of the reaction chamber 20. The inductive coupling coil is connected to the excitation RF power source 13 through the first matching unit 12, and the bias RF power source 18 is connected to the chuck 23 through the second matching unit 17, and the RF power is excited. Source 13 inputs RF energy into reaction chamber 20 to cause the process gas to be ionized to form plasma 10. The bias RF power source 18 is used to generate a radio frequency bias on the surface of the wafer S to attract ions to process the surface of the wafer S.
需要指出的是,儘管在上述實施例中,激勵射頻電源13和偏壓射頻電源18為兩個相互獨立的射頻電源。但本發明並不局限於此,在實際應用中,激勵射頻電源13和偏壓射頻電源18也可以採用一個射偏電源代替,但該射頻電源需設有兩個獨立的射頻功率輸出端。 It should be noted that although in the above embodiment, the excitation RF power source 13 and the bias RF power source 18 are two mutually independent RF power sources. However, the present invention is not limited thereto. In practical applications, the excitation RF power source 13 and the bias RF power source 18 may also be replaced by a polarization power supply, but the RF power supply needs to have two independent RF power output terminals.
需要說明的是,儘管在上述實施例中,直流電源24包括正極接線端、負極接線端以及公共端,且公共端接地或者公共端經由機殼接地;但是在實際應用中,直流電源24也可以採用其他結構。例如,直流電源24可以僅包括正極接線端和公共端,並且在使用時,將托盤電極與正極接線端連接,將卡盤電極與公共端連接或者直接接地。又如,直流電源24可以僅包括負極接線端和公共端,並且在使用時,將托盤電極與負極接線端連接,將卡盤電極與公共端連接或者直接接地。再如,直流電源24可以僅包括正極接線端和負極接線端,並且在使用時,將托盤電極與正極接線端連接,並且既可以將卡盤電極直接接地,又可以將卡盤電極接負極接線端並將負極接線端接地;或者,將托盤電極與負極接線端連接,並且既可以將卡盤電極直接接地,又可以將卡盤電極接正極接線端並將正極接線端接地。 It should be noted that, in the above embodiment, the DC power supply 24 includes a positive terminal, a negative terminal, and a common terminal, and the common terminal is grounded or the common terminal is grounded via the casing; but in practical applications, the DC power supply 24 can also be used. Adopt other structures. For example, the DC power source 24 may include only the positive terminal and the common terminal, and in use, connect the tray electrode to the positive terminal, connect the chuck electrode to the common terminal, or directly ground. As another example, the DC power source 24 can include only the negative terminal and the common terminal, and in use, connect the tray electrode to the negative terminal, connect the chuck electrode to the common terminal, or directly ground. For another example, the DC power source 24 may include only the positive terminal and the negative terminal, and in use, the tray electrode is connected to the positive terminal, and the chuck electrode may be directly grounded, and the chuck electrode may be connected to the negative terminal. The terminal is grounded to the negative terminal; or the tray electrode is connected to the negative terminal, and the chuck electrode can be directly grounded, and the chuck electrode can be connected to the positive terminal and the positive terminal can be grounded.
上述實施例提供的等離子體加工設備可以為LED刻蝕機,用於實施刻蝕工藝;或者為ITO(銦錫氧化 物)物理氣相沉積設備,用於製備ITO薄膜。晶片可以是藍寶石襯底,也可以是其他材質的被加工器件,例如,晶片的材質也可以為矽或氧化矽。 The plasma processing apparatus provided by the above embodiments may be an LED etching machine for performing an etching process; or ITO (indium tin oxide) Physical vapor deposition apparatus for preparing an ITO film. The wafer may be a sapphire substrate or a processed device of other materials. For example, the material of the wafer may also be tantalum or tantalum oxide.
下面介紹本實施例中,托盤21與晶片S之間的靜電吸附力以及托盤21與卡盤23之間的靜電吸附力。 The electrostatic adsorption force between the tray 21 and the wafer S and the electrostatic adsorption force between the tray 21 and the chuck 23 in the present embodiment will be described below.
將托盤21中的托盤電極與直流電源24的正極接通,假設托盤電極對地(GND)電壓為E1,E1等於直流電源24對地(GND)之間的電壓E。當反應腔室20內的等離子體啟輝後,在晶片S的上表面會形成一層導電層,該導電層與地(GND)之間的電壓為E2。由於等離子體的電阻很小,E2近似等於零。因此,托盤電極和晶片S的上表面之間的電壓E3=E1-E2E1=E。卡盤23中的卡盤電極與直流電源24的負極接通,托盤電極和卡盤電極之間的電壓差為E。 The tray electrode in the tray 21 is turned on with the positive electrode of the DC power source 24, assuming that the tray electrode to ground (GND) voltage is E1, and E1 is equal to the voltage E between the DC power source 24 and the ground (GND). After the plasma in the reaction chamber 20 is illuminated, a conductive layer is formed on the upper surface of the wafer S, and the voltage between the conductive layer and the ground (GND) is E2. Since the resistance of the plasma is small, E2 is approximately equal to zero. Therefore, the voltage between the tray electrode and the upper surface of the wafer S is E3 = E1 - E2 E1=E. The chuck electrode in the chuck 23 is turned on with the negative electrode of the DC power source 24, and the voltage difference between the tray electrode and the chuck electrode is E.
卡盤電極和托盤電極之間形成第一電容C1,托盤電極和晶片S的上表面之間形成第二電容C2,由於晶片S的上表面近似接地,而且卡盤電極接地(GND),第一電容C1和第二電容C2為並聯關係,假設卡盤電極和托盤電極之間的距離為d1,托盤電極和晶片S的上表面之間的距離為d2。那麼,根據庫倫定律,在卡盤電極和托盤電極之間(即,卡盤23和托盤21之間)的靜電吸附力F 1為:
在托盤電極(即,托盤21)和晶片S之間的靜電吸附力F 2為:
由上可知,由於第一電容C1和第二電容C2為並聯關係,使得卡盤電極和托盤電極之間的電壓差以及托盤電極和晶片S之間的電壓差均為E。因此,卡盤23和托盤21之間的靜電吸附力F 1以及托盤21和晶片S之間的靜電吸附力F 2較大。 As can be seen from the above, since the first capacitor C1 and the second capacitor C2 are in a parallel relationship, the voltage difference between the chuck electrode and the tray electrode and the voltage difference between the tray electrode and the wafer S are both E. Thus, the tray chuck 23 and the electrostatic attraction force F between the tray 211 and the electrostatic attractive force between the wafer 21 and the larger S F 2.
圖4為本發明另一實施例提供的等離子體加工設備的部分結構的剖面示意圖。如圖4所示,托盤21承載有多個晶片S,對應地,在托盤21的承載面上設有與晶片S數量相等的凸台21c,在蓋板25上同樣設有與晶片S數量相等的定位孔25a,而且定位孔25a的設置位置與凸台21c的位置相對。使用時,每一凸台21c和定位孔25a對應一晶片S,即每一定位孔25a對一個晶片S進行定位,且晶片S放置在凸台21c的頂端。 4 is a cross-sectional view showing a portion of a structure of a plasma processing apparatus according to another embodiment of the present invention. As shown in FIG. 4, the tray 21 carries a plurality of wafers S. Correspondingly, a boss 21c having the same number as the number of wafers S is provided on the carrying surface of the tray 21, and the number of wafers S is equally provided on the cover plate 25. The positioning hole 25a is disposed, and the positioning hole 25a is disposed at a position opposite to the position of the boss 21c. In use, each of the bosses 21c and the positioning holes 25a corresponds to a wafer S, that is, each of the positioning holes 25a positions one wafer S, and the wafer S is placed at the top end of the boss 21c.
上述實施例提供的等離子體加工設備,將托盤放置於卡盤上,托盤和卡盤之間電絕緣,且托盤和卡盤與等離子體之間電絕緣,托盤電極與直流電源的正極輸出端或負極輸出端電連接,卡盤電極接地,以使托盤和卡盤之間存在電壓差,即,在托盤和卡盤之間產生靜電吸附力,從而將托盤固定於卡盤的上表面;以及使托盤和晶片之間存在電壓差,即,在托盤和晶片之間產生靜電吸附力,從而將晶片固定在托盤的上表面,這種固定晶片和托盤的方式不僅容易操作、可靠性高,而且結構簡單、成本低、不易損壞。 The plasma processing apparatus provided in the above embodiment places the tray on the chuck, the board and the chuck are electrically insulated, and the tray and the chuck are electrically insulated from the plasma, and the tray electrode and the positive output of the DC power source or The negative output terminal is electrically connected, and the chuck electrode is grounded so that there is a voltage difference between the tray and the chuck, that is, an electrostatic attraction force is generated between the tray and the chuck, thereby fixing the tray to the upper surface of the chuck; There is a voltage difference between the tray and the wafer, that is, an electrostatic adsorption force is generated between the tray and the wafer to fix the wafer on the upper surface of the tray. This method of fixing the wafer and the tray is not only easy to operate, but also highly reliable, and the structure is Simple, low cost and not easily damaged.
可以理解的是,以上實施方式僅僅是為了說明本發明的原理而採用的示例性實施方式,然而本發明並不局限於此。對於本領域內的普通技術人員而言,在不脫離本發明的精神和實質的情況下,可以做出各種變型和改進,這些變型和改進也視為本發明的保護範圍。 It is to be understood that the above embodiments are merely exemplary embodiments employed to explain the principles of the invention, but the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.
10‧‧‧等離子體 10‧‧‧ Plasma
12‧‧‧第一匹配器 12‧‧‧First matcher
13‧‧‧激勵射頻電源 13‧‧‧Incentive RF power supply
17‧‧‧第二匹配器 17‧‧‧Second matcher
18‧‧‧偏壓射頻電源 18‧‧‧Bias RF power supply
20‧‧‧反應腔室 20‧‧‧Reaction chamber
21‧‧‧托盤 21‧‧‧Tray
21a‧‧‧托盤冷媒通道 21a‧‧‧Tray refrigerant channel
21c‧‧‧凸台 21c‧‧‧ boss
23‧‧‧卡盤 23‧‧‧ chuck
23a‧‧‧第一卡盤冷媒通道 23a‧‧‧First Chuck Refrigerant Channel
23b‧‧‧第二卡盤冷媒通道 23b‧‧‧Second chuck refrigerant channel
24‧‧‧直流電源 24‧‧‧DC power supply
25‧‧‧蓋板 25‧‧‧ Cover
25a‧‧‧定位孔 25a‧‧‧Positioning holes
27‧‧‧介質窗 27‧‧‧Media window
30、30’‧‧‧濾波電路 30, 30'‧‧‧ Filter circuit
A‧‧‧卡盤環形凹槽 A‧‧‧ chuck ring groove
B‧‧‧托盤環形凹槽 B‧‧‧Tray ring groove
S‧‧‧晶片 S‧‧‧ wafer
L21‧‧‧第一濾波電感 L21‧‧‧First filter inductor
C21‧‧‧第一濾波電容 C21‧‧‧First filter capacitor
L22‧‧‧第二濾波電感 L22‧‧‧Second filter inductor
C22‧‧‧第二濾波電容 C22‧‧‧Second filter capacitor
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TWI569363B (en) * | 2014-05-20 | 2017-02-01 | A load device, a reaction chamber and a semiconductor processing device | |
CN106531679A (en) * | 2015-09-10 | 2017-03-22 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Bearing device and reaction chamber |
CN106531679B (en) * | 2015-09-10 | 2019-10-08 | 北京北方华创微电子装备有限公司 | Bogey and reaction chamber |
CN106548969A (en) * | 2015-09-22 | 2017-03-29 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Clamping device and semiconductor processing equipment |
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CN103594315A (en) | 2014-02-19 |
TWI521639B (en) | 2016-02-11 |
WO2014026593A1 (en) | 2014-02-20 |
CN103594315B (en) | 2016-04-20 |
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