CN103280615A - Reconfigurable microwave low-pass filter with MEMS switch - Google Patents

Abstract

The invention relates to a reconfigurable microwave low-pass filter containing a MEMS switch, comprising an input end, an output end, a MEMS bridge, a bias pad, a bias line, a ground wire, a signal line and a bridge pier, and the MEMS film bridge is perpendicular to the The first and second ground wires are distributed; the adjacent MEMS membrane bridges are connected with the signal lines; the piers are respectively arranged at the two ends of the corresponding MEMS membrane bridges; the input ends and output ends are respectively connected to The corresponding ends of the ground wire and the signal wire; the bias pads are respectively connected to the piers of the corresponding ends of the MEMS membrane bridge through the bias wires. Its beneficial effects are: the MEMS switch on the silicon chip replaces the traditional PIN switching diode, varactor diode or FET and other switching devices to realize the frequency reconstruction of the filter; the coplanar waveguide transmission line replaces the coplanar waveguide transmission line on the traditional PCB board ; Compact and simple structure, small size, low power consumption of control circuit, high operating frequency; compatible with traditional IC technology, mature technology, low cost, suitable for mass production.

Description

a containing MEMS Switched reconfigurable microwave low-pass filter

technical field

The invention relates to the technical fields of micromechanical systems and microwaves, in particular to a reconfigurable microwave low-pass filter containing MEMS switches.

Background technique

Reconfigurable microwave low-pass filter is one of the important components in microwave wireless communication system. RF/microwave micromechanical system filters have the characteristics of low loss, high isolation, high linearity, small size, and easy integration with IC and MMIC circuits, which can fundamentally change the structure and characteristics of traditional RF, microwave, and millimeter wave device circuits. Sexual changes. It can reduce the size of the multi-band analog receiving front-end subsystem, suppress strong signal interference and realize multi-band conversion, especially in the millimeter wave band, which can better reflect its high-performance quality. The reconfigurable tuning filter can reduce the size of the multi-band analog receiving front-end subsystem, suppress large signal interference and complete multiple band conversions, and has good high-frequency performance.

Traditional reconfigurable microwave low-pass filters are based on coaxial lines or microstrip lines, and are fabricated on printed circuit boards. They are bulky and unfavorable for integration with IC technology. In addition, traditional microwave low-pass filters with resonant frequency Generally, PIN diode switches and FET switches are used to adjust the filter frequency, and these switches require a large number of bias circuits, which makes the filter have large insertion loss and large size, which is not suitable for small RF receiver front-end applications.

Contents of the invention

The purpose of the present invention is to overcome the above deficiencies in the prior art, to provide a reconfigurable microwave low-pass filter containing MEMS switches and a preparation method thereof, which are specifically realized by the following technical solutions:

The reconfigurable microwave low-pass filter containing MEMS switches includes an input terminal, an output terminal, a MEMS bridge, a bias pad, a bias line, a ground wire, a signal line and a bridge pier, and the MEMS membrane bridge is respectively the first MEMS membrane bridge 31, the second MEMS membrane bridge 32, the 3rd MEMS membrane bridge 33, the 4th MEMS membrane bridge 34 and the 5th MEMS membrane bridge 35; The bias pads are first bias pad 41, second bias pad respectively The pressure pad 42 and the third bias pad 43; the ground wires are the first ground wire 51 and the second ground wire 52 respectively; the first ground wire 50 and the second ground wire 51 are distributed in parallel, and the first MEMS The membrane bridge 31, the second MEMS membrane bridge 32, the third MEMS membrane bridge 33, the fourth MEMS membrane bridge 34 and the fifth MEMS membrane bridge 35 are distributed perpendicular to the first and second ground lines in turn; the adjacent MEMS membrane bridges The signal line is connected between them; the bridge piers are respectively arranged at the two ends of the corresponding MEMS film bridge; the input end and the output end are respectively connected to the corresponding ends of the ground wire and the signal line; the first bias pad 41 are respectively connected to the piers at the corresponding ends of the first and fifth MEMS membrane bridges through bias lines, and the second bias pads 42 are correspondingly connected to the piers at the corresponding ends of the third MEMS membrane bridges through bias lines, and the second bias pads 43 The bridge piers at the corresponding ends of the second and fourth MEMS membrane bridges are respectively connected through bias lines.

The further design of the reconfigurable microwave low-pass filter containing MEMS switches is that the signal lines are respectively the first signal line 71, the second signal line 72, the third signal line 73 and the fourth signal line 74, so The first, second, third and fourth signal lines are sequentially connected between two adjacent piers among the five piers mentioned above.

A further design of the reconfigurable microwave low-pass filter including MEMS switches is that the second and third signal lines contain a ground-sink structure.

The further design of the reconfigurable microwave low-pass filter containing MEMS switches is that the piers are respectively the first pier 80, the second pier 81, the third pier 82, the fourth pier 83, the fifth pier 84, the The sixth pier 85, the seventh pier 86, the eighth pier 87, the ninth pier 88, and the tenth pier 89, the first, second, third, fourth, and fifth pier respectively correspond to the first and the first Two, third, fourth, and fifth MEMS membrane bridges are located at one end of the outer side of the first ground wire; the sixth, seventh, eighth, ninth, and tenth bridge piers are respectively arranged on the first, second, and One end of the third, fourth, and fifth MEMS membrane bridges on the outside relative to the second ground wire.

The further design of the reconfigurable microwave low-pass filter containing MEMS switches is that the bias lines are respectively the first bias line 61, the second bias line 62, the third bias line 63, the fourth bias line The pressure line 64 and the fifth bias line 65, the two ends of the first bias line 61 are respectively connected to the first bridge pier 80 and the first bias pad 41, and the second bias line 62 is respectively connected to the fifth bridge pier 84 And the first bias pad 41, the two ends of the third bias line 63 are respectively connected to the seventh pier 86 and the third bias pad 43, and the two ends of the fourth bias line 64 are respectively connected to the eighth pier 87 As well as the second bias pad 42 , both ends of the fifth bias line 65 are respectively connected to the ninth bridge pier 88 and the third bias pad 43 .

The further design of the reconfigurable microwave low-pass filter containing MEMS switches is that the input terminals are respectively the first input terminal 11, the second input terminal 12 and the third input terminal 13; An output terminal 21, a second output terminal 22 and a third output terminal 23; the first, second and third input terminals are respectively connected to corresponding ends of the first ground wire, the first signal wire and the second ground wire, so The first, second, and third output ends are respectively connected to corresponding ends of the first ground wire, the fourth signal wire, and the second ground wire.

According to the preparation method of the reconfigurable microwave low-pass filter containing MEMS switches, a total of six mask plates from numbers 1 to 6 are used, and the specific operation steps are as follows:

1) Put a two-inch silicon wafer with a thickness of 500 μm in a mixture of H2O2 and H2SO4, wash it with deionized water, then put the silicon wafer into No. 1 cleaning solution, boil it for 10 minutes, and wash it with deionized water. The No. 1 cleaning solution is a mixed solution of NH ₄ OH, H ₂ O ₂ , and deionized water; finally, put the silicon wafer into the No. The solution is a mixture of HCL, H ₂ O ₂ and deionized water);

2) A silicon dioxide layer with a thickness of 1.5 μm is thermally oxidized on the surface of the silicon wafer. The process conditions are: 8-12 minutes of dry oxygen, 95-105 minutes of wet oxygen, and 18-22 minutes of dry oxygen oxidation. ;

3) A chromium layer and a gold layer are sequentially evaporated and deposited on the silicon dioxide layer, with a thickness of 800Å and 3000Å respectively, and the process conditions are: the temperature and vacuum in the evaporation furnace are 230°C~250°C and 10×10 ^-5 Torr, respectively ;

4) Use the No. 1 mask to cover the positive resist on the surface of the area other than the No. 1 mask pattern of the silicon wafer, leaving the pattern to be electroplated, and electroplating gold to form three input terminals, three output terminals, and ten bridge piers And three bias pads, the thickness of the electroplating layer is 2μm, and the glue is removed to prepare for the next operation;

5) The method of positive resist lithography No. 1 mask plate is photolithographically etched No. 2 mask plate and No. 3 mask plate, and electroplated with gold to form two ground wires, four signal wires, and five bias voltage wires. The thicknesses are respectively 2μm, this electroplating increases the thickness of the input and output terminals, bias pads and bridge piers from 2μm to 3μm, and the glue is removed to prepare for the next operation;

6) Negative photolithography No. 2 mask plate, after development, put it in an oven at 115°C~125°C to harden the film for 25~35 minutes, then plasma etch for 20 seconds, and finally put the gold layer on the unplated part at room temperature , The titanium layer is corroded, and the three input and output terminals, two ground wires, four signal wires, three bias pads, five bias wires and ten bridge piers are retained, and the gold corrosion solution is KI, I ₂ and The mixed solution of H ₂ O, the solution for corrosion of chromium is phosphoric acid;

7) Oxygen plasma etching is used to remove the glue, and the etching power, oxygen flow rate, and etching time are 50W, 60ml/min, and 18-22 seconds respectively;

8) Deposit a layer of silicon nitride film with a thickness of 0.3 μm on the surface of the silicon wafer by chemical vapor deposition, and the flow rate of ammonia gas, silane flow rate and temperature are 28ml/min, 560ml/min and 270℃~290℃ respectively;

9) Cover the pattern on the No. 4 board with positive glue to protect the required silicon nitride film, etch the silicon nitride film with SF6 gas plasma, the power, the flow rate of SF6 gas and the etching time are 50w and 2.4ml/s respectively and 75~85 seconds;

10) At the speed of 2000 rpm, spin-coat a layer of polyimide film with a thickness of Baking for 25-35 minutes, spin-coating a 2μm thick positive resist on the sacrificial layer, photolithography through the No. 5 mask, removing the positive resist after development, and obtaining the sacrificial layer pattern, and then curing the silicon wafer at 260°C for 1 hour ;

11) Under a vacuum of 5×10 ^-5 Torr, evaporate and deposit an aluminum-silicon alloy film containing 4% silicon and a thickness of 0.5 μm on the surface of the silicon wafer;

12) Negative photolithography No. 6 mask plate, place the silicon wafer in the H ₃ PO ₄ solution with a concentration ≥ 85% at 65°C~75°C, etch the aluminum-silicon alloy film until the bubbles emerging from the phosphoric acid solution are very Weak, forming a bridging film, the silicon wafer is quickly cleaned with deionized water;

13) Plasma etching to remove negative resist and sacrificial layer, plasma etching power, oxygen flow rate and nitrogen flow rate are 50w, 60ml/s and 2.8ml/s respectively, and five suspended bridge membrane structures are obtained, which are MEMS switch activities contacts.

The advantages of the present invention are as follows:

1. The filter is composed of a MEMS switch deposited on a silicon chip and a coplanar waveguide transmission line. The former replaces traditional PIN switching diodes, varactor diodes or FETs to realize the frequency reconstruction of the filter, and the latter replaces Instead of the traditional coplanar waveguide transmission line on the PCB, it has the advantages of compact and simple structure, small size, good isolation, low insertion loss, low power consumption of the control circuit, and high operating frequency.

2. The filter. Compatible with traditional IC technology, integrated on a high-resistance silicon substrate, the technology is mature, the cost is low, and it is suitable for mass production.

Description of drawings

Fig. 1 is a structural diagram of the reconfigurable filter.

FIG. 2 is a schematic diagram of the No. 1 mask pattern.

FIG. 3 is a schematic diagram of the No. 2 mask pattern.

FIG. 4 is a schematic diagram of the No. 3 mask pattern.

FIG. 5 is a schematic diagram of the No. 4 mask pattern.

FIG. 6 is a schematic diagram of the No. 5 mask pattern.

FIG. 7 is a schematic diagram of the No. 6 mask pattern.

Fig. 8 is the S parameter of the reconfigurable low-pass filter before reconstruction.

Fig. 9 is the reconstructed S-parameter of the reconfigurable low-pass filter.

In the figure, 11-first input terminal, 12-second input terminal, 13-third input terminal, 21-first output terminal, 22-second output terminal, 23-third output terminal, 31-first MEMS membrane bridge, 32-second MEMS membrane bridge, 33-third MEMS membrane bridge, 34-fourth MEMS membrane bridge, 35-fifth MEMS membrane bridge, 41-first bias pad, 42-second bias pad, 43-third bias pad, 51-first ground wire, 52-second ground wire, 61-first bias wire, 62-second bias wire, 63-third bias wire, 64- The fourth bias line, 65-the fifth bias line, 71-the first signal line, 72-the second signal line, 73-the third signal line, 74-the fourth signal line, 80-the first pier, 81- The second pier, 82-the third pier, 83-the fourth pier, 84-the fifth pier, 85-the sixth pier, 86-the seventh pier, 87-the eighth pier, 88-the ninth pier, 89-the tenth piers.

Detailed ways

The solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

The reconfigurable microwave low-pass filter including MEMS switches provided in this embodiment includes an input terminal, an output terminal, a MEMS bridge, a bias pad, a bias line, a ground line, a signal line, and a bridge pier.

The MEMS membrane bridges are respectively a first MEMS membrane bridge 31 , a second MEMS membrane bridge 32 , a third MEMS membrane bridge 33 , a fourth MEMS membrane bridge 34 and a fifth MEMS membrane bridge 35 . The bias pads are respectively a first bias pad 41 , a second bias pad 42 and a third bias pad 43 . The ground wires are the first ground wire 51 and the second ground wire 52 respectively. The first ground wire 50 and the second ground wire 51 are distributed in parallel. The first MEMS membrane bridge 31 , the second MEMS membrane bridge 32 , the third MEMS membrane bridge 33 , the fourth MEMS membrane bridge 34 and the fifth MEMS membrane bridge 35 are distributed perpendicular to the first and second ground lines in sequence. The signal lines are respectively the first signal line 71, the second signal line 72, the third signal line 73 and the fourth signal line 74, and the first, second, third and the fourth signal line. Wherein, the second and third signal lines contain a ground defect structure.

The piers are the first pier 80, the second pier 81, the third pier 82, the fourth pier 83, the fifth pier 84, the sixth pier 85, the seventh pier 86, the eighth pier 87, the ninth pier 88 and the tenth pier. Bridge piers 89, the first, second, third, fourth, and fifth piers are respectively arranged at one end of the first, second, third, fourth, and fifth MEMS membrane bridges relative to the outer side of the first ground line; The sixth, seventh, eighth, ninth, and tenth bridge piers are respectively respectively arranged on the outer ends of the first, second, third, fourth, and fifth MEMS membrane bridges relative to the second ground line.

The input terminals are respectively the first input terminal 11, the second input terminal 12 and the third input terminal 13; the output terminals are respectively the first output terminal 21, the second output terminal 22 and the third output terminal 23; The third input terminal is respectively connected to the first ground wire 51, the first signal wire 71 and the corresponding end of the second ground wire 52, and the first, second, and third output terminals are respectively connected to the first ground wire 51 and the fourth signal wire 74. and the corresponding end of the second ground wire 52 .

The bias lines are respectively the first bias line 61, the second bias line 62, the third bias line 63, the fourth bias line 64 and the fifth bias line 65, and the two ends of the first bias line 61 are respectively Connect the first bridge pier 80 and the first bias pad 41, the second bias line 62 is respectively connected to the fifth bridge pier 84 and the first bias pad 41, and the two ends of the third bias line 63 are respectively connected to the seventh bridge pier 86 and the first bias pad 41. Three biasing pads 43, both ends of the fourth biasing line 64 are respectively connected to the eighth pier 87 and the second biasing pad 42, and the two ends of the fifth biasing line 65 are respectively connected to the ninth pier 88 and the third biasing pad 43.

The reconfigurable microwave low-pass filter containing MEMS switches provided according to this embodiment provides a preparation method comprising the following steps:

1) Put a two-inch silicon wafer with a thickness of 500 μm in a mixture of H ₂ O ₂ :H ₂ SO ₄ =1:1, clean it with deionized water, and then put the silicon wafer into No. 1 cleaning solution and boil for 10 minutes , rinsed with deionized water. The composition ratio of No. 1 cleaning solution used in this example is 27%NH ₄ OH: 30% H ₂ O ₂ : deionized water = 1:2:5; finally put the silicon wafer into No. 2 cleaning solution and boil until it boils , Rinse with deionized water, spin dry, and dry. The composition ratio of No. 2 cleaning solution used in this embodiment is 37% HCL: 30% H ₂ O ₂ : deionized water = 1:2:8.

2) Thermally oxidize and grow a silicon dioxide layer with a thickness of 1.5 μm on the surface of the silicon wafer. The process conditions are: 10 minutes of dry oxygen, 100 minutes of wet oxygen, and 20 minutes of dry oxygen oxidation;

3) A chromium layer and a gold layer were sequentially evaporated and deposited on the silicon dioxide layer, with a thickness of 800Å and 3000Å respectively, and the process conditions were: the temperature and vacuum in the evaporation furnace were 250°C and 10×10-5Torr, respectively;

4) Use the No. 1 mask to cover the positive resist on the surface of the area other than the No. 1 mask pattern of the silicon wafer, leaving the pattern to be electroplated, and electroplating gold to form three input terminals, three output terminals, and ten bridge piers And three bias pads, the thickness of the electroplating layer is 2μm, and the glue is removed to prepare for the next operation;

5) The method of positive resist lithography No. 1 mask plate is photolithographically etched No. 2 mask plate and No. 3 mask plate, and electroplated with gold to form two ground wires, four signal wires, and five bias voltage wires. The thicknesses are respectively In addition, this electroplating increases the thickness of the input and output terminals, bias pads and bridge piers from the original 2 μm to 3 μm, and the glue is removed to prepare for the next operation;

6) Negative photolithography No. 2 mask plate, after development, place it in an oven at 120°C for 30 minutes to harden the film, then plasma etch for 20 seconds, and finally etch away the gold layer and titanium layer of the unplated part in turn at room temperature , retaining three input and output terminals, two ground wires, four signal wires, three bias pads, five bias wires and ten bridge piers, the formula of the gold corrosion solution is KI:I ₂ :H ₂ O= 20g: 6g: 100ml, the solution for chromium corrosion is phosphoric acid;

7) Oxygen plasma etching is used to remove the glue, and the etching power, oxygen flow rate, and etching time are 50W, 60ml/min, and 20 seconds respectively;

8) Deposit a layer of silicon nitride film with a thickness of 0.3 μm on the surface of the silicon wafer by chemical vapor deposition, the flow rate of ammonia gas, the flow rate of silane and the temperature are 28ml/min, 560ml/min and 280°C;

9) Cover the graphics on the No. 4 board with positive glue to protect the required silicon nitride film. Then use SF6 gas plasma to etch the silicon nitride film, the power, the flow rate of SF6 gas and the etching time are respectively 50w, 2.4ml/s and 1 minute and 20 seconds;

10) At a speed of 2000 rpm, spin-coat a layer of polyimide film with a thickness of Spin coat a positive resist with a thickness of 2 μm, pass through No. 5 mask plate photolithography, remove the positive resist after development, and obtain a sacrificial layer pattern, and then cure the silicon wafer at 260°C for 1 hour;

11) Under a vacuum of 5×10 ^-5 Torr, evaporate and deposit an aluminum-silicon alloy film containing 4% silicon and a thickness of 0.5 μm on the surface of the silicon wafer;

12) Negative photolithography No. 6 mask plate, place the silicon wafer in the H ₃ PO ₄ solution with a concentration ≥ 85% at 70°C, etch the aluminum-silicon alloy film until the bubbles emerging from the phosphoric acid solution are very weak, forming The bridge membrane and the silicon wafer are quickly cleaned with deionized water;

13) Plasma etching to remove negative resist and sacrificial layer, plasma etching power, oxygen flow rate and nitrogen flow rate are 50w, 60ml/s and 2.8ml/s respectively, and five suspended bridge membrane structures are obtained, which are MEMS switch activities contacts.

The 3dB cut-off frequencies of the filter before and after reconstruction are 10.5GHz and 16.8GHz, respectively. The reconfigurable low-pass filter obtains the reconfiguration function by turning off and on the five MEMS switches. Before reconfiguration, one end of the 28V voltage is applied to the bias pads 41 and 42, and the other end is applied to the first bias pad. 51 on the third bias pad 52, then the first MEMS membrane bridge 31, the third MEMS membrane bridge 33 and the fifth MEMS membrane bridge 35 are closed due to electrostatic action, the second MEMS membrane bridge 32 and the fourth MEMS membrane bridge 34 are opened, Neglecting the parasitic effect of turning on the MEMS switch, it is equivalent to connecting two small units of low-pass filters in series, one end of the 28V voltage is applied to the first ground wire 51 and the second ground wire 52, and the other end is applied to the second bias pad 43 At this time, the second MEMS membrane bridge 32 and the fourth MEMS membrane bridge 34 are closed due to the electrostatic force. The filter at this time is equivalent to a new filter with a structure similar to the original low-pass filter unit, but the length of the transmission line is twice the original, because the length of the signal line after reconstruction is double that before reconstruction, so the filter The 3dB cut-off frequency is from 10.5 to 16.8GHz, and the out-of-band rejection is greater than 27dB, thus realizing the reconfigurable low-pass filter.

The low-pass filter provided by the invention is particularly suitable for use in a phase-controlled filter array as a multi-band and broadband reconfigurable microwave low-pass filter, and has the advantages of small size, high frequency, and small insertion loss. In addition, this low-pass filter can also be used for RF device integration.

Claims (7)

1. reconfigurable microwave low-pass filter that contains mems switch, comprise input, output, MEMS bridge, bias pad, bias line, ground wire, holding wire and bridge pier, it is characterized in that described MEMS film bridge is respectively a MEMS film bridge, the 2nd MEMS film bridge, the 3rd MEMS film bridge, the 4th MEMS film bridge and the 5th MEMS film bridge; Described bias pad is respectively first bias pad, second bias pad and the 3rd bias pad; Described ground wire is respectively first ground wire and second ground wire; Described first ground wire and the second ground line parallel distribute, and a described MEMS film bridge, the 2nd MEMS film bridge, the 3rd MEMS film bridge, the 4th MEMS film bridge and the 5th MEMS film bridge distribute perpendicular to first, second ground wire successively; Be connected with described holding wire between described adjacent MEMS film bridge; Described bridge pier is located at the two ends of corresponding MEMS film bridge respectively; Described input, output be the corresponding corresponding end that is connected in ground wire and holding wire respectively; Described first bias pad connects the bridge pier of the first, the 5th MEMS film bridge corresponding end respectively by bias line, described second bias pad is by the corresponding bridge pier that connects the 3rd MEMS film bridge corresponding end of bias line, and described second bias pad connects the bridge pier of the second, the 4th MEMS film bridge corresponding end respectively by bias line.

2. the reconfigurable microwave low-pass filter that contains mems switch according to claim 1, it is characterized in that described holding wire is respectively first holding wire, secondary signal line, the 3rd holding wire and the 4th holding wire, connect the first, second, third and the 4th holding wire successively between the adjacent bridge pier in twos in described five bridge piers.

3. the reconfigurable microwave low-pass filter that contains mems switch according to claim 2 is characterized in that described second, third holding wire contains scarce earth subsidence structure.

4. the reconfigurable microwave low-pass filter that contains mems switch according to claim 1, it is characterized in that described bridge pier is respectively first bridge pier, second bridge pier, the 3rd bridge pier, the 4th bridge pier, the 5th bridge pier, the 6th bridge pier, the 7th bridge pier, the 8th bridge pier, the 9th bridge pier and the tenth bridge pier, described the first, second, third, fourth, the 5th bridge pier is corresponding successively respectively is located at the first, second, third, fourth, the 5th MEMS film bridge with respect to an end of first ground outside; Described the 6th, the 7th, the 8th, the 9th, the tenth bridge pier is corresponding successively respectively is located at the first, second, third, fourth, the 5th MEMS film bridge with respect to an end of second ground outside.

5. the reconfigurable microwave low-pass filter that contains mems switch according to claim 1, it is characterized in that described bias line is respectively first bias line, second bias line, the 3rd bias line, the 4th bias line and the 5th bias line, the two ends of described first bias line connect first bridge pier and first bias pad respectively, described second bias line connects the 5th bridge pier and first bias pad respectively, the two ends of described the 3rd bias line connect the 7th bridge pier and the 3rd bias pad respectively, the two ends of described the 4th bias line connect the 8th bridge pier and second bias pad respectively, and the two ends of described the 5th bias line connect the 9th bridge pier and the 3rd bias pad respectively.

6. the reconfigurable microwave low-pass filter that contains mems switch according to claim 1 is characterized in that described input is respectively first input end, second input and the 3rd input; Described output is respectively first output, second output and the 3rd output; Described first, second, third input connects the corresponding end of first ground wire, first holding wire and second ground wire respectively, and described first, second, third output connects the corresponding end of first ground wire, the 4th holding wire and second ground wire respectively.

7. as any described preparation method who contains the reconfigurable microwave low-pass filter of mems switch of claim 1-4, it is characterized in that adopt six mask plates altogether one to No. six, the concrete operations step is as follows:

1) two inches 500 μ m are thick silicon chip places H ₂O ₂, H ₂SO ₄Mixed liquor in, washed with de-ionized water is put into cleaning fluid to silicon chip No. one then, boil to the boiling 10 minutes, washed with de-ionized water, a described cleaning fluid is NH ₄OH, H ₂O ₂, the deionized water mixed liquor; At last silicon chip is put into No. two cleaning fluids and boil to boiling, deionized water rinsing, drying, oven dry, described No. two cleaning fluids are HCL, H ₂O ₂And the mixed liquor of deionized water);

2) be 1.5 μ m silicon dioxide layers at silicon chip surface thermal oxide growth thickness, process conditions: feed 8 ~ 12 minutes dried oxygen, fed wet oxygen in 95 ~ 105 minutes, add 18 ~ 22 minutes again and feed dry-oxygen oxidation;

3) hydatogenesis chromium layer and gold layer successively on silicon dioxide layer, thickness is respectively 800 and 3000, and process conditions are: temperature and vacuum degree in the vapourizing furnace are respectively 230 ℃ ~ 250 ℃ and 10 * 10 ^-5Torr;

4) positive glue is covered on the surface of mask plate figure with exterior domain of silicon chip by a mask plate, reserve the figure that needs plating, electrogilding forms three inputs, three outputs, ten bridge piers and three bias pad, thickness of plating layer is 2 μ m, removes photoresist and prepares next step operation;

5) No. two mask plates of the method for a positive mask plate of glue photoetching difference photoetching, No. three mask plates, electrogilding forms two ground wires, four holding wires, five bias lines, thickness is respectively 2 μ m, plating this time makes the thickness of input/output terminal, bias pad and bridge pier increase to 3 μ m by original 2 μ m, removes photoresist and prepares next step operation;

6) negative No. two mask versions of glue photoetching, be placed in 115 ℃ ~ 125 ℃ the baking oven post bake after the development 25 ~ 35 minutes, plasma etching is 20 seconds then, successively gold layer, the titanium layer of not electroplating part are eroded at normal temperatures at last, keep three input/output terminals, two ground wires, four holding wires, three bias pad, five bias lines and ten bridge piers, the solution of acid gilding be KI, I ₂And H ₂The mixed liquor of O, the solution of corrosion chromium is phosphoric acid;

7) adopt the oxygen gas plasma etching to remove photoresist, etching power, oxygen flow, etch period are respectively 50W, 60ml/min and 18 ~ 22 seconds;

8) be the silicon nitride film of 0.3 μ m with chemical vapor deposition at silicon chip surface deposit one layer thickness, ammonia flow, silane flow rate and temperature are respectively 28ml/min, 560ml/min and 270 ℃ ~ 290 ℃;

9) with figure on No. four plates of positive glue covering, the silicon nitride film that protection needs is used SF ₆Gaseous plasma etch silicon nitride film, power, SF ₆The flow of gas and etch period are respectively 50w, 2.4ml/s and 75 ~ 85 seconds;

10) under 2000 rev/mins the rotating speed, the polyimide film that at silicon chip surface spin coating one layer thickness is is as sacrifice layer, 85 ℃ ~ 95 ℃ were dried by the fire 55 ~ 65 minutes down, dried by the fire 25 ~ 35 minutes down at 125 ℃ ~ 135 ℃ again, the thick positive glue of spin coating 2 μ m on sacrifice layer, by No. 5 mask plate photoetching, positive glue is removed in the back of developing, obtain the sacrifice layer figure, then silicon chip was solidified 1 hour down at 260 ℃;

11) 5 * 10 ^-5Under the vacuum degree of Torr, with siliceous 4% and thickness be that the alusil alloy film evaporation deposition of 0.5 μ m is on the surface of silicon chip;

12) negative No. six mask plates of glue photoetching, under 65 ℃ ~ 75 ℃ with the H of silicon slice placed at concentration 〉=85% ₃PO ₄In the solution, the bubble that corrosion alusil alloy film is emerged to the phosphoric acid solution is very faint, forms the bridge film, and silicon chip cleans up with deionized water rapidly;

13) plasma etching removes negative glue and sacrifice layer, and plasma etching power, oxygen flow and nitrogen flow are respectively 50w, 60ml/s and 2.8ml/s, obtain five unsettled bridge membrane structures, and this structure is exactly the mems switch movable contact flat.

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