CN101431172B - Reconfigurable microwave low-pass filter containing MEMS switch and its manufacturing method - Google Patents

Abstract

A reconfigurable microwave low-pass filter with MEMS switch and its preparation. The filter is an integrated circuit fabricated on a substrate of a high-resistance silicon wafer. The CPW coplanar waveguide ground wire and the signal wire constitute an inductive reactance element. On the one hand, a MEMS switch constitutes a capacitive reactance element; The length of the surface waveguide makes the frequency of this filter adjustable. The filter uses a high-resistance silicon wafer as a substrate, and uses a process compatible with the IC process to evaporate the titanium layer and the gold layer through thermal oxidation, positive photolithography, electroplating, and negative photolithography to corrode the gold layer and the titanium layer. Remove the negative glue, grow the silicon nitride film, remove the silicon nitride film, evaporate and deposit the aluminum-silicon alloy film, etch the aluminum-silicon alloy film to form a bridge film and remove the sacrificial layer. It has a compact and simple structure and a small size. Good isolation, low insertion loss, low power consumption of the control circuit, high operating frequency, compatible with traditional IC technology, low cost, and suitable for mass production.

Description

A kind of reconfigurable microwave low-pass filter containing MEMS switch and its preparation method

technical field

The invention relates to a reconfigurable microwave low-pass filter containing a MEMS (micro-electro-mechanical) switch and a preparation method thereof, belonging to the technical field of micro-mechanical systems and microwave intersections. the

Background technique

Reconfigurable microwave low-pass filter is one of the important components in microwave wireless communication system. It can significantly reduce the size of the multi-band analog receiving front-end subsystem, suppress strong signal interference and realize multi-band conversion, especially in the millimeter wave band, which can better reflect its high performance quality. the

Traditional reconfigurable microwave low-pass filters are based on coaxial lines or microstrip lines, and are fabricated on printed circuit boards (PCBs). Filters generally use PIN diode switches and FET switches to adjust the filter frequency, and these switches require a large number of bias circuits, which makes the filter have large insertion loss and large size, which is not suitable for small RF receiver front-end applications. the

Contents of the invention

MEMS switches have the advantages of small size, good isolation, low insertion loss, low control circuit power consumption, wide operating frequency band and available IC process integration, especially suitable for replacing PIN diode switches or FET switches to realize microwave low-pass filters The frequency reconstruction greatly reduces the volume of the filter, so that the entire filter can be integrated on the Si-based substrate with an IC process. the

The first technical problem to be solved by the invention is to introduce a reconfigurable microwave low-pass filter containing MEMS switches. the

In order to solve the above-mentioned technical problems, the present invention adopts the following technical solutions. The reconfigurable microwave low-pass filter of the present invention is an integrated circuit fabricated on a substrate of a high-resistance silicon chip, the CPW coplanar waveguide ground wire and the signal line form the inductive element of the low-pass filter, and the MEMS film bridge and bias The pressure line constitutes a MEMS switch, which on the one hand provides a capacitive reactance element for the low-pass filter, and on the other hand changes the length of the coplanar waveguide through the on-off of the MEMS switch, so that the frequency of the filter can be adjusted, so as to achieve the reconstruction of the filter Purpose. the

The technical solution of the present invention will now be described in detail in conjunction with the accompanying drawings. The low-pass filter includes three input terminals, three output terminals, five MEMS membrane bridges, four bias pads, two ground wires, six bias voltage wires, nine signal wires and ten bridge piers, The three input terminals are respectively the first input terminal 10, the second input terminal 11 and the third input terminal 12, and the three output terminals are respectively the first output terminal 20, the second output terminal 21 and the third output terminal 22, five The MEMS membrane bridges are respectively the first MEMS membrane bridge 30, the second MEMS membrane bridge 31, the third MEMS membrane bridge 32, the fourth MEMS membrane bridge 33 and the fifth MEMS membrane bridge 34, and the four bias pads are the first bias pads respectively. The pressure pad 40, the second bias pad 41, the third bias pad 42 and the fourth bias pad 43, the two ground wires are respectively the first ground wire 50 and the second ground wire 51, and the six bias wires are respectively The first bias line 60, the second bias line 61, the third bias line 62, the fourth bias line 63, the fifth bias line 64 and the sixth bias line 65, the nine signal lines are respectively the first Signal line 70, second signal line 71, third signal line 72, fourth signal line 73, fifth signal line 74, sixth signal line 75, seventh signal line 76, eighth signal line 77, and ninth signal line 78, the ten piers are the first pier 80, the second pier 81, the third pier 82, the fourth pier 83, the fifth pier 84, the sixth pier 85, the seventh pier 86, the eighth pier 87, and the ninth pier 88 and the tenth pier 89, characterized in that nine signal lines are arranged in parallel between the first ground wire 50 and the second ground wire 51, the first pier 80, the second pier 81, the third pier 82, the fourth pier The bridge pier 83 and the fifth bridge pier 84 are arranged in sequence outside the first ground line 50, and the first bias line 60, the second bias line 61, the first bias pad 40 and the sixth bias line 65 are distributed on the first bridge pier. 80. Outside the second pier 81, the third pier 82, the fourth pier 83 and the fifth pier 84, the sixth pier 85, the seventh pier 86, the eighth pier 87, the ninth pier 88, and the tenth pier 89 are arranged in sequence Outside the second ground line 51, the third bias line 62, the fourth bias line 63, the fifth bias line 64, the second bias pad 41, the third bias pad 42 and the fourth bias pad 43 are distributed On the outside of the sixth pier 85, the seventh pier 86, the eighth pier 87, the ninth pier 88, and the tenth pier 89, the first pier 80, the second pier 81, the third pier 82, the fourth pier 83 and the fifth pier The pier 84 forms five pier pairs with the sixth pier 85, the seventh pier 86, the eighth pier 87, the ninth pier 88, and the tenth pier 89, and the first input end 10 and the first output end 20 are connected to the first ground respectively. The left end and the right end of the line 50 are connected, the third input end 12 and the third output end 22 are respectively connected with the left end and the right end of the second ground line 51, the second input end 11 is connected with the first signal line 70, the fifth signal line 74 and The sixth signal line 75 is connected, the second output terminal 21 is connected with the fourth signal line 73, the fifth signal line 74 and the ninth signal line 78, and the first bias line 60 is connected across the first bridge pier 80 and the first bias line between pads 40, the sixth bias line 65 across the Connected between the first bias pad 40 and the fifth pier 84, the second bias line 61 is connected between the second pier 81 and the fourth pier 83, and the third bias line 62 is connected across the seventh pier 86 and the second bias pad 41, the fourth bias line 63 is connected between the eighth bridge pier 87 and the third bias pad 42, and the fifth bias line 64 is connected between the ninth bridge pier 88 and the fourth bias pad Between the pressure pads 43, the first MEMS bridging membrane 30 is bridged between the first pier 80 and the sixth pier 85, the second MEMS bridging membrane 31 is bridging between the second pier 81 and the seventh pier 86, and the third The MEMS bridging membrane 32 is connected between the third pier 82 and the eighth pier 87, the fourth MEMS bridging membrane 33 is connected between the fourth pier 83 and the ninth pier 88, and the fifth MEMS bridging membrane 34 is connected between the fourth pier 83 and the ninth pier 88. Between the fifth pier 84 and the tenth pier 89. the

The second technical problem to be solved by the present invention is to provide a preparation method of the filter. In order to solve the above-mentioned technical problems, the present invention adopts the following technical solutions. The filter uses a high-resistance silicon wafer as the substrate, and uses a process compatible with the IC process to clean the silicon wafer, thermally oxidize, evaporate the titanium layer and the gold layer, positive photolithography No. 1 mask plate, electroplating, and positive photolithography Engraving No. 2 and No. 3 masks, electroplating, negative resist photolithography, etching gold layer and titanium layer, removing negative resist, growing silicon nitride film, positive resist photolithography No. 4 mask, removing silicon nitride film, positive resist Photolithography No. 5 mask plate, vapor deposition of aluminum-silicon alloy film, corrosion of aluminum-silicon alloy film to form bridge film and removal of sacrificial layer process steps. The technical solution of the present invention is now described in detail. the

A preparation method of a reconfigurable microwave low-pass filter containing a MEMS switch is characterized in that the method is compatible with the IC process, and a total of six mask plates are used, and the specific operation steps are as follows:

The first step is to clean the silicon wafer

Put a high-resistance silicon wafer with a thickness and diameter of 550 μm and two inches, respectively, in a mixture of H ₂ O ₂ : _{H 2} SO ₄ =1:1, boil until it boils and emit black smoke, clean it with deionized water, and then place the silicon wafer Put the No. 1 cleaning solution and boil until boiling, then wash with deionized water, and finally put the silicon wafer into No. 2 cleaning solution and boil until boiling, rinse with deionized water, spin dry, and dry. ₄ OH: 30% H ₂ O ₂ : deionized water = 1: 2: 5, the formula of cleaning solution No. 2 is 37% HCL: 30% H ₂ O ₂ : deionized water = 1: 2: 8;

The second thermal oxidation

A silicon dioxide layer with a thickness of 1 μm is grown on the surface of the high-resistance silicon wafer by thermal oxidation, and dry oxygen is passed in for 10 minutes, wet oxygen is passed in for 100 minutes, and dry oxygen is passed in for another 10 minutes;

The third step is to evaporate the titanium layer and the gold layer

On the silicon dioxide layer of the high-resistance silicon wafer processed in the second step, a titanium layer and a gold layer are sequentially evaporated and deposited, with a thickness of 1000 and 3000 , the temperature and vacuum in the evaporation furnace are respectively 250°C and 10×10 ^-5 Torr;

The fourth step is positive resist photolithography No. 1 mask plate, electroplating

The high-resistance silicon wafer processed in the third step is subjected to the No. 1 mask process of positive resist photolithography. At a speed of 1800 rpm, the positive resist is covered on the high-resistance silicon wafer, and the high Photolithography is performed on the positive resist on the silicon resistance wafer, leaving the pattern that needs to be electroplated, electroplating a gold layer with a thickness of 2 μm, forming three input terminals, three output terminals, ten bridge piers and four bias pads, and removing the glue;

Step 5: Positive photolithography No. 2 and No. 3 masks, electroplating

Using the same positive resist photolithography method as in the fourth step, the positive resist on the high-resistance silicon wafer is photoresisted through the No. 2 mask and the No. 3 mask in sequence, and the No. The electroplating gold layer, with a thickness of 2 μm, forms two ground wires, nine signal wires, and six bias voltage wires. The No. The thickness of a bias pad and ten bridge piers is increased from 2 μm to 4 μm, and the glue is removed;

The sixth step is negative photolithography, corroding the gold layer and titanium layer

Negative photolithography No. 2 mask plate, after development, put it in an oven at 130°C to harden the film for 30 minutes, then plasma etch it for 20 seconds, and finally etch away the gold layer and titanium layer of the unplated part at room temperature, and keep Three input terminals, three output terminals, two ground wires, nine signal wires, four bias pads, six bias wires and ten bridge piers, the formula of the gold corrosion solution is KI:I ₂ :H ₂ O =20g: 6g: 100ml, the formula of the solution for corrosion of titanium is K2[Fe(CN) ₆ ]: KOH: H ₂ O = 30g: 5g: 100ml;

The seventh step is to remove the negative glue

Use oxygen plasma etching to remove the negative resist on the high-resistance silicon wafer treated in the sixth step, and the etching power, oxygen flow rate, and etching time are 50W, 60ml/min, and 20 seconds respectively;

The eighth step is to grow silicon nitride film

Use chemical vapor deposition to deposit a layer of silicon nitride film on the surface of the high-resistance silicon wafer processed in the seventh step, the thickness is 0.3 μm, the flow rate of ammonia gas, the flow rate of silane and the temperature are respectively 24ml/min, 560ml/min and 280°C;

The ninth step is to photoresist No. 4 mask and remove the silicon nitride film

Implement the No. 4 mask process of positive resist photolithography on the high-resistance silicon wafer processed in the eighth step, cover the pattern on the No. 4 mask with positive resist, protect the silicon nitride film that needs to be retained, and etch with SF ₆ gas plasma. Etching the silicon nitride film, the etching power, the flow rate of SF ₆ gas and the etching time are respectively 50w, 2.4ml/s and 1 minute and 50 seconds;

Step 10 Positive photolithography No. 5 mask plate

At a speed of 2000 rpm, spin-coat a layer of polyimide film with a thickness of 2 μm on the surface of the high-resistance silicon wafer treated in the ninth step as a sacrificial layer, bake at 90°C for one hour, and then bake at 130°C Baking for half an hour, spin-coating a 2 μm thick positive resist on the sacrificial layer, photolithography through No. 5 mask plate, removing the positive resist after development, and obtaining the sacrificial layer pattern, and then curing the high-resistance silicon wafer at 200°C for 1 Hours;

Eleventh step evaporation deposition of Al-Si alloy film

Under a vacuum degree of 5×10 ^-5 Torr, evaporate and deposit an aluminum-silicon alloy film on the high-resistance silicon wafer treated in the tenth step, the silicon content and thickness of the aluminum-silicon alloy film are 4% and 0.5 μm, respectively;

The twelfth step corrodes the aluminum-silicon alloy film to form a bridging film

The high-resistance silicon wafer processed in the eleventh step is subjected to the No. 6 mask process of negative photolithography, and the high-resistance silicon wafer is placed in a H ₃ PO ₄ solution with a concentration ≥ 85% at 70°C to corrode aluminum The bubbles from the silicon alloy film to the phosphoric acid solution are very weak, forming a bridge film, and the high-resistance silicon wafer is cleaned with deionized water;

The thirteenth step removes the sacrificial layer

Plasma etching removes the negative resist and sacrificial layer on the high-resistance silicon wafer treated in the twelfth step. The bridging membrane is the movable contact piece of the MEMS switch. the

Compared with background technology, the present invention has the following advantages:

1. The filter is composed of a MEMS switch deposited on a silicon chip and a coplanar waveguide transmission line. The former replaces traditional PIN switching diodes, varactor diodes or FETs to realize the frequency reconstruction of the filter, and the latter replaces Instead of the traditional coplanar waveguide transmission line on the PCB, it has the advantages of compact and simple structure, small size, good isolation, low insertion loss, low power consumption of the control circuit, and high operating frequency. the

2. The filter is compatible with traditional IC technology, integrated on a high-resistance silicon substrate, has mature technology, low cost, and is suitable for mass production. the

Description of drawings

Fig. 1 is a schematic structural diagram of the reconfigurable microwave low-pass filter of the present invention. the

FIG. 2 is a schematic diagram of the No. 1 mask pattern. the

FIG. 3 is a schematic diagram of the No. 2 mask pattern. the

FIG. 4 is a schematic diagram of the No. 3 mask pattern. the

FIG. 5 is a schematic diagram of No. 4 mask pattern. the

FIG. 6 is a schematic diagram of No. 5 mask pattern. the

FIG. 7 is a schematic diagram of No. 6 mask pattern. the

Fig. 8 is the S parameter of the reconfigurable microwave low-pass filter before reconstruction. the

Fig. 9 is the reconstructed S-parameter of the reconfigurable microwave low-pass filter. the

Fig. 10 is the structure of the reconfigurable microwave low-pass filter before reconstruction. the

Fig. 11 is the equivalent circuit of the reconfigurable microwave low-pass filter before reconfiguration. the

Fig. 12 is the structure of the reconfigurable microwave low-pass filter after reconstruction. the

Fig. 13 is the equivalent circuit of the reconfigurable microwave low-pass filter after reconstruction. the

Detailed ways

The technical solution of the present invention will now be described in detail in conjunction with the accompanying drawings and embodiments. the

Example 1

The low-pass filter involved in this embodiment has exactly the same structure as the low-pass filter described in "Summary of the Invention", and details are not repeated here. The 3dB cut-off frequencies of the filter before and after reconstruction are 21GHz and 12GHz, respectively. the

The working principle of this embodiment. the

The reconfigurable low-pass filter can be reconfigured by turning off and on the five MEMS switches. As shown in FIG. , the other end is added on the first bias pad 40 and the third bias pad 42, then the first MEMS membrane bridge 30, the third MEMS membrane bridge 32 and the fifth MEMS membrane bridge 34 are closed due to electrostatic action, and the second MEMS The membrane bridge 31 and the fourth MEMS membrane bridge 33 are turned on, ignoring the parasitic effect of turning on the MEMS switch. The structure diagram at this time is shown in Figure 10, which is equivalent to the series connection of two small-unit low-pass filters, and its equivalent circuit diagram is shown in Figure 11. L1 is the equivalent inductance of the first signal line 70, the second signal line 71, the fifth signal line 74, the sixth signal line 75, and the seventh signal line 76, and L2 is the third signal line 72, the fourth signal line 73, The equivalent inductance of the fifth signal line 74 , the eighth signal line 77 and the ninth signal line 78 , C1 , C2 , and C3 are respectively the first MEMS membrane bridge 30 , the third MEMS membrane bridge 32 , and the fifth MEMS membrane bridge 34 . the

After reconfiguration, one end of the 35V voltage is applied to the first ground wire 50 and the second ground wire 51 , and the other end is applied to the second bias pad 41 and the fourth bias pad 43 . At this time, the second MEMS membrane bridge 31 and the fourth MEMS membrane bridge 33 are closed due to the electrostatic force, and simultaneously connect the first signal line 70, the third signal line 72, the sixth signal line 75 and the eighth signal line 77 to the It is connected to the second signal line 71, the fourth signal line 73, the seventh signal line 76 and the ninth signal line 78. One end of the 30V voltage is applied to the first ground line 50 and the second ground line 51, and the other end is applied to the first bias line. On the pressure pad 40, the first MEMS membrane bridge 30 and the fifth MEMS membrane bridge 34 are closed, and the third MEMS membrane bridge 32 is opened due to no static electricity, ignoring the parasitic capacitance of the switch, the structural diagram of the filter after reconstruction is shown in the figure 12. The filter at this time is equivalent to a filter with a unit structure similar to that of the original low-pass filter, but the length of the transmission line is twice the original. Its circuit structure is shown in Figure 13. L3 and L4 are the inductance formed by the bottom signal line, and C4 and C5 are respectively the capacitance formed by the first MEMS membrane bridge 30 and the second MEMS membrane bridge 34 and the bottom signal line. Because the length of the signal line after reconstruction is double that before reconstruction, the 3dB cut-off frequency of the filter is reduced from 21dB to 12dB, the in-band insertion loss is less than 1.3dB, and the out-of-band rejection is greater than 25dB, thus realizing the low-pass filter. refactor. the

The low-pass filter of the present invention is particularly suitable for use in phase-controlled filter arrays as a multi-band and broadband reconfigurable microwave low-pass filter, and has the advantages of small size, high frequency, and small insertion loss. In addition, the low-pass filter can also be used in the integration of radio frequency devices, contributing to the development of future mobile communications. the

Claims (2)

1. reconfigurable microwave low-pass filter that contains mems switch, contain three inputs, three outputs, five MEMS film bridges, four bias pad, two ground wires, six bias lines, nine holding wires and ten bridge piers, three inputs are respectively first input end (10), second input (11) and the 3rd input (12), three outputs are respectively first output (20), second output (21) and the 3rd output (22), five MEMS film bridges are respectively a MEMS film bridge (30), MEMS film bridge (31), the 3rd MEMS film bridge (32), the 4th MEMS film bridge (33) and the 5th MEMS film bridge (34), four bias pad are respectively first bias pad (40), second bias pad (41), the 3rd bias pad (42) and the 4th bias pad (43), two ground wires are respectively first ground wire (50) and second ground wire (51), six bias lines are respectively first bias line (60), second bias line (61), the 3rd bias line (62), the 4th bias line (63), the 5th bias line (64) and the 6th bias line (65), nine holding wires are respectively first holding wire (70), secondary signal line (71), the 3rd holding wire (72), the 4th holding wire (73), the 5th holding wire (74), the 6th holding wire (75), the 7th holding wire (76), the 8th holding wire (77) and the 9th holding wire (78), ten bridge piers are respectively first bridge pier (80), second bridge pier (81), the 3rd bridge pier (82), the 4th bridge pier (83), the 5th bridge pier (84), the 6th bridge pier (85), the 7th bridge pier (86), the 8th bridge pier (87), the 9th bridge pier (88) and the tenth bridge pier (89), it is characterized in that, this filter is the integrated circuit that is produced on the substrate of high resistant silicon chip, first ground wire (50) is parallel to each other with second ground wire (51), nine parallel cloth of holding wire are listed between first ground wire (50) and second ground wire (51), the parallel cloth of the 5th holding wire (74) is listed between first ground wire (50) and second ground wire (51), first holding wire (70), secondary signal line (71), the 3rd holding wire (72) and the 4th holding wire (73) are arranged in a straight line in the mode of their central axes, between first holding wire (70) and the secondary signal line (71), between secondary signal line (71) and the 3rd holding wire (72) and between the 3rd holding wire (72) and the 4th holding wire (73) space is arranged, first holding wire (70), secondary signal line (71), the 3rd holding wire (72) is listed between first ground wire (50) and the 5th holding wire (74) with the parallel cloth of the 4th holding wire (73), the 6th holding wire (75), the 7th holding wire (76), the 8th holding wire (77) and the 9th holding wire (78) are arranged in a straight line in the mode of their central axes, between the 6th holding wire (75) and the 7th holding wire (76), between the 7th holding wire (76) and the 8th holding wire (77) and between the 8th holding wire (77) and the 9th holding wire (78) space is arranged, the 6th holding wire (75), the 7th holding wire (76), the 8th holding wire (77) and the parallel cloth of the 9th holding wire (78) are listed between the 5th holding wire (74) and second ground wire (51), first bridge pier (80), second bridge pier (81), the 3rd bridge pier (82), the 4th bridge pier (83), the 5th bridge pier (84) is sequentially arranged in the outside of first ground wire (50), first bias line (60), second bias line (61), first bias pad (40) and the 6th bias line (65) are distributed in first bridge pier (80), second bridge pier (81), the 3rd bridge pier (82), the outside of the 4th bridge pier (83) and the 5th bridge pier (84), the 6th bridge pier (85), the 7th bridge pier (86), the 8th bridge pier (87), the 9th bridge pier (88), the tenth bridge pier (89) is sequentially arranged in the outside of second ground wire (51), the 3rd bias line (62), the 4th bias line (63), the 5th bias line (64), second bias pad (41), the 3rd bias pad (42) and the 4th bias pad (43) are distributed in the 6th bridge pier (85), the 7th bridge pier (86), the 8th bridge pier (87), the 9th bridge pier (88), the outside of the tenth bridge pier (89), first bridge pier (80), second bridge pier (81), the 3rd bridge pier (82), the 4th bridge pier (83) and the 5th bridge pier (84) respectively with the 6th bridge pier (85), the 7th bridge pier (86), the 8th bridge pier (87), the 9th bridge pier (88), it is right that the tenth bridge pier (89) is formed five bridge piers, first input end (10) is connected with right-hand member with the left end of first ground wire (50) respectively with first output (20), the 3rd input (12) is connected with right-hand member with the left end of second ground wire (51) respectively with the 3rd output (22), second input (11) and first holding wire (70), the 5th holding wire (74) is connected with the left end of the 6th holding wire (75), second output (21) and the 4th holding wire (73), the 5th holding wire (74) is connected with the right-hand member of the 9th holding wire (78), first bias line (60) is connected across between first bridge pier (80) and first bias pad (40), the 6th bias line (65) is connected across between first bias pad (40) and the 5th bridge pier (84), second bias line (61) is connected across between second bridge pier (81) and the 4th bridge pier (83), the 3rd bias line (62) is connected across between the 7th bridge pier (86) and second bias pad (41), the 4th bias line (63) is connected across between the 8th bridge pier (87) and the 3rd bias pad (42), the 5th bias line (64) is connected across between the 9th bridge pier (88) and the 4th bias pad (43), the one MEMS bridge film (30) is connected across between first bridge pier (80) and the 6th bridge pier (85), MEMS bridge film (31) is connected across between second bridge pier (81) and the 7th bridge pier (86), MEMS bridge film (31) be suspended in space between first holding wire (70) and the secondary signal line (71) and the space between the 6th holding wire (75) and the 7th holding wire (76) directly over, the 3rd MEMS bridge film (32) is connected across between the 3rd bridge pier (82) and the 8th bridge pier (87), the 3rd MEMS bridge film (32) be suspended in space between secondary signal line (71) and the 3rd holding wire (72) and the space between the 7th holding wire (76) and the 8th holding wire (77) directly over, the 4th MEMS bridge film (33) is connected across between the 4th bridge pier (83) and the 9th bridge pier (88), the 4th MEMS bridge film (33) be suspended in space between the 3rd holding wire (72) and the 4th holding wire (73) and the space between the 8th holding wire (77) and the 9th holding wire (78) directly over, the 5th MEMS bridge film (34) is connected across between the 5th bridge pier (84) and the tenth bridge pier (89).

2. described preparation method who contains the reconfigurable microwave low-pass filter of mems switch of claim 1 is characterized in that this method and IC process compatible adopt six mask plates, the concrete operations step altogether:

First step cleaning silicon chip

The high resistant silicon chip that thickness and diameter is respectively 550 μ m and two inches places H ₂O ₂: H ₂SO ₄=1: 1 mixed liquor boils to boiling over-emitting black exhaust, washed with de-ionized water, then silicon chip is put into a cleaning fluid and boil to boiling, washed with de-ionized water is put into No. two cleaning fluids to silicon chip at last and is boiled to boiling, deionized water rinsing, drying, oven dry, the prescription of a cleaning fluid are 27%NH ₄OH: 30%H ₂O ₂: deionized water=1: 2: 5, the prescription of No. two cleaning fluids are 37% HCL: 30%H ₂O ₂: deionized water=1: 2: 8;

The second step thermal oxidation

Be the silicon dioxide layer of 1 μ m with thermal oxidation method at the superficial growth thickness of high resistant silicon chip, fed dried oxygen in 10 minutes, fed wet oxygen in 100 minutes, add 10 minutes again and feed dried oxygen;

The 3rd step evaporation titanium layer and gold layer

Hydatogenesis titanium layer and gold layer successively on the silicon dioxide layer of the high resistant silicon chip of handling through second step, thickness is respectively 1000

With 3000

Temperature and vacuum degree in the vapourizing furnace are respectively 250 ℃ and 10 * 10 ^-5Torr;

Mask plate of the 4th positive glue photoetching of step, plating

The high resistant silicon chip of handling through the 3rd step is implemented mask plate technology of positive glue photoetching, under 1800 rev/mins the rotating speed, positive glue is covered on the high resistant silicon chip, by a mask plate the positive glue on the high resistant silicon chip is carried out photoetching, reserve the figure that needs plating, electrogilding layer, thickness are 2 μ m, form three inputs, three outputs, ten bridge piers and four bias pad, remove photoresist;

The 5th positive glue photoetching two of step, No. three mask plates are electroplated

With with the 4th the step identical positive glue photoetching method, by No. two mask plates and No. three mask plates the positive glue on the high resistant silicon chip is carried out photoetching successively, positive No. two mask plates of glue photoetching, electrogilding layer, thickness are 2 μ m, form two ground wires, nine holding wires, six roots of sensation bias line, positive No. three mask plates of glue photoetching, the electrogilding layer makes the thickness of three inputs, three outputs, four bias pad and ten bridge piers increase to 4 μ m by 2 original μ m, removes photoresist;

The negative glue photoetching of the 6th step, acid gilding layer, titanium layer

Negative No. two mask versions of glue photoetching, be placed in 130 ℃ the baking oven post bake after the development 30 minutes, plasma etching is 20 seconds then, successively gold layer, the titanium layer of not electroplating part are eroded at normal temperatures at last, keep three inputs, three outputs, two ground wires, nine holding wires, four bias pad, six roots of sensation bias line and ten bridge piers, the prescription of the solution of acid gilding is KI: I ₂: H ₂O=20g: 6g: 100ml, the prescription of the solution of corrosion titanium is K2[Fe (CN) ₆]: KOH: H ₂O=30g: 5g: 100ml;

The 7th step was removed negative glue

Adopt the oxygen gas plasma etching to remove negative glue on the high resistant silicon chip of handling through the 6th step, etching power, oxygen flow, etch period are respectively 50W, 60ml/min and 20 seconds;

The 8th one-step growth silicon nitride film

With the surface deposition one deck silicon nitride film of chemical vapor deposition at the high resistant silicon chip of handling through the 7th step, thickness is 0.3 μ m, and ammonia flow, silane flow rate and temperature are respectively 24ml/min, 560ml/min and 280 ℃;

No. four mask plates of the 9th positive glue photoetching of step, removal silicon nitride film

The high resistant silicon chip of handling through the 8th step is implemented No. four mask plate technologies of positive glue photoetching, cover the figure on the mask plate No. four with positive glue, the silicon nitride film that protection need keep is used SF ₆Gaseous plasma etch silicon nitride film, etching power, SF ₆The flow of gas and etch period are respectively 50w, 2.4ml/s and 1 minute and 50 seconds;

No. five mask plates of the tenth positive glue photoetching of step

Under 2000 rev/mins the rotating speed, spin coating one layer thickness is that the polyimide film of 2 μ m is as sacrifice layer on the surface of the high resistant silicon chip of handling through the 9th step, 90 ℃ were dried by the fire one hour down, dry by the fire half an hour down at 130 ℃ again, the thick positive glue of spin coating 2 μ m on sacrifice layer, by No. 5 mask plate photoetching, positive glue is removed in the back of developing, obtain the sacrifice layer figure, then the high resistant silicon chip is placed 200 ℃ to solidify 1 hour down;

The tenth step evaporation deposit alusil alloy film

5 * 10 ^-5Under the vacuum degree of Torr, evaporation deposition alusil alloy film on the high resistant silicon chip of handling through the tenth step, the siliceous and thickness of this alusil alloy film is respectively 4% and 0.5 μ m;

The 12 step corrosion alusil alloy film forms the bridge film

The high resistant silicon chip of handling through the 11 step is implemented negative No. six mask plate technologies of glue photoetching, at 70 ℃ of H that down this high resistant silicon chip are placed on concentration 〉=85% ₃PO ₄In the solution, the bubble that corrosion alusil alloy film is emerged to the phosphoric acid solution is very faint, forms the bridge film, with this high resistant silicon chip of washed with de-ionized water;

The 13 step was removed sacrifice layer

Plasma etching is removed negative glue and the sacrifice layer on the high resistant silicon chip of handling through the 12 step, plasma etching power, oxygen flow and nitrogen flow are respectively 50w, 60ml/s and 2.8ml/s, obtain five unsettled bridge films, this bridge film is exactly the mems switch movable contact flat.

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