CN118826690A - A multi-die stacked radio frequency device - Google Patents

Abstract

The invention provides a multi-die stacked radio frequency device, which belongs to the field of piezoelectric composite materials and comprises a first bare chip and a plurality of filter bare chips, wherein the filter bare chips are coupled with the front surface of the first bare chip, signal extraction is manufactured on the reverse surface of the first bare chip opposite to a coupling surface, the first bare chip comprises a multi-layer heterogeneous bonding substrate, a functionalized metal hole, a wafer level package and at least one surface acoustic wave filter manufactured on the front surface and the reverse surface of the first bare chip, the functionalized metal hole comprises at least one of a penetrating type via hole and/or a medium blocking type radio frequency via hole, and the surface acoustic wave filter is used for radio frequency signal communication through the functionalized metal hole. The functional metal holes can realize the series-parallel matching of capacitance and inductance of a plurality of filter bare chips and a plurality of film type surface acoustic wave filters on the two sides of the bare chips and the performance coupling promotion or isolation coexistence, the filter integration level is higher, and the loss is smaller.

Description

A multi-die stacked radio frequency device

Technical Field

The present invention belongs to the technical field of radio frequency devices, and in particular relates to a multi-die stacked radio frequency device.

Background Art

Spectrum resources are an indispensable foundation for modern communications and broadcasting technologies. Their effective management and rational use are crucial to ensuring the stability and quality of wireless communication services. Spectrum resources have extremely high economic value in modern society and are the basis for supporting key infrastructure such as mobile communications, Internet access, broadcast media and satellite communications.

With the upgrading of mobile terminals, the market demand requires the integration of more RF filters in a single terminal device. For example, a mobile phone has developed from a few filters in the past to 40 to 60 filters today. In the future, high-performance mobile phones will also need to integrate hundreds of filters. This poses a severe challenge to the miniaturization and packaging of filters. The miniaturization of filters compresses the design space of devices, resulting in a certain sacrifice in the comprehensive performance of filters.

The development of three-dimensional stacking technology enables filters to reduce the area occupied by RF modules, exchanging spatial height for area. However, it also brings problems of high packaging process costs and poor packaging reliability.

Summary of the invention

In order to solve the above problems, the present invention provides a multi-die stacked radio frequency device, which can integrate more filters in a unit space and can have comprehensive performance such as lower insertion loss and better isolation.

The present invention adopts the following technical solutions to solve the above problems:

A multi-die stacked radio frequency device comprises a first die and a plurality of filter dies, wherein the filter die is coupled to the front side of the first die, and a signal lead is made on the back side of the first die opposite to the coupling side, the first die comprises a multi-layer heterogeneous bonding substrate, a functionalized metal hole, a wafer-level package, and at least one surface acoustic wave filter made on the front and back sides of the first die, the functionalized metal hole comprises at least one of a through-type conductive hole and/or a dielectric-barrier radio frequency conductive hole, and the metallized pattern of the surface acoustic wave filter is connected to the radio frequency signal through the functionalized metal hole.

Furthermore, interconnection patterns are fabricated on the upper and lower surfaces of the through-type vias to form a three-dimensional spiral inductor, and a dielectric layer is fabricated on the dielectric barrier type RF vias to form a low-loss capacitor.

Furthermore, the medium in the dielectric-barrier RF via hole may be any layer in a multi-layer heterogeneous bonding substrate, and the thickness of the medium in the dielectric-barrier RF via hole is not greater than the thickness of the dielectric layer.

Furthermore, the first bare chip comprises a surface acoustic wave filter, coupling sites of multiple filter bare chips, metal interconnection lines and organic high polymers on both the front and back sides, and the coupling sites and the first surface acoustic wave filter transmit signals to the metallized holes through the first interconnection metal lines.

Furthermore, the organic high polymer constructs a cavity in the area of the surface acoustic wave resonator and seals the resonator. The wafer-level packaging includes the construction of the cavity above the resonator by the organic high polymer and the UBM production at the wafer coupling site. The UBM metal structure at the coupling site includes Ti-Cu-Ni, Ti-Cu-Ni-Sn, Ti-Cu-Ni-Pd-Au, Ti-Cu-Ni-Au, NiCr-Cu, NiCr-Cu-Sn, NiCr-Cu-Ni-Sn, and NiCr-Cu-Ni-Au.

Furthermore, the coupling sites of the multiple filter bare chips overlap with the positions of the functionalized metal holes on the first bare chip, and are connected and conductive through metal interconnects without overlapping. The area of the bare chip coupling sites is 1-3 times the area of the functionalized metal holes.

Furthermore, the bare chip coupling site on the first surface and the first surface acoustic wave filter transmit the signal to the metallized hole through the first interconnected metal line, and the first interconnected metal line connects, couples or isolates the first bare chip first surface acoustic wave filter, the filters of the multiple filter bare chips and the first surface metal hole according to design requirements.

Furthermore, the metallized hole position on the second surface and the second surface acoustic wave filter transmit the signal to the signal lead-out coupling site through the second interconnected metal line, and the second interconnected metal line connects and couples or isolates the signal at the metallized hole position on the second surface of the first bare chip, the second surface acoustic wave filter and the second surface signal lead-out coupling connection site according to design requirements.

Furthermore, the coupling method of the filter bare chip and the first bare chip includes metal ball implantation flip-up, metal bump-metal bump bonding, and electroplated metal column-pad flip-chip reflow.

Furthermore, the filter die includes at least one packaged RF filter die, specifically including one or more of a surface acoustic wave filter (SAW), a bulk acoustic wave filter (BAW), an integrated passive filter (IPD), a low temperature co-fired ceramic filter, and a millimeter wave filter.

Furthermore, the multilayer heterogeneous bonding substrate comprises a first thin film piezoelectric layer and a second thin film piezoelectric layer, a first isolation layer and a second isolation layer, a first absorption layer and a second absorption layer, and an intermediate substrate layer, the material properties and material parameters of which are independent of each other.

Furthermore, the materials of the first thin film piezoelectric layer and the second thin film piezoelectric layer include lithium niobate and lithium tantalate, the materials of the first isolation layer and the second isolation layer are low acoustic velocity materials, including silicon dioxide, the preparation processes of the first isolation layer and the second isolation layer materials are not necessarily the same, and the preparation processes include magnetron sputtering, ion beam sputtering, chemical vapor deposition, thermal oxidation, and gel-sol method. The materials of the first absorption layer and the second absorption layer capture electrons to improve the device quality factor Q value, the absorption layer material includes polycrystalline silicon, and the substrate layer is a high acoustic velocity material, including high-resistance silicon, silicon carbide, diamond, sapphire, and quartz.

Furthermore, the material properties include physical and chemical properties such as lattice structure, crystal type, dielectric constant, magnetic permeability, density, electro-optical effect, etc. of the crystal material; the material parameters include material thickness and material distribution area.

The multi-layer heterogeneous bonding sheet is made into through holes and metalized, the through hole sidewalls are sputtered with insulating layers, adhesive layers and metal layers, and the through holes are metallized and filled with electroplated copper to connect the upper and lower surfaces of the multi-layer heterogeneous bonding sheet.

The present invention also provides a method for manufacturing a multi-die stacked radio frequency device, the manufacturing method comprising the following steps:

S1: fabrication of the first die of multi-layer heterogeneous bonding;

S2: manufacturing functional metal holes of the first bare chip, making through holes at the through hole position by etching all layers, etching all layers except a dielectric layer of the first bare chip at the dielectric barrier hole position, sputtering insulating layers, adhesion layers and conductive layers in the holes after the etching of the above two types of holes is completed, electroplating metal copper in the holes until they are filled, and annealing;

S3: CMP grinding the front and back sides of the first bare chip to remove the surface electroplated metal layer until the piezoelectric film layer is completely exposed;

S4: fabricating at least one surface acoustic wave filter and a plurality of coupling connection sites and metal interconnection lines on a first surface of the first die;

S5: forming an organic polymer cavity on the first surface of the first bare chip to enclose the surface acoustic wave resonator region;

S6: fabricating at least one surface acoustic wave filter and a plurality of coupling connection sites and metal interconnection lines on the second surface of the first die;

S7: forming an organic polymer cavity on the second surface of the first bare chip to close the surface acoustic wave resonator region;

S8: making multiple filter bare chips;

S9: sequentially coupling the plurality of filter bare chips to the first surface of the first bare chip.

The beneficial effects of the present invention are:

1. The use of multi-layer heterogeneous bonding technology, through-hole etching technology and inter-die coupling technology of double-sided piezoelectric films can integrate more filters on a single chip, and the filter design space is larger, the insertion loss is lower, the isolation is better, the reliability is higher, and the device has better overall performance;

2. The layout of the metallized holes in the multi-layer heterogeneous bonding wafer structure is divided into multiple specifications. The size and arrangement of the metallized holes are different under each specification. The size and arrangement of the metallized holes under a certain specification are fixed and become one of the rules for the definition and design of the SAW filter pins, which is convenient for batch production of composite wafers;

3. The first absorption layer and the second absorption layer materials include polysilicon, silicon nitride, and metal, which can capture electrons and improve the device quality factor Q value;

4. The functionalized solid metal hole includes at least one of a through-type conductive hole on the upper and lower surfaces of the hole and a dielectric barrier type RF conductive hole in the middle. An interconnection pattern is made on the upper and lower surfaces of the through-type hole to form a three-dimensional spiral inductor. A dielectric layer is made in the dielectric barrier type solid hole to form a low-loss capacitor with a certain capacitance. The inductor and capacitor made on the basis of the functionalized solid metal hole can be used for circuit matching in multi-die stacked RF devices or connected in series and parallel to optimize the performance of a resonator.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation of the present invention, the following will briefly introduce the drawings required for the description of the specific implementation. The drawings described below are example diagrams of the novel RF front-end receiving surface acoustic wave filter module described above. Obviously, the drawings described below are only exemplary. For ordinary technicians in this field, other embodiment drawings can be derived from the provided drawings without creative work.

FIG1 is a structural diagram of a multi-die stacked RF device containing only through-type metal vias;

FIG2 is a schematic diagram of the distribution and connection of filters, pads and functionalized metal holes on the surface of a multi-layer heterogeneous bonded wafer;

FIG3 is a typical structure diagram of a multi-layer heterogeneous bonding wafer;

FIG4 is a schematic diagram of the structure of a multi-layer heterogeneous bonding wafer opening;

FIG5 is a schematic diagram of the structure of multi-layer heterogeneous bonding wafer through-hole metallization;

FIG6 is a schematic diagram of the structure of double-sided grinding and polishing of a multi-layer heterogeneous bonded wafer;

FIG7 is a schematic diagram of the structure of a double-sided surface acoustic wave filter fabricated on a multi-layer heterogeneous bonding wafer and wafer-level packaging;

FIG8 is a schematic diagram of the structure of the bare chip assembly ball planting;

FIG. 9 is a structural diagram of a multi-die stacked RF device including through-type and dielectric capacitor isolation metal holes.

In the figure: 1-interdigital transducer metal finger; 2-organic polymer cavity; 3-organic polymer; 4-die coupling site; 5-metal interconnection line; 6-functionalized metal hole; 7-second piezoelectric film layer; 8-second isolation layer; 9-second absorption layer; 10-substrate layer; 11-first absorption layer; 12-first isolation layer; 13-first piezoelectric film layer; 14-functionalized metal hole coupling panel; 15-filter die; 16-filter die and multi-layer heterogeneous bonding wafer coupling site; 17-functionalized metal Interconnection line between hole and coupling site; 18-short distance metal interconnection line; 19-long distance metal interconnection line; 20-multi-layer heterogeneous bonded wafer surface filter pad; 21-multi-layer heterogeneous bonded wafer surface filter; 22-multi-layer heterogeneous bonded wafer surface; 23-multi-layer heterogeneous bonded wafer surface metal pad; 25-functionalized metal hole after electroplating filling; 26-surface electroplated metal layer; 28-functionalized metal hole after etching; 29-through conductive hole after grinding and removing the surface metal layer; 30-dielectric barrier RF conductive hole.

DETAILED DESCRIPTION

The exemplary embodiments of the present patent will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present patent are shown in the accompanying drawings, it should be understood that the present patent can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present patent and to fully convey the scope of the present patent to those skilled in the art. It should be noted that the embodiments in the present patent and the features in the embodiments can be combined with each other without conflict. The present patent will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

Example 1

As shown in Fig. 1-2, the present invention provides a multi-die stacked RF device, including a first die and a plurality of filter die 15, the first die including a front and a back, the front being a first surface, the back being a second surface, the filter die 15 is coupled with the front of the first die, the coupling method of the filter die 15 with the first die includes metal ball implantation flip-flop, metal bump-metal bump bonding, electroplated metal column-pad flip-chip reflow, a signal lead is made on the back of the first die opposite to the coupling surface, the first die includes a multi-layer heterogeneous bonding substrate, a functionalized metal hole 6 penetrating the first die, and a wafer-level package, at least one thin film is made on each of the front and back sides of the first die A membrane-type surface acoustic wave filter metallization pattern, the surface acoustic wave filter metallization pattern is connected to the radio frequency signal through a functionalized metal hole 6; the front and back sides of the first bare chip include a surface acoustic wave filter, coupling sites of multiple filter bare chips, metal interconnects and organic high polymers, the coupling sites and the first surface acoustic wave filter transmit signals to the metallization holes through the first interconnected metal lines, and the filter bare chip includes at least one packaged radio frequency filter bare chip, specifically including one or more of a surface acoustic wave filter (SAW), a bulk acoustic wave filter (BAW), an integrated passive filter (IPD), a low-temperature co-fired ceramic filter, and a millimeter wave filter.

In this embodiment, the functionalized metal hole 6 only includes a through-type conductive hole, and the upper and lower surfaces of the through-type conductive hole are made into an interconnected pattern to form a three-dimensional spiral inductor. The inductor made on the basis of the functionalized metal hole 6 can be used for circuit matching in a multi-die stacked RF device or connected in series and parallel to optimize the performance of a certain resonator.

The organic polymer 3 constructs an organic polymer cavity 2 in the area of the acoustic surface wave resonator and seals the resonator. The wafer-level packaging includes the construction of the organic polymer cavity above the resonator and the UBM production of the wafer coupling site. The UBM metal structure of the coupling site includes Ti-Cu-Ni, Ti-Cu-Ni-Sn, Ti-Cu-Ni-Pd-Au, Ti-Cu-Ni-Au, NiCr-Cu, NiCr-Cu-Sn, NiCr-Cu-Ni-Sn, and NiCr-Cu-Ni-Au.

The coupling sites of the multiple filter bare chips 15 overlap with the functionalized metal hole positions on the first bare chip, and are connected and conductive through metal interconnections when they are not overlapped. The area of the bare chip coupling sites is 1-3 times the area of the functionalized metal holes. The coupling sites on the first surface and the first surface acoustic wave filter transmit signals to the metallized holes through the first interconnected metal wires. The first interconnected metal wires connect and couple or isolate the first surface acoustic wave filter of the first bare chip, the filters of the multiple filter bare chips, and the first surface metal holes according to design requirements. The metallized hole positions on the second surface and the second surface acoustic wave filters transmit signals to the signal lead-out coupling sites through the second interconnected metal wires. The second interconnected metal wires connect and couple or isolate the signals at the metallized hole positions on the second surface of the first bare chip, the second surface acoustic wave filter, and the second surface signal lead-out coupling connection sites according to design requirements.

In this embodiment, the multi-die stacked RF device structure includes: a first bare chip and multiple filter bare chips 15, the first bare chip includes a first piezoelectric film layer 13, a first isolation layer 12, a first absorption layer 11, a substrate layer 10, a second absorption layer 9, a second isolation layer 8, a second piezoelectric film layer 7, a functionalized metal hole 6, a functionalized metal hole coupling panel 14, a metal finger 1 of the interdigital transducer on the first bare chip, an organic polymer 3, an organic polymer cavity 2, a metal interconnection line 5, an interconnection line 17 between the functionalized metal hole and the coupling site of the first bare chip, a bare chip coupling site 4, the first piezoelectric film layer 13 and the second piezoelectric film layer 7 are lithium niobate films, and the crystal tangent and thickness of the two are not necessarily the same. According to the design requirements of the front and back surface acoustic wave filters, this embodiment uses professional software to perform multi-module coupled acoustic and electrical simulation before preparation to determine the filter performance corresponding to the piezoelectric material under multiple crystal directions, and different crystal material structures are arranged on the front and back sides. The crystal of the piezoelectric film layer 13 is designed on the first surface of the first bare chip. The tangent is 15°YX-lithium niobate and the thickness is 500nm. The crystal tangent of the second surface piezoelectric film layer 7 of the first bare chip is designed to be 128°YX-lithium tantalate and the thickness is 750nm. The material parameters and preparation process of the first isolation layer 12 and the second isolation layer 8 of the first bare chip are not necessarily the same. The first isolation layer 12 and the second isolation layer 8 are preferably silicon dioxide in the embodiment, which are prepared by magnetron sputtering. The embodiment adjusts the substrate temperature, sputtering atmosphere and ionization intensity in the magnetron sputtering to change the important material parameters such as the density and dielectric constant of silicon dioxide. The thickness of the first isolation layer 12 and the second isolation layer 8 is 500nm. The first absorption layer 11 and the second absorption layer 9 are made of polycrystalline silicon material. A polycrystalline silicon layer with a thickness of 1um is made on a single crystal substrate layer by sputtering. The substrate layer 10 is a high acoustic velocity material. Considering the good high acoustic impedance characteristics of the silicon substrate and the currently mature through silicon via (TSV) process, the embodiment selects a high-resistance silicon substrate with a silicon crystal orientation of (1,1,1) and a substrate silicon thickness of 500um.

For the piezoelectric film layer, the common etching methods at present are Ar physical etching and wet etching; however, wet etching is greatly affected by the anisotropy of the piezoelectric crystal material, which generally leads to poor hole morphology. Ar physical bombardment etching is a common practice in academia and industry. A mask is made on the surface of the piezoelectric film layer, and Ar physical bombardment etching is used to penetrate the piezoelectric film layer and the silicon dioxide isolation layer. CF4 and SF6 gases are used to perform cyclic etching on the silicon layer to remove the polysilicon absorption layer and the single crystal silicon substrate layer in the hole, so as to obtain a through hole with a diameter of 50 to 80 um; the through hole passes through the first bare chip, and the front and back signals are connected after metallization. In the embodiment, an insulating layer of silicon dioxide of 1 um, an adhesion layer of Ti of 0.3 um and an electroplating seed layer of 3 um are sputtered in the through hole after the manufacturing is completed, and the electroplating is filled and the metal copper on the surface is removed by CMP, and the surface is polished. At this time, the first and second surfaces of the first bare chip with no height difference between the metallized hole surface and the piezoelectric film and seamless connection are formed; the metal filling quality in the through hole can be detected by XRD.

A surface acoustic wave filter is manufactured on the surface of the first bare chip. The metal pattern on the first surface of the first bare chip is manufactured through mature semiconductor processing techniques such as coating, photolithography, development, evaporation coating, stripping, and bus bar thickening. Necessary metal interconnects and metal pads are also manufactured in the pattern according to the design.

As shown in FIG2 , in this embodiment, an incomplete surface acoustic wave filter 21, a multi-layer heterogeneous bonding wafer surface metal pad 23, and a short-distance metal interconnection line 18 are manufactured on the second surface of the first bare die. The multi-layer heterogeneous bonding wafer surface filter 21 has its own multi-layer heterogeneous bonding wafer surface filter pad 20, which is not completely dependent on the multi-layer heterogeneous bonding wafer surface metal pad 23 on the second surface of the first bare die. The diameter of the through-type via 6, the bare die coupling site 4, and the multi-layer heterogeneous bonding wafer surface metal pad 23 on the second surface is 120 um, which is used to couple with an external RF circuit, through the short-distance metal interconnection line 18, the metal interconnection line 5, and the long-distance metal interconnection line 19 arranged on the second surface. Used to couple with an external RF circuit; the bottom of the multi-layer heterogeneous bonded wafer surface metal pad 23 is a piezoelectric film layer without a through-type conductive hole 6 or a piezoelectric film layer with a through-type conductive hole 6. In this embodiment, a large-size cell is arranged on the second surface, including six multi-layer heterogeneous bonded wafer surfaces 22 of inconsistent sizes. Different multi-layer heterogeneous bonded wafer surface filters 21 are designed and manufactured in each multi-layer heterogeneous bonded wafer surface 22, and the gaps between each multi-layer heterogeneous bonded wafer surface filter 21 are distributed with multiple through-type conductive holes 6 and multiple multi-layer heterogeneous bonded wafer surface metal pads 23. The signal of the through-type conductive hole 6 is connected to the electrical signal of the first surface of the first bare chip.

A through-type via 6, a first piezoelectric film layer 13, a metal interconnection line 5, a short-distance metal interconnection line 18 and a long-distance metal interconnection line 19 are provided. On the one hand, the through-type via 6 transmits the electrical signal on the first surface to the metal pad 23 on the surface of the multi-layer heterogeneous bonding wafer through the metal interconnection line 5, the short-distance metal interconnection line 18 or the long-distance metal interconnection line 19, and then connects to the radio frequency circuit to play a role of short-distance conduction and integration. On the other hand, the performance of multiple filters is coupled, which increases more design space. Filters are respectively made on the front and back sides of the first bare chip to improve the isolation of the device, or a three-dimensional spiral inductor is formed by interconnecting the upper and lower surfaces of the through-type via 6 to connect to the filter to form a matching circuit to improve the specific indicators of the device, or a plurality of different filter ground terminals are connected in common to achieve out-of-band suppression in a specific frequency band, etc.

The first surface is directly coupled to the filter die 5, so the position specification of the metal pad 23 on the surface of the multi-layer heterogeneous bonding wafer is closely related to the size and layout of the filter die. After the filter die stacking and coupling on the first surface is connected to the die coupling site 4 and the through-type conductive hole 6 through the first die functionalized metal hole and the interconnection line 17 at the coupling site, or the bottom of the die coupling site 4 is directly in contact with the through-type conductive hole 6, and then the signal is transmitted to the second surface. The multi-layer heterogeneous bonding wafer surface filter 21 on the first surface conducts each signal end to the through-type conductive hole 6 through the first die functionalized metal hole and the interconnection line 17 at the coupling site. The first die functionalized metal hole and the interconnection line 17 at the coupling site can be mutually conductive. If the common ground end is connected through the first die functionalized metal hole on the first surface and the interconnection line 17 at the coupling site, the multi-layer heterogeneous bonding wafer surface filter 21 on the first surface can be coupled to the filter die, thereby increasing the combination of multiple filters and achieving the flexibility of coupling in performance, and improving the integration of the device.

The manufacturing method of the multi-die stacked RF device, the intermediate states of which are shown in FIG. 3 to FIG. 7 , and the specific steps are as follows:

1) Provide two double-sided polished and flat piezoelectric single crystal materials, the thickness of the piezoelectric single crystal materials is 250um, and after subsequent ion implantation and annealing and peeling, they become the second piezoelectric film layer 7 and the first piezoelectric film layer 13. The first piezoelectric crystal is 15°YX-lithium niobate, and the second piezoelectric crystal is 128°YX-lithium tantalate. When the wafer is cut down, the comprehensive performance of the surface acoustic wave filter is better. The comprehensive performance of the filter includes the passband insertion loss, bandwidth and quality factor. The first piezoelectric crystal material includes the upper surface and the lower surface of the wafer. The upper surface of the wafer is the first surface, and the lower surface of the wafer is the second surface. The first surface is the He ⁺ injected surface. The second piezoelectric crystal material includes the upper surface and the lower surface of the wafer. The upper surface of the wafer is the third surface, and the lower surface of the wafer is the fourth surface. The third surface is the He ⁺ injected surface.

2) He ⁺ is injected into the lithium niobate wafer, and the injection ion energy is selected according to the required film thickness (i.e., the injection depth). In this embodiment, the material of the first piezoelectric wafer is a lithium niobate film with a thickness of 500nm, and the material of the second piezoelectric wafer is a thin film lithium tantalate with a thickness of 750nm. The acceleration voltage and energy of the equipment are set to a certain range, so that the He ⁺ ion injection depth in 15°YX-lithium niobate reaches 500nm, and the He + ion injection depth in 128°YX-lithium tantalate reaches 750nm.

3) Provide a high-resistance silicon substrate as a substrate layer 10 for multi-layer heterogeneous bonding. The thickness of the high-resistance silicon substrate is 500um. The high-resistance silicon substrate is divided into a first surface and a second surface. A second absorption layer 9 and a first absorption layer 11 of polycrystalline silicon film are sputtered on the first and second surfaces respectively. The second absorption layer 9 and the first absorption layer 11 serve as absorption layers to capture electrons leaked from the wafer and improve the Q value of the device. The thickness of the polycrystalline silicon film is 1um.

4) A silicon oxide film is made on the surface of the polycrystalline silicon of the absorption layer. The silicon oxide film constitutes an acoustic low impedance layer, namely the second isolation layer 8 and the first isolation layer 12. The silicon oxide film can be grown on the surface of the polycrystalline silicon by thermal oxidation growth. The required thickness of the polycrystalline silicon is the approximate sum of the thickness of the grown silicon oxide and the thickness of the reserved absorption layer. Under this growth mode, the interface bonding between silicon oxide and polycrystalline silicon is perfect. The preparation of the silicon oxide film can also be prepared by sputtering. The purity and density of the generated silicon dioxide are adjusted by adjusting the parameters such as the atmosphere pressure and electric field ionization intensity of magnetron sputtering _O2 and Ar. Preferably, in this embodiment, dense silicon dioxide is generated on the surface of the wafer by reacting the silicon target with ionized O and under the action of the bias voltage. A silicon dioxide film with a thickness of 500nm is provided on the first surface and the second surface of the substrate layer 10.

5) The first surface of the 15°YX-lithium niobate piezoelectric single crystal material and the first surface of the silicon oxide wafer exhibit an activation effect superior to that of Ar under O ₂ and N ₂ plasma activation, forming strong hydrophilicity, which is conducive to hydrophilic bonding; and the piezoelectric wafer and the silicon oxide wafer are placed in the plasma activation under O ₂ and N ₂ atmosphere, which has physical and chemical effects, can remove impurities, break chemical bonds, and form hydroxyl groups and hydrogen bonds on the surface by reacting with water to enhance hydrophilicity. In the bonding process, the surface roughness of the wafer affects the bonding effect. Megasonic cleaning is required after plasma activation. Megasonic cleaning technology uses high-frequency sound waves to efficiently clean fine particles in the solution through sound pressure and acoustic flow effects to ensure that no pollutants remain, providing a high-quality foundation for the bonding process. In this embodiment, the silicon substrate and the 15°YX-lithium niobate piezoelectric wafer to be bonded are subjected to megasonic cleaning for 120s at a power of 300W.

6) The first surface of the activated and cleaned 15°YX-lithium niobate piezoelectric single crystal material and the first surface of the silicon oxide wafer are brought into contact with each other by activation. At this time, the surfaces of the lithium niobate and silicon oxide wafers have appropriate hydroxyl density. By applying pressure, the hydroxyl groups on the surfaces of the two wafers are brought close enough, and the interface force is used to spontaneously form a dehydration condensation reaction at room temperature, thereby achieving atomic-level wafer bonding.

7) Annealing reinforcement. The interface energy of the pre-bonded wafer will be enhanced after being stored at room temperature. This is mainly because the _H2O molecules gradually diffuse into the air or SiO2 _layer along the bonding interface. High temperature annealing can accelerate this process to form a stable connection, enhance the bonding strength, and reduce bubbles. However, conventional annealing can easily cause wafer breakage. The thermal expansion coefficients of lithium niobate crystals and silicon are very different. The step-by-step temperature rise and fall annealing process can relieve stress. In this embodiment, the pre-bonded wafer is subjected to step-by-step annealing reinforcement, rising from room temperature at a rate of 1°C/min to 90°C, and kept at this temperature for 5 hours, and then continued to rise to 150°C at a rate of 1°C/min and maintained for 10 hours, and then dropped to room temperature at a rate of 1°C/min.

8) Performance characterization. Bond strength is one of the most important characteristics in the bonding process. Low strength may cause wafer cracking. In this embodiment, the bonding strength is evaluated by testing the crack length using a dual cantilever beam test method. The bond strength tested in the embodiment reaches 1.94 J/cm ² , which can withstand mechanical, thermal and water stress corrosion in subsequent processing, providing a solid foundation for wafer stripping and device preparation.

9) The third surface of the 128°YX-lithium tantalate piezoelectric single crystal material and the second surface of the silicon oxide wafer are activated in O ₂ and N ₂ plasma, and then megasonic cleaning is performed. The megasonic cleaning technology uses high-frequency sound waves to efficiently clean the fine particles in the solution through sound pressure and acoustic flow effects, ensuring that no pollutants remain, providing a high-quality foundation for the bonding process. In this embodiment, the silicon substrate and the 128°YX-lithium tantalate piezoelectric wafer to be bonded are subjected to megasonic cleaning for 120S at a power of 300W.

10) The third surface of the activated and cleaned 128°YX-lithium tantalate piezoelectric single crystal material and the second surface of the silicon oxide wafer are brought into contact with each other by activation. At this time, the surfaces of the lithium niobate and silicon oxide wafers have appropriate hydroxyl density. By applying pressure, the hydroxyl groups on the surfaces of the two wafers are brought close enough, and the interface force is used to spontaneously form a dehydration condensation reaction at room temperature, thereby achieving atomic-level wafer bonding.

11) Annealing. The pre-bonded wafers are subjected to step-wise annealing, from room temperature to 90°C at a rate of 1°C/min, kept at this temperature for 5 hours, then continued to rise to 150°C at a rate of 1°C/min and maintained for 10 hours, and then dropped to room temperature at a rate of 1°C/min.

12) Performance characterization. In this embodiment, the bonding strength is evaluated by testing the crack length using a dual cantilever beam test method. The bonding strength tested in the embodiment reaches 1.97 J/cm ² , which can withstand mechanical, thermal and water stress corrosion in subsequent processing, and provides a solid foundation for wafer stripping and device preparation.

13) Preparation of piezoelectric film layer. First, keep it at 165℃ for 16h, then anneal it at 190℃ for 6h to further improve the bonding strength, and then raise the sample temperature to about 228℃ to separate the He ⁺ injection layer from the lithium niobate donor material, thereby separating the piezoelectric wafers on the front and back sides from the desired depth.

14) Double-sided grinding: Double-sided grinding is performed on the first bare chip after bonding and peeling to make the rough surface of the piezoelectric film smooth after peeling.

After the preparation steps above, a multilayer heterogeneous bonding wafer of double-sided piezoelectric film is obtained as shown in Figure 3. Then, through-type via hole production and through-type via hole metallization are performed.

15) A soft mask material is made on the surface of the positive and negative piezoelectric film layer. In this embodiment, photoresist HSQ is used, and holes required for etching are made after photolithography and development.

16) Use an Ar ion etcher to etch the front and back thin film layers including the piezoelectric thin film layer and the isolation layer. Adjust the voltage and gas atmosphere of the Ar ions to control the side wall angle of the hole etching so that it is close to the vertical angle of the side wall etching.

17) The polysilicon layer and the high-resistance silicon layer are etched using a mature TSV process to obtain an etched functionalized metal hole 28, and then ultrasonic cleaning is performed to remove impurities in the hole to obtain the wafer structure shown in FIG. 4 .

18) Sputter the insulating layer on the inner wall of the through hole. In this embodiment, the thickness of the sputtered silicon oxide layer is 300nm, the thickness of the sputtered deposited metal Ti is 300nm, and the thickness of the electroplated seed layer Cu is 3000nm. In this embodiment, a sputtering machine with a high aspect ratio coverage capability greater than 5:1 is selected to achieve uniform coverage of the hole wall insulating layer, adhesion layer, and electroplated seed layer.

19) Electroplating functionalized metal holes. In this embodiment, the plating solution formula and the distribution of the plating potential are adjusted to allow the metal copper in the through hole to be solidly filled. The structure after filling is shown in FIG5 , wherein the attached metal is plated on the surface of the wafer to form a surface electroplated metal layer 26, and the electroplated metal is obviously recessed at the through hole position to form a through-type conductive hole 25 after electroplating filling.

20) Double-sided grinding and polishing: CMP grinding and polishing are performed on both sides of the prepared first bare chip until the surface of the piezoelectric film layer is completely exposed, and polishing is performed to obtain the structure of Figure 6. After the surface metal layer is removed by grinding, the through-type via 29 is flush with the wafer surface and there is no metal residue. The flatness parameters such as PTTV and TTV within the chip meet the wafer standard.

21) Preparation and packaging of the surface acoustic wave filter on the first surface of the first bare chip. The chip is prepared into a metal pattern including electroplated interconnection by photolithography and stripping process. The first surface of the first bare chip is subjected to photoresist spin coating, photomask exposure, and TMAH development to obtain a series of strip/slit photoresist patterns, and metal Ti10nm-Al300nm is evaporated. The metal strip is removed by stamping and stripping with NMP stripping liquid, leaving the metal fingers 1 and metal interconnection lines 5 of the interdigital transducer on the first bare chip, and the interconnection lines 17 between the functionalized metal holes of the first bare chip and the coupling sites. A dry film of an organic high molecular polymer 3 is attached to the first surface in a vacuum and bubble-free manner, then baked and then exposed to i-line. After development with a special developer for the dry film, the surface of the resonator and the coupling pad is exposed. Referring to the organic high molecular polymer cavity 2, the bare chip coupling site 4, the metal interconnection line 5, and the through-type via 6 in FIG. 7 , a window without damage or pollution is formed in the resonator and coupling pad area. The dry film in other areas is tightly attached to the surface after baking, and then the first layer of dry film is cured at 200° C. for 2 hours to allow the dry film to undergo a sufficient chemical reaction.

22) A second negative dry film is prepared on the first surface of the first bare chip. The second dry film is laminated to the first bare chip without gaps or bubbles in a vacuum environment, then baked and then exposed to i-line. After development with a special developer for the dry film, a window with exposed coupling sites and no damage or pollution on the surface is obtained. Referring to the bare chip coupling sites 4 and through-type vias 6 in FIG. 7 , the dry films in other areas are tightly bonded to the surface after baking, thereby constructing an organic high molecular polymer cavity 2 above the resonator. The second dry film is then cured at 200° C. for 2 hours to allow the dry film to undergo a sufficient chemical reaction.

23) The second surface acoustic wave filter of the first bare chip is prepared and packaged, similar to step 21.

24) Preparing a second negative dry film on the second surface of the first die, similar to step 22.

25) Make a bare chip assembly. Referring to Figures 1, 2, and 8, the filter bare chip 15 includes surface acoustic wave filters (SAW), bulk acoustic wave filters (BAW), integrated passive filters (IPD), low temperature co-fired ceramic filters, millimeter wave filters, etc. In this embodiment, six different bare chips are made and packaged. Then, a plurality of filter bare chips with a diameter of 100um and a height of 50um and a multi-layer heterogeneous bonding wafer coupling site 16 are made on the surface coupling site of the packaged filter bare chip 15 by using a gold wire ultrasonic pressing and ball planting method, and the wafer is diced and cut into small core particles, and then the small core particles of various types of wafers are successively turned upside down on the surface 22 of the multi-layer heterogeneous bonding wafer, so as to realize multi-die stacking (Figure 1).

Embodiment 2:

As shown in Figure 9, the functionalized metal hole 6 includes a through-type conductive hole and a dielectric barrier type RF conductive hole 30. The dielectric in the dielectric barrier type RF conductive hole 30 can be any layer in the multi-layer heterogeneous bonding substrate, and the thickness of the dielectric in the dielectric barrier type RF conductive hole is not greater than the thickness of the dielectric layer; the upper and lower surfaces of the through-type conductive hole are made into interconnected patterns to form a three-dimensional spiral inductor, and the dielectric barrier type RF via 30 is made into a dielectric layer to form a low-loss capacitor. The inductor and capacitor made on the basis of the functionalized metal hole 6 can be used as circuit matching by a multi-die stacked RF device or can be connected in series and parallel to optimize the performance of a resonator. Other technical features are the same as those in Example 1.

The present embodiment provides a multi-die stacked RF device, the device structure includes: a first bare chip and multiple filter bare chips, the first bare chip includes a first piezoelectric film layer 13, a first isolation layer 12, a dielectric layer 30 extending from the first isolation layer, a first absorption layer 11, a substrate layer 10, a second absorption layer 9, a second isolation layer 8, a second piezoelectric film layer 7, a functionalized metal hole 6, a functionalized metal hole coupling panel 14, metal fingers 1 of the interdigital transducer on the first bare chip, an organic polymer 3, an organic polymer cavity 2, a metal interconnection line 5, an interconnection line 17 between the functionalized metal hole of the first bare chip and the coupling site, a bare chip coupling site 4, the first piezoelectric film layer 13 and the second piezoelectric film layer 7 are lithium niobate films, and the crystal tangent and thickness of the two are not necessarily the same.

This embodiment is similar to Embodiment 1 in structure and process flow, with the most important difference being that the functionalized metal hole 6 of this embodiment includes a through-type metal hole and a dielectric barrier type RF via 30. The dielectric barrier type RF via 30 is exempted from etching of certain material layers of a multi-layer heterogeneous bonded wafer, and is more complicated in manufacturing process than Embodiment 1, involving double-sided alignment etching. By making alignment marks on the front and back sides of the wafer, such as alignment through holes, high-precision front and back alignment can be achieved, so that after etching away the surface piezoelectric film on the front side, etching of multiple layers of material is performed on the back side, and the etching formula and time can be well controlled.

Based on the process of Example 1, steps 15 to 19 are modified. The process of the modified part of this embodiment is as follows:

15) A soft mask material is made on the surface of the positive and negative piezoelectric film layer. In this embodiment, a photoresist HSQ is used, and holes to be etched are made after photolithography and development;

16) Use an Ar ion etcher to etch the front and back thin film layers including the first and second piezoelectric thin film layers and the second isolation layer. Adjust the voltage and gas atmosphere of the Ar ions, control the Ar ion etching depth, and stop etching at the specified depth. Control the side wall angle of the hole etching to make it close to the vertical angle of the side wall etching;

17) Etching the first absorption layer 11, the second absorption layer 9 and the middle substrate layer 10 of the polysilicon material from the back side using a mature TSV process, and then ultrasonically cleaning to remove impurities in the hole;

18) Sputtering the insulating layer on the inner wall of the through hole. In this embodiment, a 300nm silicon oxide layer is sputtered, and a 300nm metal Ti and a 3000nm electroplated seed layer Cu are sputtered and deposited. In this embodiment, a sputtering machine with a high aspect ratio coverage capability greater than 5:1 is selected to achieve uniform coverage of the hole wall insulating layer, the adhesion layer, and the electroplated seed layer;

19) Electroplating functionalized metal holes. In this embodiment, the formula of the electroplating solution and the distribution of the electroplating potential are adjusted to make the metal copper in the through holes and blind holes solidly filled.

It should be noted that the content and exemplary embodiments of this article are only used to illustrate the technical solution of this patent, but the implementation of this patent is not limited by the above content. Any other changes, modifications, substitutions, combinations, etc. that do not deviate from the innovative essence and principles of this patent are included in the protection scope of this patent. For those skilled in the art, the specific meanings of the above terms in the patent can be understood according to the specific circumstances.

Claims (10)

1. A multi-die stacked RF device, characterized in that it comprises a first die and a plurality of filter dies, wherein the filter die is coupled to the front side of the first die, and a signal lead is made on the back side of the first die opposite to the coupling side, the first die comprises a multi-layer heterogeneous bonding substrate, a functionalized metal hole, a wafer-level package, and at least one surface acoustic wave filter made on the front and back sides of the first die, the functionalized metal hole comprises at least one of a through-type conductive hole and/or a dielectric-barrier RF conductive hole, and the surface acoustic wave filter communicates RF signals through the functionalized metal hole. 2. A multi-die stacked RF device according to claim 1, characterized in that: the upper and lower surfaces of the through-type vias are made into interconnected patterns to form a three-dimensional spiral inductor, and the dielectric barrier RF vias are made into a dielectric layer to form a low-loss capacitor. 3. A multi-die stacked RF device according to claim 2, characterized in that the medium in the dielectric barrier type RF via hole can be any layer of a multi-layer heterogeneous bonding substrate, and the thickness of the medium in the dielectric barrier type RF via hole is not greater than the thickness of the dielectric layer. 4. A multi-die stacked RF device according to claim 1, characterized in that: the first bare chip comprises a surface acoustic wave filter, coupling sites of multiple filter bare chips, metal interconnects and organic polymers on both sides, and the coupling sites and the first surface acoustic wave filter transmit signals to the metallized holes through the first interconnected metal lines. 5. A multi-die stacked RF device according to claim 4, characterized in that: the organic polymer constructs a cavity in the area of the surface acoustic wave resonator and seals the resonator, and the wafer-level packaging includes the organic polymer cavity construction above the resonator and the UBM production of the wafer coupling site. 6. A multi-die stacked RF device according to claim 4, characterized in that: the coupling sites of the multiple filter bare chips overlap with the positions of the functionalized metal holes on the first bare chip, and are connected and conductive through metal interconnects without overlapping, and the area of the bare chip coupling sites is 1-3 times the area of the functionalized metal holes. 7. A multi-die stacked RF device according to claim 1, characterized in that: the coupling method between the filter die and the first die includes metal ball implantation flip-flop, metal bump-metal bump bonding, and electroplated metal column-pad flip-chip reflow. 8. A multi-die stacked RF device according to any one of claims 1 to 7, characterized in that the filter die comprises one or more of a surface acoustic wave filter (SAW), a bulk acoustic wave filter (BAW), an integrated passive filter (IPD), a low temperature co-fired ceramic filter, and a millimeter wave filter. 9. A multi-die stacked RF device according to any one of claims 1 to 7, characterized in that the multi-layer heterogeneous bonding substrate comprises a first thin film piezoelectric layer and a second thin film piezoelectric layer, a first isolation layer and a second isolation layer, a first absorption layer and a second absorption layer, and an intermediate substrate layer, whose material properties and material parameters are independent of each other. 10. A method for manufacturing a multi-die stacked radio frequency device, the method comprising the following steps: S1: fabrication of the first die of multi-layer heterogeneous bonding; S2: manufacturing functional metal holes of the first bare chip, making through holes at the through hole position by etching all layers, etching all layers except a dielectric layer of the first bare chip at the dielectric barrier hole position, sputtering insulating layers, adhesion layers and conductive layers in the holes after the etching of the above two types of holes is completed, electroplating metal copper in the holes until they are filled, and annealing; S3: CMP grinding the front and back sides of the first bare chip to remove the surface electroplated metal layer until the piezoelectric film layer is completely exposed; S4: fabricating at least one surface acoustic wave filter and a plurality of coupling connection sites and metal interconnection lines on a first surface of the first die; S5: forming an organic polymer cavity on the first surface of the first bare chip to enclose the surface acoustic wave resonator region; S6: fabricating at least one surface acoustic wave filter and a plurality of coupling connection sites and metal interconnection lines on the second surface of the first die; S7: forming an organic polymer cavity on the second surface of the first bare chip to close the surface acoustic wave resonator region; S8: making multiple filter bare chips; S9: sequentially coupling the plurality of filter bare chips to the first surface of the first bare chip.