CN102508777A - In-circuit emulator device supporting multiple lower layer interfaces - Google Patents
In-circuit emulator device supporting multiple lower layer interfaces Download PDFInfo
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Abstract
The invention relates to an in-circuit emulator device supporting multiple lower layer interfaces. The in-circuit emulator device comprises a debug command receiving unit, a command parsing and executing unit, a JTAG (Joint Test Action Group) interface driving unit and a data encapsulating unit, wherein the debug command receiving unit is used for receiving and checking a debug command from a PC (Personal Computer); the command parsing and executing unit is used for parsing a command and resolving the command into a plurality of microoperations; the JTAG interface driving unit is used for parsing and executing the microoperations, and converting the microoperations into JTAG interface signals to drive a target CPU (Central Processing Unit), or reading data from the target CPU; and the data encapsulating unit is used for different target CPU lower layer interfaces. The command parsing and executing unit is used for resolving the same commands in a same way, while the JTAG interface driving unit is provided with a plurality of microoperation control state machines corresponding to the different lower layer interfaces respectively, and one of the microoperation control state machines corresponding to the lower layer interface is used through the arrangement. The in-circuit emulator device disclosed by the invention supports the multiple lower layer interfaces communicated with the CPU simultaneously, so that the production cost is effectively reduced, and the difficulty in program development is decreased.
Description
Technical field
The present invention relates to a kind of embedded type CPU in-circuit emulator, relate in particular to a kind of in-circuit emulator of supporting the multiple physical layer interface that is connected with target CPU.
Background technology
At present, embedded technology is used ubiquitous in actual life, travelling at home, and traffic control, radio communication, multimedia recreations etc. all have been applied to embedded technology.In embedded type CPU program development debug process, the program development personnel generally can use in-circuit emulation and download debugged program, breakpoint, single step execution are set, observe, revise processor register and memory variable.In-circuit emulator is the intermedium that connects processor debugging program and target CPU on the PC, realizes communicating by letter between the debugging software and target CPU on the PC.And PC debugging software and target CPU communicate by letter in fact that in-circuit emulator receives the debug command from the PC debugging software; And resolve command, inform how CPU should operate, if CPU has rreturn value; In-circuit emulator then continues to read the CPU return data, and the PC debugging software is given in passback.Debugging software obtains the CPU internal data with this, and the program development personnel are according to these data determining programs correct execution whether.
At present, generally all communicate by letter through USB interface between in-circuit emulator and the PC debugging software, in-circuit emulator is in PC debugging software interface end, and is unified basically to the processing mode of data.And on the other hand, though most of CPU all support to carry out on-line debugging with the JTAG communication mode,, the physical layer interface of different embedded type CPUs and in-circuit emulator but also has nothing in common with each other.To such an extent as to, if the program development personnel need select other processor for use, just need buy new in-circuit emulator again, increased cost; Also need relearn the use of new in-circuit emulator, increase the difficulty of program development.
Summary of the invention
In order to overcome the production cost that existing in-circuit emulator causes with the cpu i/f disunity and the deficiency of development difficulty increase, the present invention provides a kind of and supports multiple physical layer interface of communicating by letter with CPU simultaneously, effectively reduces production costs, reduces the in-circuit emulation apparatus of the multiple physical layer interface of support of the difficulty of program development.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of in-circuit emulation apparatus of supporting multiple physical layer interface, said in-circuit emulation apparatus comprises:
The debug command receiving element; In order to receiving order data, and the form of order is carried out the correctness inspection, for the order of correct format from the PC debugging software; The debug command receiving element can send operation requests to command analysis and performance element, does not deal with for the order of format error;
Command analysis and performance element; In order to resolving from the operation requests of debug command receiving element; And microoperation is resolved in operation according to the command type that parsing obtains, send the interface conversion request with the form of microoperation to said jtag interface driver element;
The jtag interface driver element in order to receive the microoperation conversion request of command interpretation and performance element, sends the jtag interface drive signal to target CPU, or from target CPU reading of data; The JTAG driver element sends jtag interface driving completion signal to said command analysis and performance element after each microoperation drives completion;
The data encapsulation unit in order to reading under the debug command, receives data that the jtag interface driver element returns and data is sent back to the PC debugging software according to setting form encapsulation back by byte.
As preferred a kind of scheme: in said command analysis and the performance element, resolve the order of carrying out and comprise: assistant adjustment location register read write command and the memory read write order that links to each other with target CPU among target CPU general-purpose register read write command, target CPU control register read write command, the target CPU.
As preferred another kind of scheme: in said command analysis and the performance element; Microoperation comprises: backup CPU general-purpose register; Recover the CPU general-purpose register, upgrade the CPU general-purpose register, read the CPU general-purpose register; Backup CPU assistant adjustment unit context register recovers CPU assistant adjustment unit context register and upgrades CPU assistant adjustment unit context register.
Further, said command analysis and performance element resolve to a plurality of microoperations with the debug command of PC, and control jtag interface driver element is accomplished each microoperation step according to the order of sequence.
Said command analysis resolves to identical microoperation combination with performance element to identical debug command, and irrelevant with the physical layer interface of linking objective CPU.
As preferred another scheme: said jtag interface driver element comprises microoperation control state machine and a public TAP state machine, the corresponding a kind of physical layer interface with the TAP controller of each microoperation control state machine.
Further; In the said jtag interface driver element, the microoperation control state machine is at first resolved microoperation and corresponding parameters thereof, and some parameters that then parsing obtained are input to the TAP state machine; The microoperation control state machine starts the TAP state machine, and waits for TAP state machine end of run.
Further, in the said jtag interface driver element, select to use one of them microoperation control state machine, realize support thus multiple physical layer interface through the register in the setting device.
Beneficial effect of the present invention mainly shows: 1) debug command implementation is unitized.The present invention has realized for the command execution process of different physical layer interfaces unified through debug command being resolved into the microoperation combination.2) extensibility is good.The present invention makes overall architecture clear through the execution of upper layer commands and the driving of physical layer interface are separated, and extensibility is good, as long as microoperation control state machine of design just can realize the support to a kind of new physical layer interface.
Description of drawings
Fig. 1 is an in-circuit emulator equipments overall structure synoptic diagram.
Fig. 2 is an exemplary plot of writing storage debug command form.
Fig. 3 is a debug command receiving element inner structure synoptic diagram.
Fig. 4 is command analysis and performance element inner structure synoptic diagram.
Fig. 5 is a jtag interface driver element inner structure synoptic diagram.
Fig. 6 is a data encapsulation unit inner structure synoptic diagram.
Embodiment
Below in conjunction with accompanying drawing the present invention is done and to further describe.
With reference to Fig. 1～Fig. 6, a kind of in-circuit emulation apparatus of supporting multiple physical layer interface, said in-circuit emulation device are to receive debug command with the form of frame.Frame is made up of some bytes, and first byte is always 0x68, the beginning of marking command frame, and a back to back byte is a command code, is thereafter the parameter of order band, last byte is the end of 0x16 identification frames always.
Said in-circuit emulation apparatus comprises:
The debug command receiving element: with reference to Fig. 3, this unit receives the debug command that the PC debugging software sends with the mode of 8 bit parallels, comprises the behavior of reading of a state machine control data in the unit.This unit is not empty at the debug command buffer memory, and this unit is that idle condition or command analysis and performance element send reading request signal when needing data; Be that the data of reading under the idle condition are considered to command frame and begin sign in the unit; If data are not 0x68, then the unit returns idle condition, if frame begins to identify correctly then continues the read next byte data; And think that these data are command code; The form comparison is carried out in this command code and current all orders of supporting after the sense command sign indicating number, if command format mistake then do not deal with, the unit comes back to idle condition; If command format canonical is isolated command type and issued command analysis and performance element as operation requests from command code, and WOO is resolved and performance element executes debug command and send command execution completion signal; Last byte of debug command receiving element sense command frame then, command frame finishes sign, and comes back to idle condition.
Command analysis and performance element: with reference to Fig. 4; Be responsible for resolving from the operation requests of debug command receiving element; And operation is divided into a plurality of microoperations, and send the interface conversion request to the jtag interface driver element with the microoperation form according to the order that parsing obtains.This unit analyzes specific instructions according to the operation requests that the debug command receiving element sends, and these orders comprise the memory read write order, CPU register read write order and CPU assistant adjustment location register read write command.Comprise 3 state machines in command analysis and the performance element and be responsible for execution, and the result who is resolved by mentioned order activates corresponding state machine these 3 types of orders.One or two state in each above-mentioned microoperation corresponding states machine is referred to as the microoperation state: for the microoperation that can accomplish at a state, state machine sends the microoperation request and waits for the completion of microoperation at next state at a microoperation state; Microoperation for two states completion; State machine is in the required parameter of some microoperations of preceding state initialization; Comprise and send the data in the data read command frame in the debug command, send the microoperation request and wait for the microoperation completion at next state at second state.Command analysis and performance element send the data encapsulation request to the data encapsulation unit when the debug command of reading type begins to carry out, the unit completion signal of when state machine is accomplished order, can giving an order.3 state machines all can send debug command data read request signal in this unit, and these 3 signals are through one or output to the debug command receiving element; The completion signal of also all can giving an order is equally through one or output to the debug command receiving element; The microoperation request signal that three state machines send is through a data selector switch output; The selection signal of selector switch depends on the mentioned order analysis result; The debug command data then through the debug command receiving element through to this unit, these data also can be through to the jtag interface driver element simultaneously.
The jtag interface driver element: with reference to Fig. 5, this unit is responsible for carrying out the microoperation order from command analysis and performance element, sends the jtag interface drive signal to target CPU, or from target CPU reading of data; The JTAG driver element sends jtag interface driving completion signal to said command analysis and performance element after each microoperation drives completion.Comprise several microoperation control state machine in the jtag interface driver element with a public TAP state machine and carry out the data shift register that JTAG communicates by letter; The corresponding a kind of physical layer interface of each microoperation control state machine selects to activate one of them microoperation control state machine when this unit can receive the microoperation request according to being arranged on of user.In the microoperation control state machine; Obtain the required parameter of TAP state machine and activate the TAP state machine beginning interface conversion through resolving the microoperation order; The TAP state machine parameter of a plurality of microoperation control state machine outputs is through data selector driven in common TAP state machine, and the TAP state machine parameter of output comprises instruction, instruction length, data and data length.Little manipulation control state machine is when the microoperation of type is read in execution; Can read the data that target CPU returns and pass to the data encapsulation unit through driving the TAP state machine; And changeing the length information that unit transmission data transmit data before to the data envelope; Can, all valid data send signal and inform that the data encapsulation cell data has all read completion after send completion simultaneously.
Data encapsulation unit: with reference to Fig. 6; This unit is responsible in needing the implementation of debug command that data turn back to debugging software; Reception is from the data of jtag interface driver element, and data are packaged into a frame according to the similar form of debug command frame, passes back then to PC and holds.What comprise a state machine control data in this unit reads and encapsulates process of transmitting; State machine is initialised when idle condition is received from debug command and resolution unit data sent package request; Read the data that the jtag interface driver element transmits then; Encapsulation of data, and passback is held to PC.Reading of data, encapsulation are to carry out synchronously with the passback process, and add incoming frame at data head begins to identify 0x68 and data length to encapsulation process exactly, add at the data end and finish sign 0x16.This unit sends last end byte to the PC end after receiving that jtag interface driver element data sent reads the completion signal, come back to idle condition.
In this embodiment execution is resolved in " memory read " order.The debug command data that PC debugging software 8 sends are as shown in Figure 2, and concrete expression is: write one 32 data 0x4433AA55 to storage address 0x8000FCA0 place.
When debug command receiving element 2 receives first byte 0x68 of debug command data under idle condition, represent the beginning of once new debug command data transmission, and will be command byte in the data that receive next time; After debug command receiving element 2 receives command byte 0x44, all command codes of this order and current support are relatively seen whether be effective order; Command format is correct, and debug command receiving element 2 sends operation requests to command analysis and performance element 3, can continue to receive the debug command data simultaneously and issue command analysis and performance element 3 and jtag interface converting unit 5.
Command analysis and performance element 3 receive under idle condition after the operation request signal that debug command receiving element 2 sends, and command code 0x44 is carried out command analysis; Parsing is learnt this order for " memory write order ", and to want the width of write data be 32.Command analysis and performance element receive next byte data 0x03, and expression need write 4 bytes to storer, just a write operation.This unit is that this order is resolved into to the implementation of this order: backup CPU assistant adjustment unit context register, backup CPU general-purpose register R0 and R1, renewal CPU general-purpose register R0 and R1, renewal CPU assistant adjustment unit context register, recovery CPU general-purpose register R0 and R1, these 9 microoperations combinations of recovery CPU assistant adjustment unit context register.Command analysis and performance element 3 are done following the processing to each microoperation successively: send the jtag interface conversion request to jtag interface driver element 5, and wait for this time of jtag interface driver element completion conversion.
Jtag interface driver element 5 receives under idle condition after the jtag interface conversion request that command analysis and performance element 3 send; The microoperation control state machine 4 corresponding with current goal CPU physical layer interface resolved the microoperation that will handle; And 4 parameter: IR_data, IR_length, DR_data, the DR_length of generation control TAP state machine; Wherein IR_length is the bit length of IR_data, and DR_length is the bit length of DR_data; The microoperation control state machine is passed to TAP state machine 6 with parameter, and starts the conversion of TAP state machine; TAP state machine 6 sends to microoperation control state machine 4 after converting and converts signal, and microoperation control state machine 4 is receiving that can send jtag interface to command analysis and performance element 3 after converting signal drives and accomplish signal.Each microoperation implementation is following successively:
1) in carrying out the unit context register microoperation of backup CPU assistant adjustment; TAP state machine 6 produces the JTAG signal and drives the jtag interface that is connected with target CPU, and target CPU assistant adjustment unit can turn back to jtag interface driver element 5 through jtag interface with context register; The jtag interface driver element is after TAP converts, and the value that target CPU is returned is kept at the current microoperation of completion in the register;
2) in carrying out backup CPU general-purpose register R0 microoperation; Microoperation control state machine 4 needs startup TAP state machine twice: at first; CPU assistant adjustment unit context register is write in the request of microoperation control state machine; 4 parameters of TAP state machine are set and start the TAP state machine; DR_data in the parameter is the order code of the instruction " mov r0, r0 " of CPU at this moment, and CPU carries out this instruction also will need the value (value of R0 register) of write-back to be written to CPU assistant adjustment unit context register; Microoperation control state machine then 4 starts the TAP state machine for the second time to be changed, and reads CPU assistant adjustment unit context register, and the value that target CPU returns is kept at the current microoperation of completion in the register;
3) execution backup CPU general-purpose register R1 microoperation is similar with backup CPU general-purpose register R0 microoperation;
4) in carrying out renewal CPU general-purpose register R0 microoperation; The microoperation control state machine need be read debug command receiving element 2 data sent: at first, microstructure 4 receives 4 bytes that debug command receiving elements 2 are sent, and the data 0x8000FCA0 that forms 32 is as the address of memory write; Start the TAP state machine then; The order code combination of an above-mentioned address information and an instruction " mov r0, r0 " is write CPU assistant adjustment unit context register, after the TAP state machine converts; CPU carry out this instruction and still the scholar address information be written among the CPU register R0, accomplish the microoperation of upgrading CPU general-purpose register R0;
5) according to above-mentioned identical step, the 32 bit data 0x4433AA55 that send with the debug command receiving element again upgrade CPU general-purpose register R1;
6) in carrying out the unit context register microoperation of renewal CPU assistant adjustment; Microoperation control state machine 4 produces 4 parameters of TAP state machine and starts the TAP state machine; Wherein DR_data is the order code of the instruction " st r0, r1 " of CPU, after the TAP state machine converts; CPU carries out this instruction and the data of storing among the register R1 is write in the register R0 storage address pointed, accomplishes the operation of memory write;
7) execution recovers the R1 microoperation of CPU general-purpose register and upgrades CPU general-purpose register R1 microoperation similar, and just the microoperation control state machine is passed to the parameter DR_data of TAP state machine and backed up the result who preserves in the CPU general-purpose register R1 microoperation in the 3rd step;
8) recovery CPU general-purpose register R0 microoperation is similar with recovery CPU general-purpose register R0 microoperation;
9) in carrying out the unit context register microoperation of recovery CPU assistant adjustment; Microoperation control state machine 4 starts the TAP state machine; The on-the-spot false register manipulation conversion in CPU assistant adjustment unit is write in request; Wherein, the result of the parameter DR_data of TAP state machine in the unit context register microoperation of first step backup CPU assistant adjustment, preserving.
Receive last microoperation when accomplishing signal at command analysis and performance element 3; Represent that current debug command accomplishes; And debug command this moment receiving element 2 continues to read a last byte 0x16; Debug command receiving element 2 thinks that with this byte debug command finishes sign, and debug command receiving element 2 comes back to idle condition and prepares to receive new order afterwards.
Claims (8)
1. in-circuit emulation apparatus of supporting multiple physical layer interface, it is characterized in that: said in-circuit emulation apparatus comprises:
The debug command receiving element; In order to receiving order data, and the form of order is carried out the correctness inspection, for the order of correct format from the PC debugging software; The debug command receiving element can send operation requests to command analysis and performance element, does not deal with for the order of format error;
Command analysis and performance element; In order to resolving from the operation requests of debug command receiving element; And microoperation is resolved in operation according to the command type that parsing obtains, send the interface conversion request with the form of microoperation to said jtag interface driver element;
The jtag interface driver element in order to receive the microoperation conversion request of command interpretation and performance element, sends the jtag interface drive signal to target CPU, or from target CPU reading of data; The JTAG driver element sends jtag interface driving completion signal to said command analysis and performance element after each microoperation drives completion;
The data encapsulation unit in order to reading under the debug command, receives data that the jtag interface driver element returns and data is sent back to the PC debugging software according to setting form encapsulation back by byte.
2. the in-circuit emulation apparatus of the multiple physical layer interface of support as claimed in claim 1; It is characterized in that: in said command analysis and the performance element, the order of resolve carrying out comprises: assistant adjustment location register read write command and the memory read write order that links to each other with target CPU among target CPU general-purpose register read write command, target CPU control register read write command, the target CPU.
3. according to claim 1 or claim 2 the in-circuit emulation apparatus of the multiple physical layer interface of support; It is characterized in that: in said command analysis and the performance element, microoperation comprises: backup CPU general-purpose register, recover the CPU general-purpose register; Upgrade the CPU general-purpose register; Read the CPU general-purpose register, backup CPU assistant adjustment unit context register recovers CPU assistant adjustment unit context register and upgrades CPU assistant adjustment unit context register.
4. according to claim 1 or claim 2 the in-circuit emulation apparatus of the multiple physical layer interface of support; It is characterized in that: said command analysis and performance element resolve to a plurality of microoperations with the debug command of PC, and control jtag interface driver element is accomplished each microoperation step according to the order of sequence.
5. according to claim 1 or claim 2 the in-circuit emulation apparatus of the multiple physical layer interface of support, it is characterized in that: said command analysis resolves to identical microoperation combination with performance element to identical debug command, and irrelevant with the physical layer interface of linking objective CPU.
6. the in-circuit emulation apparatus of the multiple physical layer interface of support as claimed in claim 1; It is characterized in that: said jtag interface driver element comprises microoperation control state machine and a public TAP state machine, the corresponding a kind of physical layer interface with the TAP controller of each microoperation control state machine.
7. the in-circuit emulation apparatus of the multiple physical layer interface of support as claimed in claim 6; It is characterized in that: in the said jtag interface driver element; The microoperation control state machine is at first resolved microoperation and corresponding parameters thereof; Some parameters that then parsing obtained are input to the TAP state machine, and the microoperation control state machine starts the TAP state machine, and wait for TAP state machine end of run.
8. the in-circuit emulation apparatus of the multiple physical layer interface of support as claimed in claim 6; It is characterized in that: in the said jtag interface driver element; Select to use one of them microoperation control state machine through the register in the setting device, realize support thus multiple physical layer interface.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105467960A (en) * | 2015-12-22 | 2016-04-06 | 湖南三一路面机械有限公司 | Control system and method making host computer compatible with multiple controllers and stirring stations |
| CN105824750A (en) * | 2016-05-31 | 2016-08-03 | 杭州中天微系统有限公司 | Soft breakpoint simulation method during NorFlash program space debugging |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7284172B2 (en) * | 2004-04-30 | 2007-10-16 | International Business Machines Corporation | Access method for embedded JTAG TAP controller instruction registers |
| US20080028263A1 (en) * | 2006-07-25 | 2008-01-31 | Noemi Fernandez | Apparatus and method for protection of JTAG scan chains in a microprocessor |
| CN100468335C (en) * | 2007-03-13 | 2009-03-11 | 杭州华三通信技术有限公司 | Method and device for on-line programming logic device |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
-
2011
- 2011-11-04 CN CN2011103452280A patent/CN102508777A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7284172B2 (en) * | 2004-04-30 | 2007-10-16 | International Business Machines Corporation | Access method for embedded JTAG TAP controller instruction registers |
| US20080028263A1 (en) * | 2006-07-25 | 2008-01-31 | Noemi Fernandez | Apparatus and method for protection of JTAG scan chains in a microprocessor |
| CN100468335C (en) * | 2007-03-13 | 2009-03-11 | 杭州华三通信技术有限公司 | Method and device for on-line programming logic device |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105467960A (en) * | 2015-12-22 | 2016-04-06 | 湖南三一路面机械有限公司 | Control system and method making host computer compatible with multiple controllers and stirring stations |
| CN105824750A (en) * | 2016-05-31 | 2016-08-03 | 杭州中天微系统有限公司 | Soft breakpoint simulation method during NorFlash program space debugging |
| CN105824750B (en) * | 2016-05-31 | 2018-05-22 | 杭州中天微系统有限公司 | A kind of soft breakpoint analogy method in the debugging of the NorFlash program spaces |
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Application publication date: 20120620 |