CN115454881B - Debugging system and debugging method of RISC-V architecture - Google Patents
Debugging system and debugging method of RISC-V architecture Download PDFInfo
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Abstract
The invention has provided a RISC-V architectonical debug system and debug method, relate to the technical field of the system chip, the RISC-V architectonical debug system and debug method that the invention provides, include debug host computer, hardware debugger and RISC-V chip set connected sequentially in the debug system, debug host computer and hardware debugger through USB way communication connection, hardware debugger and RISC-V chip set through the communication connection of the serial line debug protocol, and, RISC-V chip set includes at least one RISC-V chip; in the debugging process, a multi-chip, multi-core or multi-thread debugging mode in a RISC-V chip set can be supported to improve the timeliness, and because a serial line debugging protocol is applied, the hardware resource of a debugging interface can be saved, and simultaneously because the parity check of the serial line debugging protocol can improve the reliability of data transmission of the chip debugging function.
Description
Technical Field
The invention relates to the technical field of system chips, in particular to a debugging system and a debugging method of a RISC-V architecture.
Background
RISC-V is an open source instruction set architecture based on the principle of a reduced instruction set, V is expressed as a fifth generation RISC (reduced instruction set computer), various processors can be designed based on the RISC-V instruction set architecture, the RISC-V developed in recent years is a simple, open source and free instruction set architecture, has the technical advantages of simplicity, low power consumption, modularization, expandability and the like, and is very suitable for the fields of Internet of things and edge computing.
The chip enterprise uses RISC-V structure to reduce the cost of chip development, and get rid of the monopoly phenomenon, realize the homemade independence of the processor kernel. However, as the RISC-V has a short birth time, related compilers, software development environments, module debugging schemes, etc. are still developing, when a chip design enterprise debugs a processor of the RISC-V architecture, a debugging tool that can be used has a certain gap compared with the ARM architecture, and the current commonly used debugging mode is based on a single chip or a single-core chip, lacks support for multiple chips or multiple cores, occupies more hardware resources, lacks reliability, has weak anti-interference capability, and is difficult to meet the reliability requirement under the RISC-V architecture.
Disclosure of Invention
Accordingly, the present invention is directed to a debugging system and a debugging method for a RISC-V architecture, so as to alleviate the above technical problems.
In a first aspect, an embodiment of the present invention provides a debugging system of a RISC-V architecture, where the debugging system includes: the debugging host, the hardware debugger and the RISC-V chipset are connected in sequence; the debugging host is in communication connection with the hardware debugger in a USB mode, the hardware debugger is in communication connection with the RISC-V chipset through a serial line debugging protocol, and the RISC-V chipset comprises at least one RISC-V chip; the debugging host is used for inputting a debugging instruction, converting the debugging instruction into a first USB signal and transmitting the first USB signal to the hardware debugger; the hardware debugger is used for converting the first USB signal into a first serial line debugging signal, transmitting the first serial line debugging signal to the RISC-V chip set, receiving a second serial line debugging signal from the RISC-V chip set, converting the second serial line debugging signal into a second USB signal, and transmitting the second USB signal to the debugging host computer so as to debug at least one RISC-V chip of the RISC-V chip set.
With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, where the hardware debugger is a protocol converter, and includes a universal serial bus interface, a protocol conversion module, and a serial line debug interface, which are sequentially connected; the debugging host is connected to the universal serial bus interface in a USB mode, and the hardware debugger is in communication connection with the RISC-V chip set through a serial line debugging protocol through the serial line debugging interface; the protocol conversion module is used for converting the first USB signal input by the debugging host into a first serial line debugging signal and converting a second serial line debugging signal sent by the RISC-V chip set into a second USB signal.
With reference to the first aspect, a second possible implementation manner of the first aspect is provided in an embodiment of the present invention, where the hardware debugger and at least one RISC-V chip included in the RISC-V chipset are connected in a one-to-one network or a one-to-many star network.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, where the RISC-V chip is a chip using RISC-V as an architecture, and the RISC-V chip includes a debug interface module, a debug execution module, and a RISC-V core, which are sequentially connected; wherein said RISC-V chip includes at least one said RISC-V core; the RISC-V core includes at least one hardware thread.
With reference to the third possible implementation manner of the first aspect, an embodiment of the present invention provides a fourth possible implementation manner of the first aspect, where communication is performed between the debug interface module and the debug execution module, and between the debug execution module and the RISC-V core through a bus protocol; the bus protocol comprises one of the following protocols: tileLink protocol, AMBA protocol, and Wishbone protocol.
With reference to the third possible implementation manner of the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect, where the debug interface module includes a protocol processing unit, a protocol configuration unit, a protocol response unit, and a protocol conversion unit, where the protocol configuration unit is configured to configure a register preset in the debug interface module, and the register includes a configuration register and a status register; the protocol processing unit, the protocol configuration unit and the protocol response unit are connected in sequence, and the protocol processing unit is also connected with the protocol conversion unit.
With reference to the third possible implementation manner of the first aspect, an embodiment of the present invention provides a sixth possible implementation manner of the first aspect, where the debug execution module includes an instruction unit, a core and thread control unit, a data buffer unit, and a reset unit; the instruction unit is connected with the core and thread control unit, the data buffer unit and the reset unit, the core and thread control unit and the data buffer unit are also connected with the reset unit, and the connection of the instruction unit with the core and thread control unit and the data buffer unit also comprises bidirectional connection.
With reference to the first aspect, an embodiment of the present invention provides a seventh possible implementation manner of the first aspect, where the debug host includes a debugger and a debug converter that are sequentially connected, and the debug host is a computer based on a Linux or Windows operating system; the debugger is a program debugger and is used for inputting the debugging instruction; the debugging converter is configured with preset chip debugging software and used for establishing communication between the debugging host and the hardware debugger.
With reference to the seventh possible implementation manner of the first aspect, an embodiment of the present invention provides an eighth possible implementation manner of the first aspect, where the debugger is configured with a client, and the debug converter is configured with a server; and the client and the server carry out remote communication through a preset communication protocol.
In a second aspect, an embodiment of the present invention further provides a debugging method for a RISC-V architecture, where the debugging method is a serial line debugging protocol-based debugging method, and the debugging method is applied to the debugging system of the RISC-V architecture in the first aspect; the method comprises the following steps: inputting a debugging instruction through a debugging host, converting the debugging instruction into a first USB signal, and transmitting the first USB signal to a hardware debugger; converting the first USB signal into a first serial line debugging signal through the hardware debugger, and transmitting the first serial line debugging signal to a RISC-V chip set; and receiving a second serial line debugging signal from the RISC-V chipset through the hardware debugger, converting the second serial line debugging signal into a second USB signal, and transmitting the second USB signal to the debugging host to debug at least one RISC-V chip of the RISC-V chipset.
The embodiment of the invention has the following beneficial effects:
the debugging system comprises a debugging host, a hardware debugger and a RISC-V chip set which are sequentially connected, wherein the debugging host is in communication connection with the hardware debugger through a USB mode, the hardware debugger is in communication connection with the RISC-V chip set through a serial line debugging protocol, and the RISC-V chip set comprises at least one RISC-V chip; in the debugging process, the debugging host is used for inputting a debugging instruction, converting the debugging instruction into a first USB signal and transmitting the first USB signal to the hardware debugger; the hardware debugger is used for converting a first USB signal into a first serial line debugging signal, transmitting the first serial line debugging signal to the RISC-V chipset, receiving a second serial line debugging signal from the RISC-V chipset, converting the second serial line debugging signal into a second USB signal, and transmitting the second USB signal to the debugging host to debug at least one RISC-V chip of the RISC-V chipset.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a system block diagram of a debugging system of RISC-V architecture according to an embodiment of the present invention;
FIG. 2 is a system block diagram of another RISC-V architecture debugging system provided by an embodiment of the present invention;
fig. 3 is a timing diagram of signal transmission of a serial line debug protocol according to an embodiment of the present invention;
fig. 4 is a timing diagram of signal transmission of another serial line debug protocol according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating signal transmission according to another serial line debug protocol provided by an embodiment of the present invention;
fig. 6 is a timing diagram illustrating signal transmission of another serial line debug protocol according to an embodiment of the present invention;
FIG. 7 is a timing diagram illustrating signal transmission according to another serial line debug protocol provided by an embodiment of the present invention;
FIG. 8 is a schematic diagram of a RISC-V chip according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a debug interface module according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram of a debug execution module according to an embodiment of the present invention;
FIG. 11 is a flowchart illustrating a debugging method of a RISC-V architecture according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, the debugging or simulation process of the RISC-V chip based on the RISC-V architecture is mostly realized based on a JTAG (Joint Test Action Group) debugging interface, for example, a 4-wire JTAG debugging interface is adopted, and this way will result in more occupied hardware resources, and is not suitable for being applied to an environment where hardware resources (wiring area or pin number) are short.
Moreover, when the JTAG debugging interface and the cJTAG protocol are adopted to transmit data, data interaction is usually one data packet each time, data verification is not performed in the data transmission process, reliability is lacked, the anti-interference capability is weak, and the reliability requirement under a RISC-V framework is difficult to meet.
Based on this, the debugging system and the debugging method of the RISC-V architecture provided by the embodiment of the invention can not only support the debugging mode of multiple chips, multiple cores or multiple threads, but also improve the timeliness and the reliability.
For the convenience of understanding the embodiment, the debugging system of RISC-V architecture disclosed in the embodiment of the present invention will be described in detail first.
In one possible implementation, an embodiment of the present invention provides a debugging system with a RISC-V architecture, which is hereinafter referred to as a debugging system. The debugging system can be applied to the debugging scene of a reconfigurable RISC-V architecture platform.
Specifically, a system block diagram of a debugging system of a RISC-V architecture as shown in fig. 1 includes: a debugging host 10, a hardware debugger 20, and a RISC-V chipset 30 connected in sequence.
The debugging host 10 and the hardware debugger 20 are communicatively connected by a USB (Universal Serial Bus), the hardware debugger 20 and the RISC-V chipset 30 are communicatively connected by a Serial line debugging protocol, and, as shown in fig. 1, the RISC-V chipset 30 includes at least one RISC-V chip 301. In fig. 1, three RISC-V chips are taken as an example for illustration, in other embodiments, the number of RISC-V chips may be set according to actual situations, and the embodiment of the present invention is not limited thereto.
Specifically, the debug host 10 is configured to input a debug instruction, convert the debug instruction into a first USB signal, and transmit the first USB signal to the hardware debugger 20;
the hardware debugger 20 is configured to convert the first USB signal into a first serial line debugging signal, transmit the first serial line debugging signal to the RISC-V chipset 30, receive a second serial line debugging signal from the RISC-V chipset 30, convert the second serial line debugging signal into a second USB signal, and transmit the second USB signal to the debugging host 10, so as to debug at least one RISC-V chip 301 of the RISC-V chipset 30.
The debugging system of the RISC-V framework provided by the embodiment of the invention comprises a debugging host, a hardware debugger and a RISC-V chipset which are sequentially connected, wherein the debugging host is in communication connection with the hardware debugger through a USB mode, the hardware debugger is in communication connection with the RISC-V chipset through a serial line debugging protocol, and the RISC-V chipset comprises at least one RISC-V chip; in the debugging process, the debugging host is used for inputting a debugging instruction, converting the debugging instruction into a first USB signal and transmitting the first USB signal to the hardware debugger; the hardware debugger is used for converting a first USB signal into a first serial line debugging signal, transmitting the first serial line debugging signal to the RISC-V chipset, receiving a second serial line debugging signal from the RISC-V chipset, converting the second serial line debugging signal into a second USB signal, and transmitting the second USB signal to the debugging host to debug at least one RISC-V chip of the RISC-V chipset.
In specific implementation, the debugging host comprises a debugger and a debugging converter which are sequentially connected, and the debugging host is a computer based on a Linux or Windows operating system; for ease of understanding, fig. 2 shows a system block diagram of another debugging system of RISC-V architecture on the basis of fig. 1, and further shows a debugger 101 and a debug converter 102 included in the debugging host 10 in addition to the structure shown in fig. 1.
Specifically, the debugger 101 and the debug converter 102 are a debugger and a debug converter at a software level running on a debug host, and in the embodiment of the present invention, the debug host is exemplified as a computer based on a Linux operating system, and the debugger is a program debugger, which is used to input a debug instruction, and for example, the debugger may be implemented by open source software GDB (GNU symbololic debug). The debug switch is usually configured with a predetermined chip debug software for establishing communication between the debug host and the hardware debugger. Specifically, the debug converter is usually Chip debug software including a hardware driver to implement a communication function between the debug host and the hardware Debugger, and may be implemented by Open source software OpenOCD (Open On-Chip debug).
In actual use, the debugger is generally configured with a client, and the debug converter is configured with a server; the client and the server carry out remote communication through a preset communication protocol. For example, the debugger and the debug converter communicate through a remote connection, the communication mode may be a socket of a TCP/IP (Transmission Control Protocol/Internet Protocol ) Protocol, and at this time, the client of the debugger is connected to the server of the debug converter through the remote communication mode to implement remote communication.
Further, the hardware debugger in the embodiment of the present invention is generally a protocol converter, and specifically, as shown in fig. 2, the hardware debugger includes a universal serial bus interface 201, a protocol conversion module 202, and a serial line debugging interface 203, which are connected in sequence; the universal serial bus interface is also called as a USB interface, the debugging host is connected to the universal serial bus interface in a USB mode, and the hardware debugger is in communication connection with the RISC-V chip set through a serial line debugging protocol through the serial line debugging interface; the protocol conversion module is used for converting a first USB signal input by the debugging host into a first serial line debugging signal and converting a second serial line debugging signal sent by the RISC-V chip set into a second USB signal.
Specifically, based on the protocol conversion module, the hardware debugger generally has two working modes, (1) receiving a first USB signal from a debugging host through a universal serial bus interface (USB interface), converting the first USB signal into a first serial line debugging signal through the protocol conversion module, and transmitting the first serial line debugging signal through a serial line debugging interface; (2) the second serial line debugging signal from the RISC-V chip set is received through the serial line debugging interface, converted into a second USB signal through the protocol conversion module and transmitted through a universal serial bus interface (USB interface).
Further, the serial line debugging protocol between the hardware debugger and the RISC-V chipset is generally referred to as a bidirectional serial line debugging protocol (RISC-V bi-directional serial line debugging protocol) based on the RISC-V architecture, which is abbreviated as a serial line debugging protocol (RBSWD protocol), and the serial line debugging protocol is specifically two signals RBSWDC (RBSWD Clock) and RBSWDD (RBSWD Data), and respectively transmits a Clock signal and a Data signal, specifically, the timing diagram of signal transmission of the serial line debugging protocol shown in fig. 3 includes transmission diagrams of the RBSWDC signal and the RBSWDD signal, respectively.
Based on the serial line debug protocol, data signals between the hardware debugger and the RISC-V chipset are bidirectional signals, data transmission usually adopts a mode of 1-3 data packets, data verification of each data packet adopts parity check, data transmission includes instruction operations such as write, read, response cancellation, and the like, and data transmission sequence is usually that the data transmission sequence is sent first with low bits, the data transmission content is a start bit, an operation bit, a response bit, ID1, ID2, ID3, a check bit, an address and data, where ID1, ID2 and ID3 represent a chip ID (i.e. RISC-V chip ID), a core ID and a thread ID, respectively.
The write operation refers to configuring a protocol register or a debug register, and writing configuration data according to an address value of the protocol register or the debug register, as shown in fig. 3, i.e., a signal timing diagram of the write operation, and further, after the write operation is successfully performed, a write response is returned, as shown in another signal transmission timing diagram of fig. 4, which corresponds to a signal timing diagram of the write response after the write operation; as can be seen from the timing diagrams of signal transmission shown in fig. 5 and 6, after the read operation is successfully performed, a read response is returned; the response cancellation operation refers to sending a response cancellation in the process of waiting for a read-back response or a write success response after a read operation or a write operation, and ending the response waiting process, as shown in fig. 7.
The protocol register or the debugging register usually exists in the RISC-V chip, and further, the protocol register also includes a configuration register and a status register:
the types of configuration registers are: an ID bit width configuration register is used for configuring data bit widths of ID1, ID2 and ID3, and respectively represents the number of chips, cores and hardware threads which can be debugged by a serial debugging protocol; b. the data verification configuration register is used for configuring the data verification type or the on/off of the verification function of each data packet, wherein the data verification type of the corresponding data packet can be configured to be odd verification or even verification according to the protocol bit width register or the address data bit width configuration register; c. the address data bit width configuration register is used for configuring the address bit width and the data bit width of the protocol; an ID synchronous configuration register for synchronizing the ID register of the debugging interface module in the RISC-V chip and the ID register of the debugging execution module in the RISC-V chip; e. the reset register can realize reset operation of the reset state register, the recovery of the default serial line debugging protocol format, the reset of the whole debugging interface module and the like.
The types of status registers are: a. the protocol bit width state register represents the total data bit width of the serial line debugging protocol; b. a data check status register indicating the number of times of data check abnormality; and the ID state register represents the chip ID, the core ID and the thread ID of the RISC-V chip.
Further, based on the debugging system of the RISC-V architecture shown in fig. 1 and 2, the hardware debugger is connected to at least one RISC-V chip included in the RISC-V chipset in a one-to-one network manner, or a one-to-many star network manner. Specifically, the hardware debugger and the RISC-V chipset communicate through a serial line debugging protocol, and are connected in a one-to-one or one-to-many star network manner according to the number of RISC-V chips (one RISC-V chip or a plurality of RISC-V chips) in the RISC-V chipset.
In addition, the RISC-V chip in the RISC-V chip set is a chip using RISC-V as the architecture, and the RISC-V chip usually has a debugging function. Specifically, the RISC-V chip comprises a debugging interface module, a debugging execution module and a RISC-V core which are connected in sequence; FIG. 8 shows a structure diagram of a RISC-V chip, which includes a debug interface module 801, a debug execution module 802, a RISC-V core 803 and a hardware thread 804, wherein the RISC-V chip includes at least one RISC-V core; one RISC-V core contains at least one hardware thread.
Further, the communication is carried out between the debugging interface module and the debugging execution module, and between the debugging execution module and the RISC-V core through a bus protocol; and, the bus protocol includes one of the following protocols: tileLink protocol, AMBA protocol, and Wishbone protocol.
In actual use, the debug interface module is connected to the hardware debugger and the debug execution module, and the debug interface module includes a protocol processing unit, a protocol configuration unit, a protocol response unit, and a protocol conversion unit, where the protocol configuration unit is used to configure a register preset in the debug interface module, and the register includes the configuration register and the status register.
For ease of understanding, fig. 9 shows a schematic structural diagram of a debug interface module, as shown in fig. 9, including: the device comprises a protocol processing unit 901, a protocol configuration unit 902, a protocol response unit 903 and a protocol conversion unit 904, wherein the protocol processing unit 901, the protocol configuration unit 902 and the protocol response unit 903 are connected in sequence, and the protocol processing unit 901 is further connected with the protocol conversion unit 904.
In specific implementation, the protocol processing unit mainly includes the following functions: a. receiving serial line debugging information; b. chip ID information of the self-synchronizing RISC-V chip filters debugging instructions according to an ID state register; c. transmitting the filtered debugging instruction to a protocol configuration unit or a protocol conversion unit according to the register type in the debugging instruction; d. and counting the abnormal times of data verification according to the data verification result, and writing the abnormal times into a data verification status register.
Further, the role of the protocol configuration unit mainly includes: a. configuring a corresponding configuration register according to the write operation; b. and transmitting the value of the configuration register or the status register back to the register of the protocol response unit.
The protocol response unit mainly has the following functions: a. receiving read-back information of a bus protocol; b. the read-back information (from a debugging execution module) of the bus protocol or the value transmitted by the protocol configuration unit is encapsulated into the response information of the serial line debugging protocol; c. and sending response information of the serial line debugging protocol.
The role of the protocol conversion unit is mainly as follows: a. receiving read-back information of a bus protocol; b. receiving instruction information of a protocol processing unit; c. the mutual conversion of a bus protocol and a serial line debugging protocol is realized; d. and outputting the debugging instruction in the bus protocol format.
Further, the debugging instruction output by the protocol conversion unit is usually output to the debugging execution module, and at this time, after the debugging execution module receives the debugging instruction, the debugging execution module converts the debugging instruction into a specific debugging operation, including: a. providing information such as chip ID (RISC-V chip ID), core ID, thread ID, etc.; b. stopping or recovering the corresponding core or hardware thread according to the core ID and thread ID information of the instruction; c. and performing read-write debugging operation on a General Purpose Register (GPR), a Control and Status Register (CSR) or a memory.
Specifically, in order to implement the function of the debug execution module, the debug execution module in the embodiment of the present invention includes an instruction unit, a core and thread control unit, a data buffer unit, and a reset unit; for ease of understanding, fig. 10 shows a schematic structural diagram of a debug execution module, including: the core-thread control unit comprises an instruction unit 1001, a core-thread control unit 1002, a data buffer unit 1003 and a reset unit 1004, wherein the instruction unit 1001 is connected with the core-thread control unit 1002, the data buffer unit 1003 and the reset unit 1004, the core-thread control unit and the data buffer unit are also connected with the reset unit, and as shown in fig. 10, the connection of the instruction unit with the core-thread control unit and the data buffer unit also comprises bidirectional connection.
The main functions of the instruction unit are as follows: a. receiving a debugging instruction of a debugging interface module; b. transmitting the core ID and the thread ID information of the debugging instruction to a core and thread control unit; c. transmitting the specific debugging operation to the RISC-V core; d. synchronizing information such as chip ID, core ID, thread ID and the like of the current RISC-V core; e. and transmitting the response information or the read-back data of the debugging operation to the debugging interface module.
Further, the main functions of the core and thread control unit include: a. switching the core and the thread controlled by the debugging execution module according to the core ID and the thread ID information; b. controlling the thread to enter a debugging mode or a machine mode; c. and returning the working mode of the thread to the instruction unit.
Further, the data buffer unit mainly has the following functions: a. caching a debugging instruction before the core and thread control unit finishes the switching of the core and the thread; b. receiving read-back information of the RISC-V core; c. and transmitting the cache instruction or read-back information of the RISC-V core to the instruction unit.
Further, the reset unit mainly has the following functions: and resetting the working state of each module or clearing the data buffer unit.
Furthermore, the RISC-V core of the RISC-V chip in the embodiment of the present invention is a processor designed by RISC-V architecture, the processor includes a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an MCU (micro controller Unit), a DPU (Data Processing Unit), and the like, and the RISC-V core includes resources such as a hardware thread, a general purpose register, a control and status register, and a memory. The hardware thread at least comprises two working modes, namely a machine mode and a debugging mode, wherein the machine mode refers to a mode in which the thread works normally, and the debugging mode refers to a mode in which the thread can execute debugging operation.
Based on the debugging system, the debugging function can be realized on the RISC-V chip through a serial line debugging protocol, a new debugging interface is added to the debugging interface in the RISC-V architecture, and the further development and application of the RISC-V architecture are facilitated.
Moreover, the serial line debugging protocol realizes a double-pin serial line debugging interface, so that the total pin number required by chip packaging is effectively reduced, and the chip stacking technology is also favorable for producing chips, because the more the number of connectors among stacked chips is reduced, the more the process difficulty can be reduced.
Furthermore, the serial line debugging protocol supports a star-shaped topological structure and is suitable for the debugging function of the RISC-V architecture in multiple chips and multiple cores. Moreover, a protocol register of a serial line debugging protocol can be configured according to RISC-V instruction set modes (different instruction encoding lengths), the address bit width and the data bit width of the debugging protocol are adjusted, and the method is suitable for a debugging scene of a reconfigurable RISC-V architecture platform, wherein the reconfigurable RISC-V architecture platform is commonly an FPGA (Field Programmable Gate Array), and prototype verification or hardware practice of a plurality of RISC-V projects is usually realized on the FPGA at present.
To sum up, the debugging system of the RISC-V architecture provided by the embodiment of the present invention can be applied to a debugging scenario of a reconfigurable RISC-V architecture platform, and supports a multi-chip, multi-core, or multi-thread debugging mode, which can improve timeliness, further, since a serial line debugging protocol is applied to the RISC-V chip, hardware resources of a debugging interface can be saved, and meanwhile, because parity check of the serial line debugging protocol can improve transmission reliability of debugging instructions and debugging read-back data.
Further, on the basis of the above embodiment, the embodiment of the present invention further provides a debugging method of a RISC-V architecture, the debugging method being a debugging method based on a serial line debugging protocol, and the debugging method being applied to the debugging system of the RISC-V architecture; the serial line debugging protocol is a protocol suitable for the debugging function of the RISC-V architecture, and is innovative, different from the existing communication protocols such as Jtag, and specifically, as shown in fig. 11, the flow chart of the debugging method of the RISC-V architecture includes:
step S102, inputting a debugging instruction through a debugging host, converting the debugging instruction into a first USB signal, and transmitting the first USB signal to a hardware debugger;
step S104, converting the first USB signal into a first serial line debugging signal through the hardware debugger, and transmitting the first serial line debugging signal to a RISC-V chip set;
step S106, receiving a second serial line debugging signal from the RISC-V chipset by the hardware debugger, converting the second serial line debugging signal into a second USB signal, and transmitting the second USB signal to the debugging host to debug at least one RISC-V chip of the RISC-V chipset.
The debugging method of the RISC-V architecture provided by the embodiment of the invention has the same technical characteristics as the debugging system of the RISC-V architecture provided by the embodiment, thereby solving the same technical problems and achieving the same technical effect.
The computer program product of the debugging system and the debugging method of the RISC-V architecture provided in the embodiments of the present invention includes a computer readable storage medium storing a program code, and instructions included in the program code may be used to execute the method described in the foregoing method embodiments.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the method described above may refer to the corresponding process in the foregoing embodiment, and is not described herein again.
In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases for those skilled in the art.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part thereof which substantially contributes to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A RISC-V architecture debugging system, said debugging system comprising: the debugging host, the hardware debugger and the RISC-V chipset are connected in sequence;
the debugging host is in communication connection with the hardware debugger in a USB mode, the hardware debugger is in communication connection with the RISC-V chipset through a serial line debugging protocol, and the RISC-V chipset comprises at least one RISC-V chip; the hardware debugger is connected with at least one RISC-V chip contained in the RISC-V chip set in a one-to-one network mode or a one-to-many star network mode; data signals between the hardware debugger and the RISC-V chipset are bidirectional signals, data transmission usually adopts a mode of 1-3 data packets, and data check of each data packet adopts parity check;
the serial line debugging protocol is a bidirectional serial line debugging protocol based on a RISC-V architecture, and specifically comprises two paths of signals which respectively transmit a clock signal and a data signal; and, the data format of the serial line debug protocol includes: the system comprises a start bit, an operation bit, a response bit, ID1, ID2, ID3, a check bit, an address and data, wherein ID1, ID2 and ID3 respectively represent a chip ID, a core ID and a thread ID;
the debugging host is used for inputting a debugging instruction, converting the debugging instruction into a first USB signal and transmitting the first USB signal to the hardware debugger;
the hardware debugger is used for converting the first USB signal into a first serial line debugging signal, transmitting the first serial line debugging signal to the RISC-V chipset, receiving a second serial line debugging signal from the RISC-V chipset, converting the second serial line debugging signal into a second USB signal, and transmitting the second USB signal to the debugging host computer so as to debug at least one RISC-V chip of the RISC-V chipset;
the RISC-V chip is a chip with an architecture of RISC-V, and comprises a debugging interface module, a debugging execution module and a RISC-V core which are connected in sequence; wherein said RISC-V chip includes at least one said RISC-V core; the RISC-V core includes at least one hardware thread;
the debugging interface module comprises a protocol processing unit, a protocol configuration unit, a protocol response unit and a protocol conversion unit, wherein the protocol configuration unit is used for configuring a preset register in the debugging interface module, and the register comprises a configuration register and a state register;
the protocol processing unit, the protocol configuration unit and the protocol response unit are connected in sequence, and the protocol processing unit is also connected with the protocol conversion unit.
2. The RISC-V architecture debug system of claim 1, wherein said hardware debugger is a protocol converter comprising a universal serial bus interface, a protocol conversion module and a serial line debug interface connected in sequence;
the debugging host is connected to the universal serial bus interface in a USB mode, and the hardware debugger is in communication connection with the RISC-V chip set through a serial line debugging protocol through the serial line debugging interface;
the protocol conversion module is used for converting the first USB signal input by the debugging host into a first serial line debugging signal and converting the second serial line debugging signal sent by the RISC-V chip set into a second USB signal.
3. The RISC-V architecture debug system of claim 1, wherein communication between said debug interface module and said debug execution module, and between said debug execution module and said RISC-V core, is via a bus protocol;
the bus protocol comprises one of the following protocols: tileLink protocol, AMBA protocol, and Wishbone protocol.
4. The RISC-V architecture debugging system of claim 1, wherein the debug execution module comprises an instruction unit, a core and thread control unit, a data buffering unit, and a reset unit;
the instruction unit is connected with the core and thread control unit, the data buffer unit and the reset unit, and the core and thread control unit and the data buffer unit are also connected with the reset unit;
the connection between the instruction unit and the core, the connection between the thread control unit and the data buffer unit also comprise bidirectional connection.
5. The RISC-V architecture debug system of claim 1, wherein said debug host comprises a debugger and a debug converter connected in sequence, and wherein said debug host is a Linux or Windows operating system based computer;
the debugger is a program debugger and is used for inputting the debugging instruction;
the debugging converter is configured with preset chip debugging software and used for establishing communication between the debugging host and the hardware debugger.
6. The RISC-V architecture debugging system of claim 5, wherein the debugger is configured with a client, the debugging converter is configured with a server;
and the client and the server carry out remote communication through a preset communication protocol.
7. A debugging method of RISC-V architecture, characterized by that, the said debugging method is a debugging method based on debug protocol of the serial line, and, the said debugging method is applied to the debugging system of RISC-V architecture of any claim 1~6;
the method comprises the following steps:
inputting a debugging instruction through a debugging host, converting the debugging instruction into a first USB signal, and transmitting the first USB signal to a hardware debugger;
converting the first USB signal into a first serial line debugging signal through the hardware debugger, and transmitting the first serial line debugging signal to a RISC-V chip set;
and receiving a second serial line debugging signal from the RISC-V chipset through the hardware debugger, converting the second serial line debugging signal into a second USB signal, and transmitting the second USB signal to the debugging host to debug at least one RISC-V chip of the RISC-V chipset.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101251819A (en) * | 2007-12-11 | 2008-08-27 | 浙江大学 | A Debugging Method Applicable to Multi-processor Core System-on-Chip |
| CN101963934A (en) * | 2010-10-27 | 2011-02-02 | 山东大学 | Method for debugging 8051 core-based system on chip (SOC) on line |
| CN102411535A (en) * | 2011-08-02 | 2012-04-11 | 上海交通大学 | Navigating-SoC (System On Chip) simulating, verifying and debugging platform |
| CN105446933A (en) * | 2014-09-26 | 2016-03-30 | 扬智科技股份有限公司 | debugging system and debugging method of multi-core processor |
| CN110851388A (en) * | 2019-11-08 | 2020-02-28 | 南京沁恒微电子股份有限公司 | Debugging system and debugging signal transmission method for RISC-V processor |
| CN216210991U (en) * | 2021-10-28 | 2022-04-05 | 山东浪潮科学研究院有限公司 | Wireless transmission multi-path RISC-V chip debugger based on WIFI |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190271740A1 (en) * | 2018-03-05 | 2019-09-05 | Changyi Gu | Non-intrusive on-chip debugger with remote protocol support |
-
2022
- 2022-11-10 CN CN202211401840.XA patent/CN115454881B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101251819A (en) * | 2007-12-11 | 2008-08-27 | 浙江大学 | A Debugging Method Applicable to Multi-processor Core System-on-Chip |
| CN101963934A (en) * | 2010-10-27 | 2011-02-02 | 山东大学 | Method for debugging 8051 core-based system on chip (SOC) on line |
| CN102411535A (en) * | 2011-08-02 | 2012-04-11 | 上海交通大学 | Navigating-SoC (System On Chip) simulating, verifying and debugging platform |
| CN105446933A (en) * | 2014-09-26 | 2016-03-30 | 扬智科技股份有限公司 | debugging system and debugging method of multi-core processor |
| CN110851388A (en) * | 2019-11-08 | 2020-02-28 | 南京沁恒微电子股份有限公司 | Debugging system and debugging signal transmission method for RISC-V processor |
| CN216210991U (en) * | 2021-10-28 | 2022-04-05 | 山东浪潮科学研究院有限公司 | Wireless transmission multi-path RISC-V chip debugger based on WIFI |
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