CN117172018A - Singlechip on-line debugging system suitable for multiple kernels - Google Patents

Abstract

The invention discloses a singlechip on-line debugging system suitable for multiple cores, belonging to the technical field of singlechip debugging simulation; the single chip microcomputer debugging module sends a debugging instruction; the debugger is connected with the singlechip debugging module, receives and analyzes the debugging instruction, and obtains the analyzed debugging instruction; a kernel processor subunit for performing debugging processing; a debug interface subunit that converts to debug data; the target singlechip is connected with the debugger and used for receiving the debugging data, and comprises a kernel debugging module and a kernel chip, wherein the kernel debugging module is used for carrying out debugging control on the kernel chip according to the debugging data and feeding the debugging information back to the singlechip debugging module through the debugger. The beneficial effects of the technical scheme are as follows: the on-line debugging function of the singlechip supporting various kernels is realized, the operation is simple and convenient, and the resource waste is avoided.

Description

Singlechip on-line debugging system suitable for multiple kernels

Technical Field

The invention relates to the technical field of singlechip debugging simulation, in particular to a singlechip online debugging system suitable for multiple cores.

Background

At present, the trend in the embedded Debugging field is to integrate a functional module specially used for Debugging On an MCU (Microcontroller Unit, micro control unit) and provide a special interface for a user to open, and the user can stop or continue the operation of the central processing unit and access various resources On the target machine through the Debugging control module, which is an OCD (On-Chip Debugging) technology; meanwhile, JTAG (Joint Test Action Group, joint test working group) and SWD (Serial Wire Debug, serial line debug) are used as the most widely applied system-level test technology, and the control logic is simple and convenient to realize and often used as a test interface of an on-chip debugging module.

A complete OCD debug system typically includes three parts, a debug host, a debugger, and a target, where the debug host runs IDE (Integrated Development Environment ) software and is connected to the target through the debugger; the debugger converts the debug command and data sent by the host into debug data based on the OCD module of the target machine and the debug interface; the OCD block of the target machine receives the debug data sent by the debugger, and completes the logic control of the central processor; a typical OCD debugging system is shown in FIG. 1, and mainly comprises an upper computer 12, a debugger 2 and a target singlechip 3.

In the development process of the embedded system, the upper computer completes development, downloading and debugging of target machine software through a debugger, and the singlechip debugging technology is an important component of application development; the product development and updating and the variety of the single chip microcomputer are more and more, the debugging system is important to develop as an indispensable tool for the single chip microcomputer, along with the continuous increase of market demands, the variety of debuggers is also rapidly developed, different factories of the same kernel correspond to different debuggers, and different kernel chips of the same factory correspond to different debuggers.

In the prior art, the single chip microcomputer debugging systems are independent, different cores correspond to different debugging systems and solutions, the same is also corresponding to different debugging devices, different debuggers are needed to be purchased for replacing a processor, and different driving and application software are installed, so that resource waste can be caused, and the operation is inconvenient, and therefore, the single chip microcomputer online debugging system capable of being simultaneously applicable to multiple cores is urgently needed.

Disclosure of Invention

The invention aims to provide a singlechip on-line debugging system suitable for various kernels, which solves the technical problems;

a singlechip on-line debugging system suitable for multiple cores comprises,

the singlechip debugging module sends a debugging instruction;

the debugger is connected with the singlechip debugging module and comprises a second integrated debugging unit which comprises,

a protocol receiving subunit receives and analyzes the debug instruction to obtain an analyzed debug instruction;

the kernel processor subunit performs debugging processing according to the analyzed debugging instruction;

a debug interface subunit, which converts the parsed debug instruction into debug data;

the target single chip microcomputer is connected with the debugger and receives the debugging data, the target single chip microcomputer comprises a kernel debugging module and a kernel chip, the kernel debugging module is used for carrying out debugging control on the kernel chip according to the debugging data, and debugging information is fed back to the single chip microcomputer debugging module through the debugger.

Preferably, the singlechip debugging module comprises a first integrated debugging unit, the first integrated debugging unit comprises,

the command storage subunit is used for storing the debugging instructions, wherein the debugging instructions comprise single-step operation, full-speed operation, resetting of a singlechip interface, setting of a breakpoint and stopping of operation;

and the protocol transmitting subunit is used for carrying out USB protocol transmission.

Preferably, the debug instruction further includes a set and fetch register, a set and read register value, a set and fetch upper computer pointer, writing or reading data to a memory address, writing or reading a bank.

Preferably, the instruction set of the singlechip debugging module comprises an 8051 kernel instruction set, an ARM kernel instruction set and a RISC-V kernel instruction set.

Preferably, the singlechip debugging module is connected with the debugger through WinUSB protocol, and the hardware interface is USB2.0.

Preferably, the debug interface between the debugger and the target singlechip comprises a JATG interface, a SWD interface, a power supply voltage interface, a grounding interface and a reset interface.

Preferably, the debugger is further provided with a clock line interface, an SWD data line interface, a data transmission interface, a data receiving interface, a JATG test data output port and a JATG test mode selection port.

Preferably, the debug interface subunit comprises,

a JATG data sequence conversion module for generating a JATG data stream;

and the SWD data sequence conversion module is used for generating the SWD data stream.

Preferably, the core processor subunit comprises,

the IAP processing set module is used for Flash programming;

OCD debugging module for on-chip debugging;

and the GDB debugging module is used for tracking and debugging.

Preferably, the second integrated debug unit further comprises,

a key and indicator lamp module;

the CDC serial port conversion module is used for converting interface types;

the USB data analysis module is used for analyzing the debugging instructions;

and the USB device management module is used for identifying and driving.

The beneficial effects of the invention are as follows: due to the adoption of the technical scheme, the on-line debugging function of the singlechip supporting multiple kernels is realized, the operation is simple and convenient, and the resource waste is avoided.

Drawings

FIG. 1 is a schematic diagram of a prior art OCD debug system;

FIG. 2 is a schematic diagram of an online debugging system in accordance with a preferred embodiment of the present invention;

FIG. 3 is a schematic diagram of a debugger according to a preferred embodiment of the present invention;

FIG. 4 is a block diagram of a master control chip according to a preferred embodiment of the present invention;

FIG. 5 is a flow chart of an online debugging system in a preferred embodiment of the present invention.

In the accompanying drawings: 1. the singlechip debugging module; 11. a first integrated debug unit; 111. a command storage subunit; 112. a protocol transmitting subunit; 12. an upper computer; 2. a debugger; 21. a second integrated debugging unit; 211. a protocol receiving subunit; 212. a core processor subunit; 213. a debug interface subunit; 22. a main control chip; 221. a JATG data sequence conversion module; 222. a SWD data sequence conversion module; 223. an IAP processing set module; 224. a USB device management module; 225. a USB data analysis module; 226. CDC serial port conversion module; 227. an OCD debugging module; 228. a GDB debug module; 229. a key and indicator lamp module; 3. a target singlechip; 31. a first target singlechip; 32. a second target singlechip; 33. a core chip; 34. and a kernel debugging module.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.

The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.

A singlechip on-line debugging system suitable for various kernels, as shown in figures 2 and 3, comprises,

the singlechip debugging module 1 sends a debugging instruction;

the debugger 2 is connected with the singlechip debugging module 1, the debugger 2 comprises a second integrated debugging unit 21, the second integrated debugging unit 21 comprises,

protocol receiving subunit 211 receives and parses the debug instruction, and obtains a parsed debug instruction;

a kernel processor subunit 212, performing debugging processing according to the resolved debugging instruction;

a debug interface subunit 213 that converts the parsed debug instruction into debug data;

the target singlechip 3 is connected with the debugger 2 and receives the debugging data, the target singlechip 3 comprises a kernel debugging module 34 and a kernel chip 33, the kernel debugging module 34 carries out debugging control on the kernel chip 33 according to the debugging data, and debugging information is fed back to the singlechip debugging module 1 through the debugger 2.

The on-line debugging system for the single chip microcomputer is applicable to the single chip microcomputer debugging simulation, integrates and optimizes various debugging software and transmission protocols, and is convenient to use and capable of avoiding resource waste according to the requirements of different kernel processor debugging systems.

In a preferred embodiment, the single chip debug module 1 comprises a first integrated debug unit 11, the first integrated debug unit 11 comprising,

a command storage subunit 111, configured to store debug instructions, where the debug instructions include single step operation, full speed operation, resetting a singlechip interface, setting a breakpoint, and stopping operation;

a protocol transmitting subunit 112, configured to perform USB protocol transmission;

the debug instruction also includes a set and acquire register, set and read register values, set and acquire upper computer pointers, write or read data to memory addresses, write or read banks.

Specifically, in order to achieve the consistency of debugging interfaces for various processors, the transmission protocol design is to define and adapt the debugging operations from different IDEs and different kernel processors to the transmission protocols of different IDEs and processors through the ideas of converging, diverging, optimizing and merging, optimize the instruction processing number for a specific processor, and reasonably use a synchronous and asynchronous mode to improve the downloading rate and the debugging response speed of the system; the method mainly comprises the functions of full-speed operation, stop operation, single-step operation, stop MCU, reset MCU interface, register setting, register obtaining, register value setting, register value reading, upper computer pointer setting, upper computer pointer obtaining, breakpoint setting, writing data to a memory address, reading memory data, writing a memory bank, reading a memory bank and the like.

In a preferred embodiment, the instruction set of the singlechip debugging module 1 comprises an 8051 kernel instruction set, an ARM kernel instruction set and a RISC-V kernel instruction set.

Specifically, the system comprises chip debugging IDE software (KEIL), a dynamic link library, a debugger 2 and a target singlechip 3; the IDE runs on the upper computer 12 and belongs to application software; the dynamic link library and registry configuration thereof and the host computer 12 driver software are packaged and integrated into an installation package file, and a user can complete one-key installation by clicking installation without secondary configuration.

More specifically, the implementation is realized by adopting a VC++ MFC framework aiming at Keil IDE upper computer 12 software, and mainly comprises an AGDI interface implementation module, a WinUSB driving module, a transmission protocol sending and analyzing module between debugger 2, a configuration byte user management module and the like, which are provided based on Keil; AGDI is a set of APIs provided by Keil, and contains all interface functions of downloading programs and simulation debugging, and is used for driving the online debugger 2; the AGDI interface is independent of the architecture of the processor, can conveniently realize the development of the drive and brings little expense; writing a target driver dll through the interface to connect the debugger 2 and the Keil IDE; all functions beginning with ag_need to be defined in the target driver dll, or a null function, for implementing the functions of the debugger 2; the data analysis processing module mainly adopts an asynchronous mode to issue and analyze instructions so as to reduce system blocking; aiming at Eclipse IDE, a USB driving module, a lower computer transmission protocol module, a FLASH programming algorithm and the like are required to be realized according to an OpenOCD realization framework.

In a preferred embodiment, the singlechip debugging module 1 and the debugger 2 are connected through WinUSB protocol, and the hardware interface is USB2.0.

Specifically, on one hand, the debugger 2 sends downlink data, receives debugging protocol data of the USB interface after the enumeration process of the USB device is completed, analyzes the obtained debugging command and debugging data, and writes the debugging command and the debugging data into a command register and a data register of the JTAG controller module respectively; and on the other hand, monitoring the return information of the target machine and sending the return information to the debugging host machine through the USB interface.

In a preferred embodiment, as shown in fig. 2 and 3, in the embodiment, the debugging interface between the debugger 2 and the first target singlechip 31 and the debugging interface between the debugger 2 and the second target singlechip 32 comprise a JATG interface, a SWD interface, a power supply voltage interface, a ground interface and a reset interface; the debugging interface between the debugger 2 and the target singlechip 3 comprises a JATG interface, a SWD interface, a power supply voltage interface, a grounding interface and a reset interface.

In a preferred embodiment, the debugger 2 is further provided with a clock line interface, an SWD data line interface, a data transmission interface, a data receiving interface, a JATG test data output port and a JATG test mode selection port.

Specifically, the system can freely switch various kernel singlechips for online debugging, optimizes Gpio conversion time sequences of JTAG and SWD, improves downloading and debugging speed, has small volume, is convenient to carry, low in manufacturing cost, simple in structural design, strong in usability and easy to popularize.

In a preferred embodiment, as shown in fig. 2 and 4, the main control chip 22 of the debug interface subunit 213 comprises,

a JATG data sequence conversion block 221 for generating a JATG data stream;

a SWD data sequence conversion module 222 for generating a SWD data stream.

In a preferred embodiment, the core processor subunit 212 includes,

IAP processing set module 223 for Flash programming;

an OCD debug module 227 for on-chip debugging;

GDB debug module 228 for trace debug.

In a preferred embodiment, the second integrated debug unit 21 further comprises,

a key and indicator module 229;

a CDC serial port conversion module 226 for converting interface types;

a USB data parsing module 225 for parsing debug instructions;

a USB device management module 224 for identification and driving.

Specifically, as shown in fig. 2 and 5, the IDE is loaded into the debug driver and opened; connecting the upper computer 12, the debugger 2 and the target singlechip 3, and powering up; IDE operates the debug button to start to enter a debug mode; the debugger 2 receives the debug instruction issued by the IDE and converts the debug instruction into a debug interface data stream identified by the MCU; the target MCU receives the debugging data stream, performs debugging control on the processor, and feeds the result back to the debugger 2; the debugger 2 feeds the data back to the IDE upper computer 12, and the upper computer 12 performs display and next operation to complete the debugging.

Further specifically, the KEIL IDE or Eclipse IDE environment is operated, a debugging device described in the system is inserted, and normal power supply is carried out on the target board; taking 8051 kernel MCU debugging as an example, opening a Keil to click a corresponding button to perform online debugging or downloading, starting a DOP module of the upper computer 12, wherein the DOP is responsible for transmitting corresponding instructions and data to the DOP module of the debugger 2, the debugger 2 converts the instructions into JTAG protocol data streams which can be identified by the MCU hardware debugging module, thus performing online debugging on the 8051MCU, and simultaneously returning data such as a debugging result TRACE, VAR_VIEW and the like to the Keil through the DOP protocol, thus completing one-time debugging operation on the 8051 MCU; the ARM core and the RISC-V core correspond to the DAP module and the GDB module respectively, and the debugging process is similar and will not be described herein.

In summary, the system comprises upper computer software running on the upper computer 12, hardware equipment of the debugger 2 and software firmware running on the debugger 2; the upper computer software running on the upper computer 12 mainly comprises Keil IDE software used by 8051 and ARM and Eclipse IDE software used by RISC-V, wherein Keil realizes communication with the debugger 2 by loading a developed dll dynamic library, thereby realizing debugging and downloading of a target MCU; the software protocol followed is the AGDI interface protocol; eclipse realizes communication with the debugger 2 by loading an exe object file produced by OpenOCD; the OpenOCD is an open source general upper computer debugging software, and supports various debugging interfaces; the specific model is required to be adapted according to the chip debugging interface, the OCD system, the FLASH type and the like; the firmware software running in the debugger 2 is mainly used for receiving a debugging downloading instruction issued by the IDE at the upper computer 12 end, converting the instruction into a JTAG or SWD data sequence identified by the target MCU debugging module, and feeding back debugging information and Trace information fed back to the upper computer 12IDE by the target MCU; the throughput and the response time of the USB bus are improved; the integrated optimization of transmission protocols between various debugging IDEs and debuggers 2, the addition of required FLASH programming algorithm, OCD debugging, TRACE, VAR_VIEW and other functions aiming at various requirements of different kernel processor debugging systems, realizes a singlechip on-line debugging system capable of supporting various kernels; the downloading speed is improved, and the function is stable, the cost is low and the use is convenient in the use process.

The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included within the scope of the present invention.

Claims (10)

1. A singlechip on-line debugging system suitable for multiple cores is characterized by comprising,

the singlechip debugging module (1) sends a debugging instruction;

the debugger (2) is connected with the singlechip debugging module (1), the debugger (2) comprises a second integrated debugging unit (21), the second integrated debugging unit (21) comprises,

a protocol receiving subunit (211) for receiving and analyzing the debug instruction to obtain an analyzed debug instruction;

a kernel processor subunit (212) for performing debugging processing according to the parsed debugging instruction;

a debug interface subunit (213) that converts the parsed debug instruction into debug data;

the target singlechip (3) is connected with the debugger (2) and receives the debugging data, the target singlechip (3) comprises a kernel debugging module (34) and a kernel chip (33), the kernel debugging module (34) is used for carrying out debugging control on the kernel chip (33) according to the debugging data, and debugging information is fed back to the singlechip debugging module (1) through the debugger (2).

2. The singlechip on-line debugging system suitable for various cores according to claim 1, wherein the singlechip debugging module (1) comprises a first integrated debugging unit (11), the first integrated debugging unit (11) comprises,

a command storage subunit (111) for storing the debug instruction, wherein the debug instruction comprises single-step operation, full-speed operation, resetting of a singlechip interface, setting of a breakpoint and stopping of operation;

and the protocol transmission subunit (112) is used for carrying out USB protocol transmission.

3. The on-line debug system of claim 2, wherein the debug instruction further comprises a set and fetch register, a set and read register value, a set and fetch upper pointer, a write or read data to memory address, a write or read bank.

4. The on-line debugging system of a single chip microcomputer applicable to multiple cores according to claim 1, wherein the instruction set of the single chip microcomputer debugging module (1) comprises an 8051 core instruction set, an ARM core instruction set and a RISC-V core instruction set.

5. The on-line singlechip debugging system applicable to multiple cores according to claim 4, wherein the singlechip debugging module (1) and the debugger (2) are connected through WinUSB protocol, and the hardware interface is USB2.0.

6. The on-line debugging system of a single chip microcomputer applicable to multiple cores according to claim 5, wherein the debugging interface between the debugger (2) and the target single chip microcomputer (3) comprises a JATG interface, a SWD interface, a power supply voltage interface, a grounding interface and a reset interface.

7. The on-line debugging system of the single chip microcomputer applicable to the multiple cores according to claim 6, wherein the debugger (2) is further provided with a clock line interface, an SWD data line interface, a data transmission interface, a data receiving interface, a JATG test data output port and a JATG test mode selection port.

8. The on-line debug system of a single chip microcomputer adapted to multiple cores according to claim 1, wherein said debug interface subunit (213) comprises,

a JATG data sequence conversion block (221) for generating a JATG data stream;

a SWD data sequence conversion module (222) for generating a SWD data stream.

9. The on-line debugging system of a single chip microcomputer adapted for multiple cores according to claim 1, wherein said core processor subunit (212) comprises,

an IAP processing set module (223) for Flash programming;

an OCD debug module (227) for on-chip debugging;

GDB debug module (228) for trace debug.

10. The on-line debugging system of a single chip microcomputer applicable to multiple cores according to claim 1, wherein said second integrated debugging unit (21) further comprises,

a key and indicator light module (229);

a CDC serial port conversion module (226) for converting interface types;

a USB data parsing module (225) for parsing the debug instruction;

a USB device management module (224) for identification and driving.