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CN102214615B - 具扇出且具堆栈用连接组件的半导体装置封装件及其制法 - Google Patents

具扇出且具堆栈用连接组件的半导体装置封装件及其制法 Download PDF

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CN102214615B
CN102214615B CN2011100432745A CN201110043274A CN102214615B CN 102214615 B CN102214615 B CN 102214615B CN 2011100432745 A CN2011100432745 A CN 2011100432745A CN 201110043274 A CN201110043274 A CN 201110043274A CN 102214615 B CN102214615 B CN 102214615B
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semiconductor device
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package
conductive layer
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CN102214615A (zh
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丁一权
陈家庆
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Advanced Semiconductor Engineering Inc
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Abstract

本发明提出了一种具扇出且具堆栈用连接组件的半导体装置封装件及其制法。该半导体装置封装件的实施例包括：(1)包含一图案化导电层的一互连单元；(2)实质上垂直延伸自导电层的一电性互连件；(3)毗邻于互连单元且电性连接至导电层的一半导体装置；(4)一封装件主体：(a)实质上覆盖互连单元的上表面及该装置；以及(b)毗邻于封装件主体的上表面定义一开口，并外露互连件的上表面；以及(5)电性连接至装置，实质上填满开口，且外露于装置封装件的外部周围的一连接组件。互连件的上表面于一第二平面之上及于一第三平面之下定义出一第一平面，第二平面由互连单元的上表面的至少一部分所定义，第三平面由封装件主体的上表面所定义。

Description

具扇出且具堆栈用连接组件的半导体装置封装件及其制法
技术领域
本发明是一般上有关于一种半导体装置封装件及其制造方法。更甚者，本发明是有关于具有金属柱及通孔(via hole)的半导体装置封装件及其制造方法。
背景技术
电子产品已逐步变得更加复杂，至少某种程度上受增进的功能及较小尺寸的需求所驱策。而增进的功能及较小尺寸的益处显现的同时，达到该些益处亦可能产生问题。尤其，电子产品通常必须容纳高密度半导体装置于有限的空间中。举例而言，可用于处理器、内存装置及其它主动或被动装置的空间，该空间能够相当地被缩限于手机、个人数字助理、膝上型计算机及其它可携式消费产品之中。在同时，半导体装置通常以提供对抗环境状况的保护及提供输入及输出电性连接的方式封装。于半导体装置封装件内半导体装置的封装可能占据电子产品内额外宝贵的空间。同样地，具有朝向减缩由半导体装置封装件所占据的行踪面积(footprint area)的强烈驱动力。对此相关的一种制造方法为堆栈半导体装置封装件于另一个的顶端上，以形成一堆栈封装件组合。不幸的是，由堆栈功能的观点看来，已知的晶圆级封装并不能够适用。
此外，于已知的晶圆级封装中，晶圆内的半导体装置于晶圆切单之前进行封装。同样地，已知的晶圆级封装可能局限于扇入(fan-in)配制，亦即电性接触件及完成的半导体装置封装件的其它零件局限于由半导体装置的周围所定义的区域中。任何设置于半导体装置周围外侧的零件通常不受支持且通常经由切单移除。当半导体装置尺寸日益缩小且欲在小尺寸的半导体装置进行扇入配置时，其配制限制将是一大挑战。
因此，需要开发出半导体装置封装件及其相关制造方法以克服先前技术的缺陷。
发明内容
本发明的一实施方面与一半导体装置封装件有关。于一实施例中，半导体装置封装件包括：(1)一互连单元，包含上表面及实质上旁侧延伸于互连单元内的一第一图案化导电层；(2)一电性互连件，实质上垂直延伸自第一图案化导电层，且包含：(a)一上表面；及(b)一下表面，毗邻于第一图案化导电层上表面；(3)一第一半导体装置，设置成毗邻于互连单元的上表面且电性连接至第一图案化导电层；(4)一封装件主体，设置成实质上覆盖互连单元的上表面及第一半导体装置，封装件主体毗邻于封装件主体上表面定义有一第一开口而外露电性互连件的上表面；以及(5)一连接组件，电性连接至第一半导体装置并实质上填满第一开口，且连接组件外露于半导体装置封装件的外部周围。电性互连件的上表面定义出一第一平面于一第二平面之上及于一第三平面之下，第二平面由互连单元的上表面的至少一部分所定义，第三平面由封装件主体的上表面所定义。
本发明的另一实施方面与一堆栈装置组合有关。于一实施例中，堆栈装置组合包括：(1)一半导体装置封装件，包含：(a)一互连单元，包含上表面；(b)一第一半导体装置，设置成毗邻于互连单元的上表面且电性连接至互连单元；及(c)一封装件主体，设置成毗邻于互连单元的上表面且实质上覆盖第一半导体装置，封装件主体包含上表面且毗邻于封装件主体的上表面定义有一开口；(2)一第二半导体装置，设置成毗邻于封装件主体的上表面；以及(3)一堆栈组件，延伸经过封装件主体中的开口且电性连接第一半导体装置及第二半导体装置，堆栈组件包含：(a)一电性互连件，包含上表面且实质上垂直延伸自互连单元；及(b)一经熔化的导电凸块(fused conductive bump)，至少通过电性互连件而电性连接至第一半导体装置，且实质上填满该开口，该熔化的导电凸块则外露于堆栈装置组合的外部周围。电性互连件的上表面定义出一第一平面于一第二平面之上及于一第三平面之下，第二平面由互连单元的上表面的至少一部分所定义，第三平面由封装件主体的上表面所定义。
本发明的另一实施方面与形成一半导体装置封装件的方法有关。该形成一半导体装置封装件的方法包括：(1)提供一第一半导体装置；(2)形成一互连结构，互连结构包含：(a)一上表面；(b)一下表面；及(c)实质上旁侧延伸于互连结构内的一图案化导电层；(3)形成一电性互连件，电性互连件包含上表面及毗邻于图案化导电层上表面的下表面，于此处电性互连件实质上垂直延伸自图案化导电层；(4)毗邻于互连结构的上表面设置第一半导体装置，以使第一半导体装置电性连接至图案化导电层；(5)敷设一模塑材料(molding material)以形成实质上覆盖电性互连件的上表面及第一导体装置的一模造结构；(6)于模造结构中形成一第一开口，第一开口为毗邻于模造结构的上表面且外露电性互连件的上表面，于此处从电性互连件上表面至电性互连件下表面间的一第一距离，大于从互连结构上表面至互连结构下表面间的一第二距离；以及(7)形成一第一连接组件，其电性连接至电性互连件且实质上填满第一开口。
本发明亦可具有其它实施方面及实施例。前述发明内容及下列特举实施例的详细描述与配合附图，并非意图将本发明局限于任何特定实施例，而仅用以描述本发明的若干实施例。
附图说明
为了较佳理解本发明的若干实施例的本质及对象，应参考上述实施方式并伴随下列附加图式。于图式中，除了前后文中清楚规定以外，相似的组件符号意味着相似组件。
图1绘示依照本发明的实施例，半导体装置封装件的透视图。
图2为沿图1中A-A剖面线所绘制本发明实施例的封装件的剖视图。
图3绘示依照本发明的实施例，堆栈装置组合的剖视图。
图4A至4S绘示依照本发明的实施例，形成图2的半导体装置封装件的方法。
主要组件符号说明：
100：半导体装置封装件；封装件
202、302：半导体装置
204、216、232、254、262a、262b、243、432、443、454：下表面
206、218、234、242、252、266a、266b、257a、257b、401、403、404、415、434、442、452、482：上表面
208、210、220、222、236、238、264a、264b：旁侧表面
212、212a、212b：连接件
213：底胶层
214：封装件主体
215a、215b、231a、231b、233a、233b、286、286a、286b、408a至408e、412a、412b、416a、416b：开口
223a、223b、224a、224b：部分
225a、225b、226a、226b、275a、275b：宽度
230、430：层状物
240：互连单元
244、246a、246b、247、248、417、483：平面
250、306、450：图案化导电层；导电层
251a、251b、260、260a、260b、451a、451b：电性互连件
253a、253b、453a、453b：第一表面
256a、256b：电镀层；表面处理层
270a、270b、272、274a、274b：高度
284、484：保护层
292、292a、292b：连接组件
294a、294b：电性接触件
300：堆栈装置组合
304a、304b：堆栈组件
310：上侧
312：下侧
400：承载件
402：导电层
402a、402b：次层
406、410、414：光阻层
434：距离
440：互连结构
480：模造结构
492：切缝
具体实施方式
定义
下列定义适用于描述关于本发明的若干实施例的若干实施方面。该些定义亦能据此予以延伸。
如使用于此，除了前后文中清楚规定以外，单数词汇「一」、「一个」及「该(the)」包含数个指示物。因此，举例而言，除了前后文中清楚规定以外，一电性互连件能包含多重电性互连件。
如使用于此，词汇「组(set)」指的是一个或多个零件的汇集。因此，举例而言，一组层状物能包含单一层状物或多重层状物。一组的零件能指的是该组的构成物。一组的零件能是相同的或相异的。于若干范例中，一组的零件能共享一个或多个共同的特征。
如使用于此，词汇「毗邻(adjacent)」指的是附近的(near)或邻接的(adjoining)。毗邻零件能彼此间隔开或者能实际上或直接彼此接触。于若干范例中，毗邻零件能彼此连接或彼此累积形成。
如使用于此，比较(relative)词汇，如「之内(inner)」、「内部(interior)」、「之外(outer)」、「外部(exterior)」、「顶端(top)」、「底部(bottom)」、「正(front)」、「背(back)」、「上(upper)」、「朝上(upwardly)」、「下(lower)」、「朝下(downwardly)」、「垂直(vertical)」、「垂直地(vertically)」、「旁侧(lateral)」、「旁侧的(laterally)」、「之上(above)」及「之下(below)」，指的是一组零件与另一组之间例如依据图式的方位，而并非指于制造或使用期间需要该些零件的特定方位。
如使用于此，词汇「连接(connect)」、「连接的(connected)」、「连接(connection)」指的是操作上耦合(coupling)或连结(linking)。连接的零件能彼此直接耦合或能彼此例如通过另一组零件而非直接耦合。
如使用于此，词汇「实质上地(substantially)」及「实质上(substantial)」指的是值得考虑的程度或幅度。当伴随一事件或情况时，该词汇能指的是使该事件或情况恰好发生的范例，以及使该事件或情况接近近似值发生的范例，例如描述于此可解释成制造作业的通常容许层级(typical tolerance level)。
如使用于此，词汇「导电(electrically conductive)」及「导电性(electricalconductivity)」指的是传输电流的能力。导电材料通常对应于那些呈现极少或无电流流动阻碍的材料。导电性的测量则以每公尺多少西门子(Siemens per meter)(「S·m-1」)来表示。通常而言，导电材料为具有大于约104S·m-1的导电性的材料，例如至少约105S·m-1或至少约106S·m-1。材料的导电性有时可能随温度变化。除非另外指定，否则皆以在室温的情况下定义材料的导电性。
本发明实施例的描述
首先请参照图1及图2，该些图式绘示依照本发明实施例实施的半导体装置封装件100。尤其，图1绘示封装件100的透视图，而图2为沿图1中A-A剖面线所绘制本发明实施例的封装件100的剖视图。
于所绘示的实施例中，封装件100的各侧面实质上为平面且具有实质上正交的方位，以便定义实质上延伸围绕封装件100完整周围的旁侧轮廓。有利地，此正交旁侧轮廓经由缩减或最小化封装件100的行踪面积而得以缩减整体封装件尺寸。然而一般而言，封装件100的旁侧轮廓能考虑为多种形状的任何形状，例如弯曲的、倾斜的、阶梯的或粗糙质地的。
请参照图2，半导体装置封装件100包含半导体装置202，半导体装置202包含下表面204、上表面206以及旁侧表面208及210，该旁侧表面208及210设置成毗邻于半导体装置202的周围且延伸于下表面204及上表面206之间。于所绘示的实施例中，该些表面204、206、208及210的每一表面实质上为平面，该些旁侧表面208及210相对于下表面204或上表面206具有实质上正交的方位，但该些表面204、206、208及210的形状及方位亦可能随其它实施方式而改变。如图2所示，上表面206为半导体装置202的背表面，而下表面204为半导体装置202的主动表面。于一实施例中，将连接件212a及212b设置成毗邻于下表面204。连接件212提供用于半导体装置202的输入及输出电性连接以连接至包含于封装件100的导电结构，例如图案化导电层250(如下所述)。于一实施例中，连接件212为焊料凸块。于一实施例中，可选择性地填充一底胶层213于下表面204及一互连单元240(如下所述)之间。底胶层213例如是包含环氧基树脂(epoxy)、树脂(resin)或其它合适的材料。于所绘示的实施例中，半导体装置202为一半导体芯片，但一般而言仍应考虑到半导体装置202能为任何主动装置、任何被动装置或其结合。而于图2中虽绘示一个半导体装置，对于其它实施方式而言亦仍能设计成包含额外的半导体装置。
如图2所示，半导体装置封装件100亦包含设置成毗邻于半导体装置202的封装件主体214。于所绘示的实施例中，封装件本体214伴随底胶层213实质上覆盖或包覆(encapsulate)半导体装置202及互连单元240(如下所述)的上表面242，以提供机械稳定性及抵抗氧化、湿气与其它环境状况的保护。于此实施例中，封装件主体214实质上覆盖半导体装置202的上表面206及旁侧表面208与210，而半导体装置202的下表面204则实质上外露于或未覆盖于封装件本体214。然而，在实际应用时封装件本体214的覆盖幅度亦可设计成异于图2所示。举例而言，封装件本体214可设计成能实质上覆盖旁侧表面208及210，而实质上皆未覆盖下表面204及上表面206二者。
如图2所示，封装件主体214包含下表面216、上表面218及旁侧表面220与222，该旁侧表面220与222设置成毗邻于封装件本体214的周围且延伸于下表面216及上表面218之间。于所绘示的实施例中，该些表面216、218、220及222的每一表面实质上为平面，该些旁侧表面220及222相对于下表面216及上表面218具有实质上正交的方位，但仍应考虑到该些表面216、218、220及222的形状及方位可能随其它实施方式而改变。
于一实施例中，封装件本体214能由模塑材料形成。举例而言，模塑材料能包含酚醛基(Novolac-based)树脂、环氧基树脂、硅基树脂或另一合适的包覆料。亦能包含如粉状二氧化硅的合适的填充剂。该模塑材料能为预浸(pre-impregnated(prepreg))材料，例如预浸介电材料。实际应用时，亦可设计成封装件主体214能包含伴随或取代模塑材料的支撑结构。举例而言，封装件主体214能包含框架或内转接板(interposer)，其能由玻璃、硅、金属、金属合金、聚合物或另一合适的结构材料所形成。
如图2所示，层状物230包含下表面232、上表面234及旁侧表面236与238，该旁侧表面236与238设置成毗邻于该层状物230周围，且延伸于下表面232及上表面234之间。于所绘示的实施例中，该些表面234、236及238的每一表面实质上为平面，旁侧表面236及238相对于上表面234具有实质上正交的方位，但实际应用时，仍可设计成该些表面234、236及238的形状及方位可能随其它实施方式而改变。图中显示出下表面232延伸进图案化导电层250(如下所述)的开口内，但下表面232的形状及方位在实际应用时仍可能随其它实施方式而改变。举例而言，下表面232能实质上为平面。上表面234能毗邻于封装件主体214的下表面216。
于一实施例中，层状物230能由聚酰亚胺(polyimide)、聚苯恶唑(polybenzoxazole)、苯环丁烯(benzocyclobutene)或其结合等的介电材料所形成。对于特定实施方式而言，层状物230能由光显影(photoimageable)或光活化(photoactive)的介电材料所形成。于另一实施例中，层状物230能由防焊屏蔽(solder mask)(防焊阻剂(solder resist))(例如干膜式可显影型(dry filmimageable)防焊屏蔽)或另一类型的图案化层或介电层所形成。于一实施例中，层状物230的厚度能在10微米(micron)至30微米的范围中，例如10微米至20微米的范围，或20微米至30微米的范围。虽然图2中绘示单一层状物230作为封装件100的部分，于其它实施例的半导体装置封装件中应考虑到能包含多个与层状物230相仿的布局及特征的层状物。
如图2所示，半导体装置封装件100进一步包含毗邻于层状物230下表面232的图案化导电层250。图案化导电层250具有上表面252及下表面254。图案化导电层250能包含电性互连件251a及251b。该些电性互连件251a及251b能实质上旁侧延伸于图案化导电层250之内。电性互连件251a及251b分别具有第一表面253a及253b，其能包含于图案化导电层250的上表面252中。封装件100进一步包含电性互连件260a及260b。
电性互连件251a能将电性互连件260a电性连接至一电性接触件294a或另一电性互连件(未显示)。于一实施例中，电性互连件251a能于毗邻于图案化导电层250的保护层284中的开口286a处，与电性接触件294a或另一电性互连件相毗邻。电性互连件251b能将电性互连件260b电性连接至电性接触件294b或另一电性互连件(未显示)。于一实施例中，电性互连件251b能于保护层284中的开口286b处，与电性接触件或另一电性互连件相毗邻。
电性互连件260a及260b分别具有下表面262a与262b、旁侧表面264a与264b及上表面266a与266b。电性互连件260a及260b则是置放成围绕半导体装置202，且能实质上分别垂直延伸自第一表面253a及253b。下表面262a及262b能分别毗邻于第一表面253a及253b。第一表面253a及253b的至少一部分能实质上由层状物230所覆盖。旁侧表面264a与264b的至少一部分能实质上被层状物230所覆盖。
如图2所示，能形成层状物230以便于定义开口233a及233b，该些开口233a及233b定位对准且按一定尺寸制成以便于分别容纳该些连接件212a及212b。连接件212a及212b能毗邻于图案导电层250的上表面252。可替代地，该些连接件212a及212b亦能分别毗邻于电镀层256a及256b(或表面处理层(finish layer)256a及256b)。电镀层256a及256b能设置成毗邻于图案化导电层250的上表面252，且能分别设置于开口233a及233b中。
图案化导电层250能包含于互连单元240中。此外，电镀层256a与256b及层状物230可选择性地包含于互连单元240中。图案化导电层250能实质上旁侧延伸于互连单元240之内。图案化导电层250的上表面252能包含于互连单元240的上表面242中。此外，该些电镀层256a与256b其分别的上表面257a与257b以及层状物230的上表面234能包含于互连单元240的上表面242中。该互连单元240亦包含下表面243。图案化导电层250的下表面254能包含于下表面243中。此外，层状物230的下表面232的部分能包含于下表面243中。
如图2所示，形成封装件本体214以便于定义开口215a及215b。形成层状物230以便于定义开口231a及231b，其中开口231a及231b能实质上分别对准开口215a及215b。开口215a及215b能从上表面218分别延伸至该些电性互连件260a及260b的上表面266a及266b，且能外露上表面266a及266b。开口231a及231b能从层状物230的上表面234延伸至下表面232，且能设置成毗邻于图案化导电层250的上表面252。电性互连件260a的上表面266a能定义平面246a于平面247之上及于平面248之下，该平面247由互连单元240的上表面242的至少一部分所定义(例如电镀层256a及256b其分别的上表面257a及257b中的至少一者)，该平面248由封装件主体214的上表面218所定义。相仿地，电性互连件260b的上表面266b能定义平面246b于平面247之上及于平面248之下。于一实施例中，电性互连件260a能实质上填满开口231a，及/或电性互连件260b能实质上填满开口231b，以使该些平面246a及246b的至少一者位于平面244之上，该平面244由层状物230的上表面234所定义。可替代地，该些平面246a及246b的至少一者能分别位于平面247之上及于平面248之下。
如图2所示，连接组件292a及292b外露于半导体装置封装件100的外部周围。该些连接组件292a及292b提供用于封装件100的输入及输出电性连接，且连接组件292a及292b的至少一者通过图案化导电层250及电性互连件260的至少一者电性连接至半导体装置202。于所绘示的实施例中，连接组件292a及292b为导电凸块，例如焊料凸块。可替代地，连接组件292a及292b能为经熔化的导电凸块，例如已回焊且与其它导电组件(如其它焊料凸块)结合的焊料凸块。经熔化的导电凸块形成以提供于封装件100及堆栈于封装件100上的另一半导体装置(如图3中所示)及/或半导体封装件间的导电性。于一实施例中，可自封装件100的外侧通过该些连接组件292a及292b物理性地进入封装件100。举例而言，通过该些连接组件292的可物理性进出的能力，可使连接组件292回焊成为于封装件100上另一半导体装置及/或封装件的堆栈的一部分。该些连接组件292能由焊料膏形成，其中焊料膏能包含锡、铜及其它各种合适材料的其中至少一者。
有利地，能按一定尺寸制作开口215a及215b，以使连接组件292a及292b能实质上分别填满开口215a及215b，以达到最小化及/或避免空隙(void)产生。于开口215a及215b内避免空隙发生可增进电性互连件260及连接组件292的导电性，因而增进介于封装件100及堆栈于该封装件100上的另一半导体装置(如图3中所示)及/或半导体装置封装件间的导电性。控制开口215a及215b按一定尺寸制作的进一步的优点，为促进控制形成连接组件292a及292b的导电材料体积。于一实施例中，能于开口215a及215b内经由按一定尺寸制作电性互连件260a及260b而达到最小化及/或避免空隙产生，以使平面246a及246b位于平面247之上，因而使开口215a及215b的高度270a及270b受到控制。于一实施例中，对于该些开口215a及215b其分别的高度270a及270b而言，可为400微米或更小，以达到最小化及/或避免于开口215a及215b内产生空隙。举例而言，封装件本体214的高度272能于200微米至500微米的范围中，例如200微米至300微米的范围，300微米至400微米的范围，或400微米至500微米的范围。于此范例中，电性互连件260a及260b其分别的高度274a及274b能足够大(例如大于100微米)到使开口215a及215b的高度270a及270b为400微米或更小。高度270a及270b能大于、等于或小于高度274a及274b。
于一实施例中，连接组件292a及292b能突出于封装件本体214的上表面218之外。连接组件292a及292b的突出部分能增加外露的连接组件292a及292b的接触面积，而使封装件100及堆栈于封装件100上的另一半导体装置(如图3中所示)及/或半导体装置封装件间，能有较强的物理接合及较佳的导电性。可替代地，连接组件292a及292b能不突出于封装件本体214的上表面218之外。举例而言，连接组件292a及292b能延伸至但不突出于上表面218之外，以实质上填满开口215a及215b。
于一实施例，开口215a及215b的部分224a及224b分别毗邻于电性互连件260a及260b的上表面266a及266b。部分224a的宽度226a能小于上表面266a的宽度275a，且部分224b的宽度226b能小于上表面266b的宽度275b。
于一实施例中，开口215a及215b的部分223a及223b毗邻于由封装件本体214的上表面218所定义的平面248。部分223a的宽度225a能大于部分224a的宽度226a，且部分223b的宽度225b能大于部分224b的宽度226b。
有利地，图案化导电层250能作为用于半导体装置202的重分配网络(redistribution network)。于一实施例中，半导体装置封装件100能提供一扇出(fan-out)配制，其中图案化导电层250实质上旁侧延伸至半导体装置202的周围外侧。举例而言，图2显示电性互连件251a及251b位于半导体装置202的周围外侧。电性互连件251a及251b能通过于图案化导电层250中的其它电性互联(未显示)电性连接至半导体装置202。封装件100的扇出配置得使电性接触件294a及294b的安排及隔间具较优越的灵活度，而得减少对于半导体装置202接触垫的安排及间隔的依赖。电性互连件260a及260b及连接组件292a及292b能经由从半导体装置202至封装件100的上表面设置电性路径而促使将其延伸至三维扇出(参见图3)。
电性接触件294a及294b提供用于封装件100的输入及输出电性连接，且电性接触件294a及294b的其中至少一者通过导电层250电性连接至半导体装置202。于所绘示的实施例，电性接触件294a及294b为导电凸块。例如焊料凸块。可替代地，电性接触件294a及294b能为经熔化的导电凸块，例如已回焊且与其它导电组件(如其它焊料凸块)结合的焊料凸块。
依据封装件100的扇出配置，连接组件292a与292b及电性接触件294a与294b旁侧设置于半导体装置202的周围外侧，但一般应用时仍亦可设计成电性接触件294a与294b可旁侧设置于其周围、其周围外侧或二者皆设置。于此方式中，封装件100的扇出配置得使电性接触件294a及294b的安排及隔间具较优越的灵活度，而得减少对于半导体装置202接触垫的安排及间隔的依赖。
一般而言，图形化导电层250及电性互连件260a及260b中的每个电性互连件能由金属、金属合金、具金属或金属合金分散于其中的基质或另一合适的导电材料所形成。举例而言，图形化导电层250及电性互连件260a及260b中的至少一者能由铝、铜、钛或其结合所形成。图形化导电层250及电性互连件260a及260b中的每个电性互连件能由相同导电材料或相异导电材料所形成。
电镀层256a及256b能相仿于如先前所述的图案化导电层250而形成。可替代地，电镀层256a及256b能以相异方式形成。举例而言，电镀层256a及256b能由锡、镍及金或含锡或含镍及金的合金中的至少一者所形成。电镀层256a及256b能由相同导电材料或相异导电材料所形成。
保护层284相仿于如先前所述的层状物230而形成。保护层284能使用例如干膜式可显影型防焊屏蔽的防焊屏蔽(solder mask)(防焊阻剂(solder resist))或另一类型的图案化层或介电层所形成。虽然图2中绘示单一保护层284，对于其它实施方式而言亦能包含多个保护层。于保护层284中的开口，例如开口286a及286b，能外露导电层250的部分，例如电性互连件251a及251b中至少一者的部分。开口286a及286b能实质上分别与电性互连件260a及260b的下表面262a及262b的至少其中一者对准。能图案化保护层284以形成该些开口286。该些开口286能具有多种形状中的任何形状，该些形状包含柱形的形状，例如圆柱形、椭圆柱形、正方柱形或矩形柱形，或者包含非柱形的形状，例如圆锥形、漏斗形或另一锥形。亦可将该些完成的开口的旁侧边界设计为弯曲的或质地粗糙的。
请参照图3，为绘示依照本发明实施例的堆栈装置组合300剖视图。于此实施例，堆栈装置组合300包含堆栈于封装件100上的半导体装置302。半导体装置302亦能不予以封装。可替代地，堆栈装置组合能包含另一半导体装置封装件(未显示)堆栈于封装件100上。所谓另一半导体装置封装件能与封装件100相仿，能包含相仿于图案化导电层250的图案化导电层，且能包含相仿于半导体装置202的半导体装置。半导体装置302及/或另一半导体装置封装件能设置成毗邻于封装件主体214的上表面或位于其上。虽然绘示于图3中的堆栈装置组合300包含二层堆栈，对于其它实施方式而言此堆栈亦可设计成包含超过二层堆栈。
如图3所示，堆栈装置组合300能包含堆栈组件304a及304b，其中至少一者通过图案化导电层250及图案化导电层306电性连接半导体装置202及半导体装置302。堆栈组件304a包含电性互连件260a及连接组件292a，且堆栈组件304b包含电性互连件260b及连接组件292b。堆栈组件304a能延伸经过且实质上填满于封装件主体中214的开口215a，且堆栈组件304b能延伸经过且实质上填满于封装件主体中214的开口215b。于此实施例中，连接组件292a及292b以经熔化的导电凸块形成而外露于堆栈装置组合300的外部周围。如前所述，连接组件292可从封装件100外侧物理性地进入。
于一实施例中，能将连接组件292a及292b熔化至图案化导电层306，以形成经熔化的导电凸块而外露于堆栈装置组合300的外部周围。图案化导电层306能设置成毗邻于封装件主体214的上表面。可替代地，能将连接组件292a及292b熔化至堆栈于封装件100上的另一半导体封装件的电性接触件(与电性接触件294a及294b相仿)，其中电性接触件电性连接至另一半导体装置封装件中的图案化导电层(与该图案化导电层250相仿)。
如图3所示，堆栈装置组合300能包含图案化导电层306，其能作为用于半导体装置302的重分配网络。于一实施例中，堆栈装置组合300能提供一扇出配制，其中图案化导电层306电性连接至该半导体装置302且实质上旁侧延伸至半导体装置302的周围外侧。如前所述，封装件100的电性互连件260a及260b及连接组件292a及292b能经由从半导体装置202至封装件100的上表面设置电性路径而促使二维扇出延伸成三维扇出。能经由将连接组件292a及292b电性连接至图案化导电层306而产生三维扇出配置。就于堆栈装置组合300的上侧310及下侧312二者上的电性接触件的安排及间隔而言，此三维扇出配置能有利增加灵活度更胜于由二维扇出所提供的灵活度。
图4A至4S绘示依照本发明的实施例，形成图2的半导体装置封装件100的方法。为易于说明，将参照图2的封装件100描述下列制造作业。然而，亦能相仿地依上述实施例的制造作业，形成其它能异于封装件100的内部结构的半导体装置封装件。
首先参照图4A，提供承载件400，将导电层402设置成毗邻于承载件400的上表面401。导电层402具有上表面404，且能包含多重次层402a及402b。次层402a能由金属、金属合金、具金属或金属合金分散于其中的基质或另一合适的导电材料所形成。举例而言，次层402a能包含由铜或含铜合金所形成的金属薄层。次层402a能附属于承载件400，其具有设置成毗邻于该承载件400上表面401的胶带(未显示)。该胶带能考虑为单面或双面黏着胶带以使零件间彼此以适当空间固接，而得使用设置成毗邻于承载件400的零件来实行后续的制造作业。
如图4A所示。次层402b能敷设于次层402a的上表面403。能使用多种涂层技术中的任何技术，例如化学气相沉积(chemical vapor deposition)、无电电镀(electroless plating)、电解电镀(electrolytic plating)、印刷(printing)、纺织(spinning)、喷雾(spraying)、溅镀(sputtering)或真空沉积(vacuum deposition)，来敷设次层402b。次层402b能由金属、金属合金、具金属或金属合金分散于其中的基质或另一合适的导电材料所形成。次层402b能由相异于形成次层402a所使用的导电材料所形成。举例而言，次层402b能作为蚀刻停止层，且能包含镍或含镍合金。
接着，如图4B所示，能将光阻材料敷设于导电层402的上表面404，以毗邻于该上表面404形成一光阻层406。该光阻材料能为干膜光阻或另一类型的可图案化层或介电层。另能经由涂层、印刷或任何其它合适的技术形成光阻层406。且能光显影及显影(develop)光阻层406的预定或所选择的部分，以便于产生包含开口408a至408e的开口，而外露导电层402的上表面404。还能使用光屏蔽(未显示)光化学定义光阻层406。相较于其它用于在光阻层406中产生开口的途径，光显影及显影能具有低成本及减少处理时间的优点。完成的开口能具有多种形状中的任何形状，该些形状包含柱形的形状，例如圆柱形、椭圆柱形、正方柱形或矩形柱形，或者包含非柱形的形状，例如圆锥形、漏斗形或另一锥形。亦可依应用所需设计成完成的开口的旁侧边界为弯曲的或质地粗糙的。
接着，如图4C所示，将导电材料敷设进包含由光阻层406定义的开口408a至408e的该些开口内，以形成包含电性互连件451a及451b的导电层450。导电层450及电性互连件451a及451b能实质上旁侧延伸，且能使用与前述导电层250及电性互连件251a及251b(如图2中所示)相同类型的材料来形成。图案化导电层450能使用多种涂层技术中的任何技术而形成，例如化学气相沉积、无电电镀、电解电镀、印刷、纺织、喷雾、溅镀或真空沉积(vacuum deposition)等技术。
接着，如图4D所示，去除光阻层406以外露次层402b的部分。
接着，如图4E所示，将层状物430形成毗邻于图案化导电层450及次层402b的外露部分。层状物430能实质上覆盖图案化导电层450的上表面452，以使图案化导电层450埋设于层状物430中。另能使用多种如印刷、纺织和喷雾的涂层技术中的任何技术来敷设介电材料。于一实施例中，能经由将介电材料层压(laminate)于图案化导电层450的上表面452(包含第一表面453a及453b，对应于图2中的第一表面253a及253b)上及次层402b的外露部分上，而产生层状物430。可替代地，能经由将呈液态的介电材料涂布于图案化导电层450的上表面452(包含第一表面453a及453b)上及次层402b的外露部分上，而产生该层状物430。可替代地，层状物430能由例如干膜式可显影型防焊屏蔽的防焊屏蔽(防焊阻剂)或另一类型的图案化层或介电层所形成。层状物430能使用与前述层状物230(如图2中所示)相同类型的材料来形成。
接着，如图4F所示，于层状物430中形成开口231a及231b以分别外露电性互连件451a及451b的第一表面453a及453b。此外，于层状物430中形成开口233a及233b以分别外露图案化导电层450的上表面452的额外部分。以此方式中，图案化该层状物430以形成该些开口231a、231b、233a及233b。该些开口231a、231b、233a及233b能从层状物430的上表面434延伸至层状物430的下表面432。能以多种如光微影术(photolithography)、化学蚀刻、激光钻孔或机械钻孔的方式中的任何方式来实行图案化以形成层状物430，且该些完成的开口能具有多种形状中的任何形状，例如柱形的形状，如圆柱形、椭圆柱形、正方柱形或矩形柱形，或者非柱形的形状，如圆锥形、漏斗形或另一锥形。亦可依应用所需设计成完成的开口的旁侧边界为弯曲的或质地粗糙的。
接着，如图4G所示，能将光阻材料敷设于层状物430的上表面434，以毗邻于上表面434形成光阻层410。光阻材料能为干膜光阻或另一类型的可图案化层或介电层。能如先前图4B所述形成光阻层410。亦能如先前图4B所述，光显影及显影该光阻层410的预定或所选择的部分，以便于产生包含开口412a及412b的开口。该些开口412a及412b能分别对准于开口233a及233b，以外露图案化导电层450的上表面452的部分。开口412a及412b能具有与开口408a至408e相仿的特征。
接着，如图4H所示，将导电材料敷设进外露图案化导电层450的上表面452的部分的开口233a及233b内。以此方式中，能使用先前图4C所描述的技术中的任何技术，形成电镀层256a及256b。
接着，如图4I所示，去除光阻层410以外露层状物430的上表面434及电性互连件451a及451b其分别的第一表面453a及453b。去除光阻层410而外露先前已形成的互连结构440。于此实施例中，互连结构440包含层状物430、图案化导电层450及电镀层256a及256b。于其它实施例中，互连结构440(与互连单元240相仿)能包含图案化导电层450及能可选择性地包含电镀层256a及256b而不包含层状物430。如先前所述，图案化导电层450的上表面452能包含于互连结构440的上表面442中。此外，电镀层256a及256b其分别的上表面257a及257b以及层状物430的上表面434能包含于互连结构440的上表面442中。图案化导电层450的下表面454能包含于互连结构440的下表面443中。此外，层状物430的下表面432的部分能包含于下表面443中。
接着，如图4J所示，能将光阻材料敷设于层状物430的上表面434及电镀层256a及256b，以毗邻于上表面434及电镀层256a及256b形成光阻层414。光阻材料能为干膜光阻或另一类型的可图案化层或介电层。能如先前图4B所述形成光阻层414。亦能如先前图4B所述，光显影及显影光阻层414的预定或所选择的部分，以便于产生包含开口416a及416b的开口。该些开口416a及416b能分别对准于开口231a及231b，以外露第一表面453a及453b。开口416a及416b能具有与开口408a至408e相仿的特征。
接着，如图4K所示，将导电材料敷设进由光阻层414定义的开口416a及416b内以及敷设进开口231a及231b内，以分别形成电性互连件260a及260b。能将电性互连件260a及260b形成为自该导电层402实质上垂直延伸远离。电性互连件260a能实质上填满开口416a及231a，且电性互连件260b能实质上填满开口416b及231b。可替代地，分别由电性互连件260a及260b的上表面266a及266b所定义的平面246a及246b，能位于由光阻层414的上表面415所定义的平面417之下。还能使用多种涂层技术中的任何技术，例如电解电镀或塞入由导电材料所组成的膏状物，形成电性互连件260a及260b。
接着，如图4L所示，去除光阻层414以外露层状物430的上表面434、电镀层256a及256b以及该些电性互连件260a及260b其分别的旁侧表面264a及264b。于连接至任何半导体装置202之前的此阶段中，互连结构440及电性互连件260a及260b二者皆已形成。再于连接至任何半导体装置202之前，能先测试互连结构440及电性互连件260a及260b。因此，半导体装置202将装设(例如图4M所示)至性能令人满意的互连结构440及电性互连件260a及260b。经由移除有缺陷的互连结构，可有利地防止或减少起因于互连结构的制造良率损失而造成的半导体装置202损失，其中制造良率损失例如是因图案化失误而造成的良率损失。
接着，如图4M所示，将半导体装置202设置成毗邻于互连接构440的上表面442。半导体装置202能以覆晶(flip-chip)方式连结，以使半导体装置202通过连接件212a及212b电性连接至图案化导电层450及电性互连件260a及260b。如先前所述，于一实施例中，可选择性地填充底胶层213于半导体装置202的下表面204及层状物430之间
接着，如图4N所示，能敷设模塑材料以形成模造结构480。该模造结构480能实质上覆盖或包覆半导体装置202的上表面206及旁侧表面208与210。该造结构480亦能实质上覆盖或包覆该些电性互连件260a及260b其分别的旁侧表面264a及264b及上表面266a及266b。形成模造结构480的模塑材料能例如包含酚醛基树脂、环氧基树脂、硅基树脂或另一合适的包覆料。亦能包含如粉状二氧化硅的合适的填充剂。模造结构480能使用多种如射出成型(injection molding)的模塑技术中的任何技术来形成。一经敷设，则硬化或固化该模塑材料，例如经由将温度降低至模塑材料的熔点以下，从而形成模造结构480。为了于后续切单作业期间促成模造结构480恰当定位，于模造结构480中形成基准标记，例如使用激光标记。
接着，如图4O所示，于模造结构480中形成开口215a及215b。该些开口215a及215b能毗邻于模造结构480的上表面482，且能外露该些电性互连件260a及260b其分别的上表面266a及266b。距离274a指的是从电性互连件260a的上表面266a至下表面262a间的距离，而距离274b指的是从电性互连件260b的上表面266b至下表面262b间的距离。距离434指的是从由互连结构440的上表面442所定义的平面247至互连结构440的下表面443间的距离。于一实施例中，根据该些电镀层256a及256b其分别的上表面257a及257b的其中至少一者定义平面247。但是可替代地，距离434亦能为上表面442的不同部分至下表面443间的距离。距离274a及274b的其中至少一者能大于该距离434。
毗邻于模造结构480的上表面482能经由钻孔移除模造结构480的一部分，而形成开口215a及215b。使用激光钻孔比机械钻孔有利，使得因钻孔而对由该模造结构480包覆的结构(例如电性互连件260、互连结构440及半导体装置202)造成伤害的可能性达到最小化。
接着，如图4P所示，形成连接组件292a及292b。该些连接组件292a及292b能实质上分别填满开口215a及215b。于一实施例中，连接组件292能突出于由模造结构480的上表面482定义的平面483之外。该些连接组件292a及292b能分别电性连接至该些电性互连件260a及260b。如先前所述，连接组件292a及292b能由焊料膏形成，其中焊料膏能包含锡、铜及其它各种合适材料的其中至少一者。另能经过印刷、塞入、电镀或经过其它合适技术形成连接组件292a及292b。
有利地，连接组件292a及292b形成于钻入该模造结构480内的开口215a及215b中。如此将省下处理步骤，例如：于图4M之后敷设及图案化另一光阻层，于图案化光阻层中的开口中形成连接组件292，去除光阻层，再敷设模造结构480。自将开口215钻入该模造结构480起，于图4M之后毋需产生额外的光阻层。
接着，如图4Q所示，移除承载件400而外露导电层450。再毗邻于导电层450形成保护层484。另能以相仿于如先前所述的保护层284的方式来形成保护层484。虽然图4M中绘示单一保护层284，对于其它实施方式而言应考虑到能包含多个保护层。于保护层484中的开口，例如开口286a及286b，能外露导电层450的部分。还能图案化保护层484以形成开口286a及286b，此与先前所述的层状物430图案化相仿。
接下来如图4R所示沿虚线实行切单。于所绘示的实施例中，能使用形成切缝492的锯子(未显示)实行切单。于切单期间锯子能经由基准标记辅助其对准，当形成切缝492时该基准标记能使该锯子恰当定位。再者，将切缝492完全延伸穿透模造结构480、互连结构440及保护层484，从而将模造结构480、互连结构440及保护层484细分成分离的单元，其包含封装件主体214、互连单元240及保护层284。于切单后，如图4S所示，如焊料凸块的外部连接件能电性连接至互连单元240，该互连单元240例如分别于开口286a及286b中的电性接触件294a及294b。
虽已参照本发明的特定实施例描述本发明，通常知识者仍应理解到，可能在不悖离由权利要求书所定义的本发明的真实精神及范畴内进行各种变更以及替换均等物。此外，能进行许多修饰以使特殊状态、材料、事物的布局、方法或处理适应于本发明的对象、精神及范畴。所有如此的修饰皆意指落入权利要求书的范畴内。尤其，虽已参照以特定顺序实施的特定作业于此描述该方法，将理解到能结合、细分、重新排序该些作业，以形成均等方法而不悖离本发明的教示。因此，除非于此特别指出以外，该些作业的顺序及集合并非本发明的限制。

Claims (19)

1.一种半导体装置封装件，包括：
一互连单元，包括：
一上表面；及
一第一图案化导电层，旁侧延伸于该互连单元内；
一电性互连件，垂直延伸自该第一图案化导电层，且包括：(a)一上表面；及(b)毗邻于该第一图案化导电层一上表面的一下表面；
一第一半导体装置，设置成毗邻于该互连单元的该上表面且电性连接至该第一图案化导电层；
一封装件主体，设置成覆盖该互连单元与该第一半导体装置的该上表面，该封装件主体毗邻于该封装件主体的一上表面定义有一第一开口而外露该电性互连件的该上表面；以及
一连接组件，电性连接至该第一半导体装置并填满该第一开口，且该连接组件外露于该半导体装置封装件的一外部周围；
其中，该电性互连件的该上表面定义出一第一平面于一第二平面之上及于一第三平面之下，该第二平面由该互连单元的该上表面的至少一部分所定义，该第三平面由该封装件主体的该上表面所定义。
2.如权利要求1所述的半导体装置封装件，其中：
该互连单元进一步包括一第一层状物，该第一层状物毗邻于该第一图案化导电层的该上表面；
该第一层状物包括一第二开口，该第二开口毗邻于该第一图案化导电层的该上表面；以及
该电性互连件填满该第二开口。
3.如权利要求2所述的半导体装置封装件，其中：
该第一层状物包括一第三开口，该第三开口从该第一层状物的一上表面延伸至该第一层状物的一下表面；以及
该第三开口对准于该第一半导体装置的一接触垫。
4.如权利要求3所述的半导体装置封装件，其中，该互连单元进一步包括一表面处理层，该表面处理层毗邻于该第一图案化导电层的该上表面且设置于该第三开口中。
5.如权利要求4所述的半导体装置封装件，其中，该第二平面由该表面处理层的一上表面所定义。
6.如权利要求2所述的半导体装置封装件，其中，该第一平面位于一第四表面上方，该第四表面由该第一层状物的一上表面所定义。
7.如权利要求2所述的半导体装置封装件，其中，该连接组件为一经熔化的导电凸块，且电性连接该第一半导体装置及一第二半导体装置。
8.如权利要求2所述的半导体装置封装件，其中：
该第一开口包括一第一部分，该第一部分毗邻于该电性互连件的该上表面；以及
该第一开口的该第一部分具有一第一宽度，该第一宽度小于该电性互连件的该上表面的一第二宽度。
9.如权利要求8所述的半导体装置封装件，其中：
该第一开口包括一第二部分，该第二部分毗邻于该第三平面；以及
该第一开口的该第二部分具有一第三宽度，该第三宽度大于该第一宽度。
10.一种堆栈装置组合，包括：
一半导体装置封装件，包括：
一互连单元，包括一上表面
一第一半导体装置，设置成毗邻于该互连单元的该上表面且电性连接至该互连单元；及
一封装件主体，设置成毗邻于该互连单元的该上表面且覆盖该第一半导体装置，该封装件主体包括一上表面且定义有设置成毗邻于该封装件主体的该上表面的一开口；
一第二半导体装置，设置成毗邻于该封装件主体的该上表面；以及
一堆栈组件，延伸经过该封装件主体中的该开口且电性连接该第一半导体装置及该第二半导体装置，该堆栈组件包括：
一电性互连件，包括一上表面且垂直延伸自该互连单元；及
一经熔化的导电凸块，至少通过该电性互连件而电性连接至该第一半导体装置，且填满该开口，该经熔化的导电凸块则外露于该堆栈装置组合的一外部周围；
其中，该电性互连件的该上表面定义出一第一平面于一第二平面之上及于一第三平面之下，该第二平面由该互连单元的上表面的至少一部分所定义，该第三平面由该封装件主体的该上表面所定义。
11.如权利要求10所述的堆栈装置组合，其中，该半导体装置封装件包括一图案化导电层，该图案化导电层设置成毗邻于该封装件主体的该上表面，且其中该第二半导体装置至少通过该图案化导电层而电性连接至该经熔化的导电凸块。
12.如权利要求10所述的堆栈装置组合，
进一步包括一第二半导体封装件，该第二半导体封装件包括：
该第二半导体装置；以及
一图案化导电层，包括一下表面；
其中，该第二半导体装置至少通过该图案化导电层而电性连接至该经熔化的导电凸块。
13.如权利要求12所述的堆栈装置组合，其中，该经熔化的导电凸块突出于该封装件本体的该上表面之外且毗邻于该图案化导电层的该下表面。
14.一种形成半导体装置封装件的方法，包括：
提供一第一半导体装置；
形成一互连结构，该互连结构包括：
一上表面；
一下表面；及
一图案化导电层，旁侧延伸于该互连结构内；
形成一电性互连件，该电性互连件包括一上表面及一下表面，该下表面毗邻于该图案化导电层的一上表面，其中该电性互连件垂直延伸自该图案化导电层；
设置该第一半导体装置毗邻于该互连结构的该上表面，以使该第一半导体装置电性连接至该图案化导电层；
敷设一模塑材料以形成覆盖该电性互连件的该上表面及该第一导体装置的一模造结构；
于该模造结构中形成一第一开口，该第一开口为毗邻于该模造结构的一上表面且外露该电性互连件的该上表面，其中从该电性互连件的该上表面至该电性互连件的该下表面间的一第一距离，大于从该互连结构的该上表面至该互连结构的该下表面间的一第二距离；以及
形成一第一连接组件，电性连接至该电性互连件且填满该第一开口。
15.如权利要求14所述的方法，其中，形成该互连结构包括：
形成一第一层状物，包括：(a)一下表面，设置成毗邻于该图案化导电层；及(b)一上表面，相对于该第一层状物的该下表面；以及
形成一第二开口，自该第一层状物的该上表面延伸至该第一层状物的该下表面，其中该第二开口外露该图案化导电层的该上表面；
其中，该第一层状物包括一介电材料或一防焊阻剂材料。
16.如权利要求15所述的方法，其中，形成该电性互连件包括：
将一光阻材料敷设于该第一层状物的该上表面，以毗邻于该第一层状物形成一光阻层；
图案化该光阻层，以定义一第三开口，该第三开口外露该图案化导电层的该上表面；
将一导电材料敷设进该光阻层中的该第三开口内以及敷设进该第一层状物中的该第二开口内，以形成该电性互连件；以及
去除该光阻层；
其中，该光阻层的该上表面定义一第一平面，该第一平面位于一第二平面之上，该第二平面由该电性互连件的该上表面所定义。
17.如权利要求14所述的方法，其中，于该模造结构中形成该第一开口包括以激光钻孔移除毗邻于该模造结构的该上表面的该模造结构的一部分。
18.如权利要求14所述的方法，进一步包括：经由结合该第一连接组件及电性连接至一第二半导体装置的一第二连接组件而形成一经熔化的导电凸块，其中该第一连接组件突出于由该模造结构的该上表面所定义的一第三平面。
19.如权利要求14所述的方法，其中：
该第一开口的一第一高度大于该电性互连件的一第二高度；以及该第一高度小于等于400微米。
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