CN101488555A - Manufacturing method for low power consumption phase changing memory - Google Patents

Abstract

The invention relates to a method for preparing a chalcogenide compound storage unit device by depositing a nano-conical bottom electrode using FIB, which includes the following steps: first, on a (100)-oriented silicon wafer, a layer of Si _x is prepared by chemical vapor deposition N dielectric layer; then use magnetron sputtering to deposit Al/Ti/TiN as the bottom electrode material; use ion beam method to deposit silicon oxide as the dielectric layer on the bottom electrode material; use electron beam exposure combined with reactive ion etching method Prepare a number of silicon oxide holes; use the focused ion beam system to prepare the required conical bottom electrode in the silicon oxide hole; use the photolithographic stripping method to deposit a phase change material layer on the bottom electrode; then use the focused ion beam to extract the upper test electrode ; Finally, ion beam deposition sputtered silicon oxide as a heat insulating protective layer. The invention helps to prepare a novel low-power phase-change memory, provides an effective method for studying the performance of the phase-change memory with a size below 20nm, and promotes the development of the phase-change memory.

Description

A kind of preparation method of low power consumption phase change memory

technical field

The invention relates to a preparation method of a phase-change memory with a new electrode structure, which belongs to the field of microelectronics.

Background technique

Chalcogenide random access memory is developed based on the idea that chalcogenide thin films can be applied to phase-change storage media proposed by S.R. Ovshinsky in the late 1960s and early 1970s. In 2001, Intel first reported 4MB of C-RAM, and by the end of 2006, Samsung had reported 512MB of C-RAM. At present, the mainstream non-volatile memory is mainly flash memory. However, according to Moore's law, when the existing memory cell design is below 45nm, it is difficult to maintain its non-volatile characteristics. Since phase change memory does not need to erase the original data when writing new data, its data writing speed can reach tens to hundreds of times that of traditional flash memory, while its power consumption is less than half of that of flash memory, and its size is also smaller than that of flash memory. Much smaller; and the durability of phase change memory is excellent, and the service life is much longer than that of traditional flash memory. Based on these factors, the industry generally believes that below 45nm, phase-change memory will replace flash as the mainstream non-volatile memory. At present, companies such as Ovonyx, Intel, Samsung, STMicroelectronics, Infineon, Elpida, Philips, and IBM are conducting research on phase change memory in the world, and their direction is developing towards high speed, high density, and low power consumption. The focus of their attention is on how to realize the commercialization of phase change memory as soon as possible, in which the reduction of power consumption of the device is very critical and important, because the phase change process of the phase change memory device unit ultimately depends on metal complementary oxide semiconductor transistors. In order to achieve the power matching with the CMOS tube in the high-density memory chip, it is necessary to reduce the power consumption of the device. The methods to reduce the power consumption of the device include: reducing the contact area between the electrode and the phase change material; increasing the resistance of the phase change material; adding a thermal resistance layer between the electrode and the phase change material or inside the phase change material, etc. Reducing the contact area between the electrodes and the phase-change material can effectively reduce the volume of the phase-change material, thereby reducing power consumption, which is the starting point of the present invention.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for preparing a low-power phase-change memory. Reducing the contact area between the electrodes and the phase-change material can effectively reduce the volume of the phase-change material, thereby reducing power consumption.

In order to solve the above-mentioned technical problems, the present invention adopts the following technical scheme: a method for preparing a low-power phase-change memory, which mainly includes the following steps:

1) preparing a layer of _Six N dielectric layer on the silicon wafer substrate;

2) preparing a bottom electrode material layer on the _Six N dielectric layer;

3) preparing a silicon oxide dielectric layer on the bottom electrode material layer;

4) preparing silicon oxide holes on the silicon oxide dielectric layer;

5) Using focused ion beam to deposit metal in silicon oxide pores to prepare conical bottom electrodes;

6) Depositing a phase change material layer on the conical bottom electrode;

7) Lead out the upper test electrode on the phase change material layer.

As one of the preferred solutions of the present invention, in step 5) in the silicon oxide hole, a conical bottom electrode is prepared by using focused ion beam deposition metal, and the metal includes one of platinum, tungsten, titanium, gold, titanium nitride, and tungsten titanium. species or several.

As one of the preferred solutions of the present invention, the thickness of the _Six N dielectric layer is 300-500 nm.

As one of the preferred solutions of the present invention, the bottom electrode material layer is the bottom electrode Al/Ti/TiN formed by magnetron sputtering, and its corresponding thickness is 150nm/100nm/50nm.

As one of the preferred solutions of the present invention, the preparation of the silicon oxide holes is completed by electron beam exposure combined with reactive ion etching, the diameter of the silicon oxide holes is 40-60 nm, and the depth of the holes is greater than the thickness of the silicon oxide dielectric layer. .

As one of the preferred solutions of the present invention, the diameter of the bottom of the conical bottom electrode is 40-60 nm, and the height of the conical bottom electrode is higher than the height of the silicon oxide pores.

As one of the preferred solutions of the present invention, the deposition of the phase change material is completed by magnetron sputtering combined with stripping, that is, after the phase change material is deposited by magnetron sputtering, the photoresist and the phase change material deposited on it are soaked in acetone remove.

As one of the preferred solutions of the present invention, the upper test electrode is extracted by focused ion beam deposition of platinum, the line width of the extraction electrode is controlled to be below 100nm, and the electrode thickness is 80nm.

As one of the preferred solutions of the present invention, the method further includes depositing silicon oxide on the upper test electrode by means of ion beam deposition to prepare a top thermal insulation protection layer, and the thickness of the silicon oxide is 200nm.

As one of the preferred solutions of the present invention, the silicon wafer is cleaned before preparing the _Six N dielectric layer. The specific steps are as follows: the first solution is prepared by using ammonia water: hydrogen peroxide: deionized water with a mixing ratio of 1:2:5, and the silicon wafer is Put it into the first solution for cleaning; use hydrochloric acid: hydrogen peroxide: deionized water with a mixing ratio of 1:2:5 to configure the second solution, put the silicon wafer into the second solution for cleaning; finally bake the silicon wafer in an oven to remove it surface moisture.

The present invention utilizes a focused ion beam system to deposit a platinum electrode. The shape of the electrode is conical, and the size of the bottom is as large as 40-60 nm (diameter). The size of the top of the electrode in contact with the phase change material is very small, below 20 nm. The main advantages are that, firstly, the contact area between the electrode and the phase change material can be fully reduced to less than 20nm; secondly, the relatively large size of the bottom of the electrode and the large contact area with the bottom electrode material can ensure that the gap between the electrode layer materials at the bottom is relatively large during device operation. No detachment; third, because the electrodes are tapered, there is a relatively large contact area (compared with vertical electrodes) when depositing phase change materials, which makes the growth of phase change materials easier.

Description of drawings

Fig. 1 is the schematic diagram of preparing one deck _Six N dielectric layer on silicon chip substrate among the present invention;

Fig. 2 is the schematic diagram of preparing the bottom electrode material layer on the _Six N dielectric layer in the present invention;

Fig. 3 is a schematic diagram of preparing a silicon oxide dielectric layer on the bottom electrode material layer in the present invention;

Fig. 4 is a schematic diagram of preparing silicon oxide holes on a silicon oxide dielectric layer in the present invention;

Fig. 5 is a schematic diagram of provisioning a mark graphics layer in the present invention;

Fig. 6 is a schematic diagram of preparing a conical bottom electrode by using focused ion beam deposition of platinum in a silicon oxide hole in the present invention;

7 is a schematic diagram of depositing a phase-change material layer on the bottom electrode in the present invention;

Fig. 8 is a schematic diagram of drawing out the upper test electrode on the phase change material layer in the present invention.

Detailed ways

Further illustrate the specific implementation steps of the present invention below in conjunction with accompanying drawing:

Silicon wafer substrate cleaning. Silicon wafer cleaning: first solution: ammonia water: hydrogen peroxide: deionized water = 1:2:5, put the silicon wafer into the first solution and boil for 5 minutes, cool, rinse with deionized water for 3 minutes, and then blow dry with nitrogen. The main function is to remove oil and large particles on the silicon surface. The second solution: hydrochloric acid: hydrogen peroxide: deionized water = 1:2:5, put the silicon chip into the second solution for cleaning, the method is the same as that of the first solution, the main function is to remove the metal ions on the surface of the silicon chip, and finally put The silicon wafers were baked in an oven at 120°C for 30 minutes to remove surface moisture.

As shown in Figure 1, the preparation of the _Six N dielectric layer. A layer of _Six N with a thickness of 300-500 nm is deposited on the previously treated and cleaned silicon wafer by chemical vapor deposition.

As shown in Figure 2, the preparation of the bottom electrode material layer. The bottom electrode Al/Ti/TiN is formed by magnetron sputtering, and its corresponding thickness is controlled to be 150nm/100nm/50nm.

As shown in FIG. 3 , a silicon oxide dielectric layer is prepared on the bottom electrode material layer. The silicon oxide dielectric layer is prepared by ion beam deposition, and the thickness of the silicon oxide is controlled to be 100nm.

As shown in FIG. 4 , the silicon oxide holes on the silicon oxide dielectric layer are prepared. Electron beam positive resist is spin-coated, and the thickness of the resist is controlled to 150nm. Electron beam lithography is performed to form photoresist holes of 50nm, and reactive ion etching is used to transfer patterns to the silicon oxide layer. The depth of the silicon oxide holes is determined by The thickness of the silicon oxide layer is at least 100-120nm to be etched in order to ensure the complete removal of the silicon oxide in the holes. In actual operation, it can be properly over-etched to ensure the complete removal of the silicon oxide in the holes.

As shown in Figure 5, mark the preparation of the graphics layer. The marking pattern layer was prepared by depositing platinum by focused ion beam. The shape of the marking pattern is composed of a cross and four connected squares; the line width of the cross is 200nm and the length is 2μm; the size of the square is a square with a length of 1μm; the thickness of the marking layer is 200nm.

As shown in Figure 6, the preparation of the conical bottom electrode. Platinum electrodes are deposited using a focused ion beam. The diameter of the bottom of the electrode is controlled to be less than 60nm, preferably 50nm, the size of the top is controlled to be less than 20nm, and the height of the electrode is at least 100nm.

As shown in Figure 7, the phase change material layer is prepared. The phase change material was deposited by magnetron sputtering combined with stripping. Spin-coat positive double-layer electron beam resist, the thickness is controlled to 300nm, carefully and accurately perform the alignment procedure, and then electron lithography forms the deposition area of the phase change material, the area size is 2×2μm; magnetron sputtering deposition thickness For a 100nm phase change material, soak in acetone for 12 hours to strip off the photoresist and the phase change material deposited on it.

As shown in Figure 8, the lead-out of the upper test electrode. Deposition of the upper test electrode was accomplished using focused ion beam deposition of platinum material. The line width of the electrode is controlled below 100nm, and the thickness of the electrode material is 100nm.

Prepare the top thermal insulation protection layer, and deposit silicon oxide on the top layer as the top thermal insulation protection layer, which is completed by ion beam deposition. The thickness of silicon oxide is controlled to be 200nm.

In this paper, a focused ion beam system is used to deposit a platinum electrode. The shape of the electrode is conical, and the size of the bottom is 40-60nm (diameter). The top of the electrode in contact with the phase change material is very small, below 20nm. The main advantages are that, firstly, the contact area between the electrode and the phase change material can be fully reduced to less than 20nm; secondly, the relatively large size of the bottom of the electrode and the large contact area with the bottom electrode material can ensure that the gap between the electrode layer materials at the bottom is relatively large during device operation. No detachment; third, because the electrodes are tapered, there is a relatively large contact area (compared with vertical electrodes) when depositing phase change materials, which makes the growth of phase change materials easier.

The above embodiments are only used to illustrate but not limit the technical solution of the present invention. Any technical solutions that do not deviate from the spirit and scope of the present invention shall be included in the patent application scope of the present invention.

Claims (10)

1. the preparation method of a low power consumption phase changing memory is characterized in that, this method mainly may further comprise the steps:

1) preparation one deck Si on silicon chip substrate _xThe N dielectric layer;

2) at Si _xPreparation bottom electrode material layer on the N dielectric layer;

3) preparation silica medium layer on the bottom electrode material layer;

4) preparation silica hole on the silica medium layer;

5) in the silica hole, utilize the focused ion beam deposition metal to prepare cone bottom electrode;

6) sediment phase change material layer on cone bottom electrode;

7) on phase-change material layers, draw the upper strata test electrode.

2. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1, it is characterized in that: utilize the focused ion beam deposition metal to prepare cone bottom electrode in the step 5) in the silica hole, this metal comprises one or more in platinum, tungsten, titanium, gold, titanium nitride, the tungsten titanium.

3. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1 is characterized in that: the Si in the described step 1) _xN dielectric layer, its thickness are 300～500nm.

4. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1 is characterized in that: described bottom electrode material layer is the bottom electrode Al/Ti/TiN that the method with magnetron sputtering forms, and its corresponding thickness is 150nm/100nm/50nm.

5. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1, it is characterized in that: the preparation in described silica hole utilizes the ion etching of electron beam exposure association reaction to finish, the diameter in silica hole is 40～60nm, and the degree of depth in hole is greater than the thickness of silica medium layer.

6. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1, it is characterized in that: described cone bottom electrode base diameter is 40～60nm, and the cone bottom electrode height is higher than the height in silica hole.

7. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1, it is characterized in that: the deposition of described phase-change material utilizes magnetron sputtering to finish in conjunction with peeling off, and promptly adopts acetone to soak behind the magnetron sputtering deposition phase-change material photoresist and the phase-change material that deposits above thereof are removed.

8. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1, it is characterized in that: described upper strata test electrode utilizes focused ion beam deposition platinum to draw, and the live width of extraction electrode is controlled to be below the 100nm, and thickness of electrode is 80nm.

9. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1; it is characterized in that: this method further is included in utilizes ion beam depositing method cvd silicon oxide to prepare the top layer heat-insulating protective layer on the test electrode of upper strata, the thickness of silica is 200nm.

10. the preparation method of a kind of low power consumption phase changing memory as claimed in claim 1 is characterized in that: at preparation Si _xFirst cleaning silicon chip before the N dielectric layer, concrete steps are as follows: adopt ammoniacal liquor: hydrogen peroxide: the deionized water mixed proportion is that 1:2:5 disposes first solution, silicon chip is put into first solution clean; Adopt hydrochloric acid: hydrogen peroxide: the deionized water mixed proportion is that 1:2:5 disposes second solution, silicon chip is put into second solution clean; At last silicon chip is toasted the moisture of removing the surface in baking oven.

Images