CN114937738B - A three-dimensional phase change memory based on vertical electrodes and preparation method thereof - Google Patents

Abstract

The present invention discloses a three-dimensional phase change memory based on vertical electrodes and a preparation method thereof. The three-dimensional phase change memory comprises: a first silicon dioxide layer, a first word line electrode layer, a second silicon dioxide layer, a second word line electrode layer, a third silicon dioxide layer, a third word line electrode layer, a fourth silicon dioxide layer and a fifth silicon dioxide layer arranged in sequence from bottom to top, a first through-hole vertically arranged in the fifth silicon dioxide layer, a second through-hole vertically arranged and a bit line electrode; the bit line electrode extends to the surface of the phase change memory structure through the first through-hole. In the present invention, since all memory cells in the same vertical direction share the same bit line electrode, the word line electrode of each memory cell is in the horizontal direction, and the functional layer of each memory cell is the functional layer portion directly facing the shared bit line electrode and the corresponding word line electrode, the functional layer only needs to be deposited once by increasing the number of layers of the word line electrode layer and the isolation layer, thereby reducing the process complexity.

Description

A three-dimensional phase change memory based on vertical electrodes and preparation method thereof

Technical Field

The present invention belongs to the field of memory, and in particular relates to a three-dimensional phase change memory based on vertical electrodes and a preparation method thereof.

Background technique

Phase change memory (PCM) as a non-volatile memory is expected to replace flash memory and become one of the next generation mainstream storage technologies. In order to improve storage density and cost competitiveness, three-dimensional phase change memory (3D PCM) using three-dimensional stacking has attracted widespread attention in the industry. The 3D PCM solution proposed by Intel and others mainly adopts a three-dimensional horizontal stacking method based on a cross-point structure, that is, each storage unit and the upper and lower adjacent word lines and bit lines are arranged horizontally, so this method is also called a horizontal stacking structure. This method has a simple structure and is easy to implement, but when the number of stacking layers is large, the number of photolithography and etching times is too many, which will lead to excessive costs. At the same time, the surface unevenness problem and sidewall coverage problem are gradually aggravated. In addition, there is an inevitable limit to the number of stacking layers due to process constraints, and the prominent thermal crosstalk problem of PCM also limits the further improvement of storage density. Therefore, it is necessary to propose a new three-dimensional phase change memory structure and preparation method.

Summary of the invention

In view of the defects of the prior art, the purpose of the present invention is to provide a three-dimensional phase change memory based on vertical electrodes and a preparation method, aiming to solve the problems in the prior art that the three-dimensional phase change memory adopts a horizontal stacking structure, which leads to complex structure, high process difficulty and thermal crosstalk when the number of stacking layers is large.

The present invention provides a three-dimensional phase change memory based on vertical electrodes, the three-dimensional phase change memory comprising: a first silicon dioxide layer, a first word line electrode layer, a second silicon dioxide layer, a second word line electrode layer, a third silicon dioxide layer, a third word line electrode layer, a fourth silicon dioxide layer and a fifth silicon dioxide layer arranged in sequence from bottom to top, a first through-hole vertically arranged at the center of the fifth silicon dioxide layer, a second through-hole vertically arranged at the center of a combination consisting of the first word line electrode layer, the second silicon dioxide layer, the second word line electrode layer, the third silicon dioxide layer, the third word line electrode layer and the fourth silicon dioxide layer, and a bit line electrode; the bit line electrode extends to the surface of the three-dimensional phase change memory structure through the first through-hole.

Furthermore, the second through hole is filled with multiple layers of material in a sleeve shape, including the first carbon layer, phase change unit layer, second carbon layer, gate tube layer and third carbon layer from outside to inside, and the first carbon layer is tightly connected to the inner wall of the second through hole.

Furthermore, the first word line electrode layer and the second silicon dioxide layer are periodically repeated in the vertical direction as required, and the number of repetitions is the same as the number of memory cell layers required by the three-dimensional phase change memory.

Furthermore, all memory cells in the same vertical direction share the same bit line electrode.

Furthermore, the word line electrode of each memory cell is arranged in the horizontal direction, and the phase change unit layer and the gate tube layer in each memory cell are functional layer parts directly facing the common bit line electrode and the corresponding word line electrode.

The present invention also provides a method for preparing the three-dimensional phase change memory, comprising the following steps:

(1) growing a bottom electrode metal material on a silicon substrate using magnetron sputtering;

(2) growing SiO ₂ on the bottom electrode metal prepared in step (1) using PECVD;

(3) Alternating the growth of bottom electrode metal material and SiO ₂ by repeating steps (1) and (2) until the desired number of layers is reached;

(4) using ultraviolet light to form a columnar hole structure on the wafer prepared in step (3) and to etch through holes, and then peeling off the photoresist;

(5) A purple-coated hole-shaped upper electrode is formed on the columnar hole structure prepared in step (4), and only the photoresist is developed without stripping the photoresist temporarily. The columnar hole structure prepared in step (4) is located in the center of the square hole upper electrode;

(6) using magnetron sputtering to sequentially deposit a carbon layer, a phase change unit layer, a carbon layer, a gate tube layer, a carbon layer, and an upper electrode layer;

(7) stripping the photoresist spin-coated in step (5);

(8) Performing ultraviolet photolithography and etching a groove to expose the topmost bottom electrode metal;

(9) Repeat step (8) and repeat the same number of times as step (3), each etching depth is deeper than the previous one and the groove position is closer to the edge of the upper electrode than the previous one, exposing all the bottom electrode metals in turn.

The columnar hole structure is a square hole structure or a circular hole structure, and the hole-shaped upper electrode is a square hole or a circular hole.

Furthermore, when the carbon layer, phase change unit layer, carbon layer, gate tube layer, carbon layer and electrode layer are sequentially deposited by magnetron sputtering, it is necessary to start for a period of time and stop for a period of time in order to prevent excessive energy from damaging the photoresist.

Through the above technical solution conceived by the present invention, compared with the prior art, the beneficial effects of the present invention are:

(1) In the three-dimensional phase change memory structure provided by the present invention, since all the memory cells in the same vertical direction share the same bit line electrode, the word line electrode of each memory cell is in the horizontal direction, and the functional layer (phase change unit and gate tube unit) of each memory cell is the functional layer part directly opposite to the common bit line electrode and the corresponding word line electrode, when realizing the three-dimensional phase change memory, it is only necessary to increase the number of word line electrode layers and isolation layers, and the functional layer (phase change unit and gate tube unit) only needs to be deposited once, thereby reducing the process complexity of the three-dimensional phase change memory.

(2) The three-dimensional phase change memory structure proposed by the present invention can increase the number of storage unit layers of the three-dimensional phase change memory simply by increasing the number of word line electrode layers and isolation layers.

(3) In the three-dimensional phase change memory structure proposed in the present invention, when operating the memory cell, the current flows in the horizontal direction, so the heat distribution is more concentrated in the horizontal direction, and the heat distribution in the vertical direction is less, thereby reducing the thermal crosstalk problem between the cells, effectively suppressing the thermal crosstalk problem between adjacent memory cells, and improving the data reliability of the three-dimensional phase change memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a structural diagram of a three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention;

2 is a flowchart of preparing a three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention;

3 is a diagram showing the resistance characteristics of the first layer of a three-layer three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention;

4 is a diagram showing the resistance characteristics of the second layer of a three-layer three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention;

5 is a diagram showing the resistance characteristics of the third layer of a three-layer three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention;

6 is a structural diagram of a three-layer 3D PCM based on a horizontal stacking structure provided by an embodiment of the present invention;

7 is a graph showing the variation of the temperature Tpcm and the crystal fraction (θpcm) of an unselected cell adjacent to a selected memory cell in a three-layer 3D PCM structure based on a horizontal stacking structure according to an embodiment of the present invention over time;

FIG. 8 is a thermal crosstalk simulation diagram of a three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention.

In the figure: 1 is the first silicon dioxide layer, 2 is the first word line electrode layer, 3 is the second silicon dioxide layer, 4 is the second word line electrode layer, 5 is the third silicon dioxide layer, 6 is the third word line electrode layer, 7 is the fourth silicon dioxide layer, 8 is the fifth silicon dioxide layer, 9 is the bit line electrode, 10 is the third carbon layer, 11 is the gate tube layer, 12 is the second carbon layer, 13 is the phase change unit layer, and 14 is the first carbon layer.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

FIG1 is a structural diagram of a three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention. The bottom layer is a first silicon dioxide layer 1. Above the first silicon dioxide layer 1 is a combination of a first word line electrode layer 2 and a second silicon dioxide layer 3 that are repeatedly grown in sequence. The three-dimensional phase change memory needs as many layers of storage cells as it needs to grow repeatedly. There is a second through hole inside the combination. The second through hole is filled with multiple layers of materials in a sleeve shape. From the outside to the inside, there are a first carbon layer 14, a phase change unit layer 13, a second carbon layer 12, a gate tube layer 11, a third carbon layer 10, and a bit line electrode 9. The layers of material are tightly adhered together, and the first carbon layer 14 is tightly connected to the inner wall of the second through hole. There is a fifth silicon dioxide layer 8 above the combination. There is a first through hole in the fifth silicon dioxide layer 8. The bit line electrode 9 extends to the surface of the structure through the first through hole in the fifth silicon dioxide layer 8.

The three-dimensional phase change memory based on vertical electrodes provided by the embodiment of the present invention comprises a first silicon dioxide layer 1, a first word line electrode layer 2, a second silicon dioxide layer 3, a second word line electrode layer 4, a third silicon dioxide layer 5, a third word line electrode layer 6, a fourth silicon dioxide layer 7, a fifth silicon dioxide layer 8, a bit line electrode 9, a third carbon layer 10, a gate tube layer 11, a second carbon layer 12, a phase change unit layer 13, and a first carbon layer 14. The first word line electrode layer 2 is located above the first silicon dioxide layer 1, the second silicon dioxide layer 3 is located above the first word line electrode layer 2, the second silicon dioxide layer 3 is located above the second word line electrode layer 4, the third silicon dioxide layer 5 is located above the second word line electrode layer 4, the third silicon dioxide layer 6 is located above the third silicon dioxide layer 5, and the third word line electrode layer 6 is located above the third word line electrode layer 6. A fourth silicon dioxide layer 7 is located above the line electrode layer 6, and a fifth silicon dioxide layer 8 is located above the fourth silicon dioxide layer 7. A first through-hole exists in the fifth silicon dioxide layer 8. A second through-hole exists in the combination of the first word line electrode layer 2, the second silicon dioxide layer 3, the second word line electrode layer 4, the third silicon dioxide layer 5, the third word line electrode layer 6, and the fourth silicon dioxide layer 7. The second through-hole is filled with multiple layers of material in a sleeve shape, which are, from outside to inside, the first carbon layer 14, the phase change unit layer 13, the second carbon layer 12, the gate tube layer 11, the third carbon layer 10, and the bit line electrode 9. The first carbon layer 14 is tightly connected to the inner wall of the second through-hole, and the bit line electrode 9 extends to the surface of the structure through the first through-hole of the fifth silicon dioxide layer 8.

The first word line electrode layer 2 and the second silicon dioxide layer 3 can be repeated periodically in the vertical direction as needed, and the number of repetitions is the same as the number of memory cell layers required by the three-dimensional phase change memory.

In the prior art of three-dimensional phase change memory, each memory cell is composed of a phase change unit and a gate tube unit connected in series, and each memory cell is at the intersection of a word line and a bit line, so when the memory cell is operated, the current flows through the memory cell in the vertical direction, and the heat mainly diffuses in the vertical direction, causing thermal crosstalk to the adjacent memory cells in the vertical direction. The phase change memory provided by the present invention is based on a vertical electrode structure, and all memory cells in the same vertical direction share the same bit line electrode, and the word line electrode of each memory cell is in the horizontal direction. The functional layer (phase change unit and gate tube unit) of each memory cell is the functional layer part that is directly opposite to the common bit line electrode and the corresponding word line electrode. The current flows through the memory cell in the horizontal direction, and the heat mainly diffuses in the horizontal direction, so no thermal crosstalk is generated to the adjacent memory cells in the vertical direction. In addition, the phase change memory provided by the present invention only needs to deposit the functional layer (phase change unit and gate tube unit) once, which greatly simplifies the process and greatly improves the manufacturing cost of the three-dimensional phase change memory.

FIG. 2 shows a method for preparing a three-dimensional phase change memory based on vertical electrodes provided by an embodiment of the present invention, which specifically includes the following steps:

(1) First, a bottom electrode metal material is grown on a silicon substrate by magnetron sputtering;

(2) growing SiO ₂ on the bottom electrode metal material prepared in step (1) using PECVD;

(3) Repeat the above two steps to alternately grow the bottom electrode and SiO ₂ until the target number of layers is reached;

(4) A columnar hole structure is formed on the structure prepared in the above steps by ultraviolet etching and a through hole is formed. The etching limit is to ensure that the bottom electrode material is etched away. Slight overetching may occur, and then the photoresist is stripped off. The columnar hole may be a square hole or a circular hole.

(5) purple coat engraving the hole-shaped electrode again and ensuring that the columnar hole structure prepared in step (4) is in the center of the square hole, and then developing without removing the glue temporarily; the hole-shaped electrode can be a square hole electrode or a circular hole electrode;

(6) Magnetron sputtering the carbon layer, phase change unit layer, carbon layer, gate tube layer, carbon layer, and upper electrode layer in sequence. During sputtering, in order to prevent excessive energy from damaging the photoresist, a 100-second on-off and 100-second on-off method is adopted. Then the photoresist spin-coated in step (5) is stripped off;

(7) UV photolithography is performed in the area of the square hole electrode near the columnar hole structure to etch a groove so that the topmost bottom electrode metal is exposed;

(8) Repeat step (7) and repeat the same number of times as step (3), each etching depth is deeper than the previous one, and the groove position is closer to the edge of the upper electrode than the previous one, so that all the bottom electrode metals are exposed in turn.

In the prior art of three-dimensional phase change memory preparation process, each time a layer of storage unit is prepared, a hole structure needs to be overlaid and etched out and a functional layer (phase change unit and gate tube unit) needs to be filled in the hole structure. In the phase change memory preparation method provided by the present invention, it is only necessary to deposit all the word line electrode layers and the isolation layer, then photolithograph and etch the hole structure once and fill the functional layer in the hole structure, which greatly simplifies the complexity of the preparation process and improves the yield of the three-dimensional phase change memory preparation.

In order to further illustrate the three-dimensional phase change memory based on vertical electrodes and the preparation method thereof provided by the embodiments of the present invention, the following is further described in detail in conjunction with the preferred embodiments:

Embodiment 1:

The three-layer vertical electrode-based three-dimensional phase change memory is prepared as follows:

(1) Grow 50 nm of metal W on a silicon substrate using magnetron sputtering;

(2) using PECVD to grow 100 nm of SiO ₂ on the tungsten electrode prepared in step (1);

(3) Repeat steps (1) and (2) twice to obtain 6 layers of alternately grown metal W and SiO ₂ ;

(4) Using ultraviolet light to etch out a cylindrical hole structure and a through hole, the bottom metal tungsten is etched through, resulting in a slight overetching, and then the photoresist is stripped off;

(5) purple coat engraving the square hole electrode again and ensure that the cylindrical hole structure prepared in step (4) is in the center of the square hole, and then develop without removing the glue temporarily;

(6) Magnetron sputtering of 10nmC, 70nmGST225, 10nmC, _30nmGeTe6 , 10nmC, 50nmW in sequence, with a 100s on, 100s off method. Then stripping the photoresist spin-coated in step (5);

(7) UV photolithography is performed in the area of the square hole electrode near the columnar hole structure to etch a groove so that the topmost bottom electrode metal is exposed;

(8) Repeat step (7) and repeat the same number of times as step (3), each etching depth is deeper than the previous one, and the groove position is closer to the edge of the upper electrode than the previous one, so that all the bottom electrode metals are exposed in turn.

After the above steps, the preparation of a three-layer three-dimensional phase change memory based on vertical electrodes can be completed. SET electric pulses and RESET electric pulses are applied to the three-layer units for testing. The resistance characteristics of the first layer unit are shown in Figure 3, the resistance characteristics of the second layer unit are shown in Figure 4, and the resistance characteristics of the third layer unit are shown in Figure 5. It can be seen that the three-layer units under the vertical electrode stacking structure all show certain high and low resistance characteristics, and have a certain cyclic repeatability. Therefore, this structure has the potential to achieve higher storage density, and tries to avoid the problems of inaccurate precision and high cost caused by multiple overlay.

The three-dimensional phase change memory structure obtained by the above preparation method only needs to deposit the phase change unit and the gate tube material once, which reduces the process complexity of the three-dimensional phase change memory. At the same time, the number of storage unit layers of the three-dimensional phase change memory can be increased by simply increasing the number of word line electrode layers and isolation layers. In addition, it can effectively suppress the thermal crosstalk problem between adjacent storage cells and improve the data reliability of the three-dimensional phase change memory.

FIG6 is a 3D PCM based on a horizontal stacking structure proposed by Intel and others. In this structure, when a SET operation is performed on a selected cell, the heat generated by the selected cell will diffuse to the unselected cell, resulting in thermal crosstalk. FIG7 shows the change in the temperature T _pcm and the crystal fraction (θ _pcm ) of the unselected cell adjacent to the selected storage cell over time. It can be seen that since the PCM only needs to be heated to above 400K to become a crystalline state, the heat dissipated from the selected cell can cause the third-layer cell PCM to heat up to a partial area exceeding 400K, achieving a certain amount (about 25%) of crystallization, which means that the cell resistance will be reduced and the "0" state cannot be maintained well.

Figure 8 is a simulation diagram of thermal crosstalk of a three-dimensional phase change memory based on vertical electrodes. For the selected area, the crystallization transition fraction is 97.863% calculated by probe integration. It can be considered that the selected area has completely undergone a transition from amorphous to crystalline state. The data "1" is written into the storage unit. The temperature change does not cause the first and third layers of unselected units to undergo phase change. In other words, during the application of the SET pulse voltage, the unselected area PCM is still in an amorphous high-resistance state. This is because the direction of the voltage and current applied under the vertical electrode structure is horizontal, so the diffusion of heat in the horizontal direction is much higher than that in the vertical direction. In summary, for the vertical electrode stacking structure, the selected unit can perfectly reproduce the crystallization transition process of the SET operation, and the influence of thermal crosstalk on the unselected unit is negligible.

It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A three-dimensional phase change memory based on vertical electrodes, characterized in that the three-dimensional phase change memory comprises: a first silicon dioxide layer (1), a first word line electrode layer (2), a second silicon dioxide layer (3), a second word line electrode layer (4), a third silicon dioxide layer (5), a third word line electrode layer (6), a fourth silicon dioxide layer (7) and a fifth silicon dioxide layer (8) arranged in sequence from bottom to top, a first through-hole vertically arranged at the center of the fifth silicon dioxide layer (8), a second through-hole vertically arranged at the center of a combination consisting of the first word line electrode layer (2), the second silicon dioxide layer (3), the second word line electrode layer (4), the third silicon dioxide layer (5), the third word line electrode layer (6) and the fourth silicon dioxide layer (7), and a bit line electrode (9); the bit line electrode (9) extends to the surface of the three-dimensional phase change memory structure through the first through-hole. 2. The three-dimensional phase change memory according to claim 1 is characterized in that the second through-hole is filled with multiple layers of material in a sleeve shape, which are, from the outside to the inside, a first carbon layer (14), a phase change unit layer (13), a second carbon layer (12), a gate tube layer (11) and a third carbon layer (10), and the first carbon layer (14) is tightly connected to the inner wall of the second through-hole. 3. The three-dimensional phase change memory according to claim 1 or 2, characterized in that the first word line electrode layer (2) and the second silicon dioxide layer (3) are periodically repeated in the vertical direction as required, and the number of repetitions is the same as the number of storage unit layers required by the three-dimensional phase change memory. 4 . The three-dimensional phase change memory according to claim 3 , wherein all memory cells in the same vertical direction share the same bit line electrode. 5. The three-dimensional phase change memory as described in claim 3 or 4 is characterized in that the word line electrode of each memory cell is arranged in the horizontal direction, and the phase change unit layer (13) and the gate tube layer (11) in each memory cell are functional layer parts that are directly opposite to the common bit line electrode and the corresponding word line electrode. 6. A method for preparing a three-dimensional phase change memory according to any one of claims 1 to 5, characterized in that it comprises the following steps: (1) growing a bottom electrode metal material on a silicon substrate using magnetron sputtering; (2) growing SiO ₂ on the bottom electrode metal prepared in step (1) using PECVD; (3) Alternating the growth of bottom electrode metal material and SiO ₂ by repeating steps (1) and (2) until the desired number of layers is reached; (4) using ultraviolet light to form a columnar hole structure on the wafer prepared in step (3) and to etch through holes, and then peeling off the photoresist; (5) A purple-coated hole-shaped upper electrode is formed on the columnar hole structure prepared in step (4), and only the photoresist is developed without stripping the photoresist temporarily. The columnar hole structure prepared in step (4) is located in the center of the square hole upper electrode; (6) using magnetron sputtering to sequentially deposit a carbon layer, a phase change unit layer, a carbon layer, a gate tube layer, a carbon layer, and an upper electrode layer; (7) stripping the photoresist spin-coated in step (5); (8) Performing ultraviolet photolithography and etching a groove to expose the topmost bottom electrode metal; (9) Repeat step (8) and repeat the same number of times as step (3), each etching depth is deeper than the previous one and the groove position is closer to the edge of the upper electrode than the previous one, exposing all the bottom electrode metals in turn. 7. The preparation method according to claim 6, characterized in that the columnar pore structure is a square pore structure or a circular pore structure. 8. The preparation method according to claim 6, characterized in that the hole-shaped upper electrode is a square hole or a round hole. 9. The preparation method according to any one of claims 6 to 8, characterized in that when the carbon layer, phase change unit layer, carbon layer, gate tube layer, carbon layer and electrode layer are sequentially deposited by magnetron sputtering, in order to prevent excessive energy from damaging the photoresist, it is necessary to do it for a period of time and stop for a period of time.