CN105489755B - Vertical stratification limits the autoregistration preparation method of phase transition storage entirely - Google Patents
Vertical stratification limits the autoregistration preparation method of phase transition storage entirely Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 34
- 230000007704 transition Effects 0.000 title claims abstract description 16
- 238000003860 storage Methods 0.000 title claims description 20
- 238000013517 stratification Methods 0.000 title claims 11
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000012782 phase change material Substances 0.000 claims abstract description 46
- 230000008569 process Effects 0.000 claims abstract description 17
- 239000011810 insulating material Substances 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 238000012360 testing method Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 239000012670 alkaline solution Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 239000012774 insulation material Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 238000000354 decomposition reaction Methods 0.000 claims description 4
- 230000009466 transformation Effects 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 229910000618 GeSbTe Inorganic materials 0.000 claims description 2
- 229920001486 SU-8 photoresist Polymers 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 238000010894 electron beam technology Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 238000010884 ion-beam technique Methods 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 2
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000004807 localization Effects 0.000 claims 4
- 239000010409 thin film Substances 0.000 claims 4
- 238000005485 electric heating Methods 0.000 claims 2
- 230000005611 electricity Effects 0.000 claims 2
- 238000002161 passivation Methods 0.000 claims 2
- 239000004411 aluminium Substances 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000000605 extraction Methods 0.000 claims 1
- 238000001259 photo etching Methods 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 238000004062 sedimentation Methods 0.000 claims 1
- 238000004528 spin coating Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000015654 memory Effects 0.000 abstract description 17
- 230000008859 change Effects 0.000 abstract description 11
- 238000000137 annealing Methods 0.000 abstract description 9
- 238000011049 filling Methods 0.000 abstract description 9
- 238000005429 filling process Methods 0.000 abstract description 7
- 238000001039 wet etching Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000013461 design Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012827 research and development Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical class O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- -1 chalcogenide compounds Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
本发明提出一种垂直结构全限制相变存储器的自对准制备方法,一方面,采用无掩模相变材料填充、退火并湿法腐蚀形成局域化相变材料的方法,不仅降低了填孔工艺中的深宽比,提高了薄膜的填充质量,而且该相变材料填充工艺为自对准工艺,工艺实施难度低;另一方面,该结构的锥形电极能够把两个电极间的电场在锥尖端附近强化,相当于减小了接触电极的尺寸,减小了有效相变体积,降低了功耗。此外,由于可用的相变材料储备充分,该结构还具有较好的疲劳特性,提高了器件的工作可靠性。
The present invention proposes a self-aligned preparation method for a fully confined phase change memory with a vertical structure. On the one hand, the method of filling, annealing and wet etching with a maskless phase change material to form a localized phase change material not only reduces the filling The aspect ratio in the hole process improves the filling quality of the film, and the phase change material filling process is a self-alignment process, which is less difficult to implement; on the other hand, the tapered electrode of this structure can integrate the The electric field is strengthened near the tip of the cone, which is equivalent to reducing the size of the contact electrode, reducing the effective phase transition volume, and reducing power consumption. In addition, due to the sufficient reserves of available phase-change materials, the structure also has good fatigue characteristics, which improves the working reliability of the device.
Description
技术领域technical field
本发明涉及微纳技术领域,特别涉及一种垂直结构全限制相变存储器的自对准制备方法。The invention relates to the field of micro-nano technology, in particular to a self-aligned preparation method of a vertical structure full-confinement phase-change memory.
背景技术Background technique
高新技术产业和基础服务设施的加速发展对于快速计算和高效存储的要求越来越高,而CPU处理能力的提升对存储芯片的速度和功耗的依赖性越来越显著,因此如何发展高效存储成为未来急需突破的关键技术之一。相变存储器PCM(phase change randomaccess memory)以硫系化合物为存储介质,依靠电流的热效应控制相变材料在晶态(低阻)和非晶态(高阻)之间转化实现信息的写入与擦除,依靠探测存储区域电阻的变化实现信息的读出。PCM具有非挥发性,与目前大多数的存储器相比,具有器件尺寸小、功耗低、读取速度快、抗辐照、能实现多级存储以及与现有的CMOS工艺兼容等诸多优点。具有类似器件结构,基于金属氧化物的电阻存储器RRAM由于其结构简单、成分精确可控、与逻辑工艺兼容等优点,被认为最有可能取代目前的SRAM、DRAM、FLASH等主流产品而成为未来主流存储的半导体存储器之一。The accelerated development of high-tech industries and basic service facilities has higher and higher requirements for fast computing and efficient storage, and the improvement of CPU processing capabilities is increasingly dependent on the speed and power consumption of memory chips. Therefore, how to develop efficient storage It will become one of the key technologies that urgently need a breakthrough in the future. Phase change memory PCM (phase change random access memory) uses chalcogenide compounds as the storage medium, and relies on the thermal effect of the current to control the transformation of the phase change material between the crystalline state (low resistance) and the amorphous state (high resistance) to achieve information writing and Erasing relies on detecting changes in the resistance of the storage area to read out information. PCM is non-volatile, and compared with most current memories, it has many advantages such as small device size, low power consumption, fast reading speed, radiation resistance, multi-level storage, and compatibility with existing CMOS processes. With a similar device structure, the resistance memory RRAM based on metal oxide is considered to be the most likely to replace the current mainstream products such as SRAM, DRAM, and FLASH and become the mainstream in the future due to its simple structure, precise and controllable composition, and compatibility with logic processes. One of the semiconductor memories for storage.
目前,PCM相变存储器面临的最主要问题是操作电流过大,对驱动电路的要求较高,限制了存储功耗的降低、存储速度的提升和存储密度的提高。PCM的量产结构降低有效相变体积的方法中一类是是制备更小尺寸的纳米插塞电极;另一类方法是制备相变材料限制性结构,通过减小可供于相变的体积减小有效相变体积。这两类方法都要受限于复杂的PVD、CVD填孔工艺和CMP表面平坦化工艺。本发明提出的垂直结构全限制相变存储器的自对准制备方法,一方面,采用无掩模相变材料填充、退火并湿法腐蚀形成局域化相变材料的方法,降低了填孔工艺中的深宽比,提高了薄膜的填充质量,且制备工艺为自对准工艺,降低了工艺实施难度;另一方面,该结构的锥形电极能够把两个电极间的电场在锥尖端附近强化,相当于减小了接触电极的尺寸,减小了有效相变体积,降低了功耗。此外,由于可用的相变材料储备充分,该结构还具有较好的疲劳特性,提高了器件的工作可靠性。At present, the main problem faced by PCM phase-change memory is that the operating current is too large and the requirements on the drive circuit are high, which limits the reduction of storage power consumption, the improvement of storage speed and the increase of storage density. One of the methods to reduce the effective phase change volume of PCM mass production structure is to prepare smaller nano-plug electrodes; the other method is to prepare phase change material confinement structures, by reducing the volume available for phase change Reduce the effective phase change volume. Both types of methods are limited by complex PVD, CVD hole filling processes and CMP surface planarization processes. The self-aligned preparation method of the vertical structure fully confined phase change memory proposed by the present invention, on the one hand, uses the method of filling, annealing and wet etching to form a localized phase change material with a maskless phase change material, which reduces the hole filling process The aspect ratio in the medium improves the filling quality of the film, and the preparation process is a self-alignment process, which reduces the difficulty of process implementation; on the other hand, the tapered electrode of this structure can transfer the electric field between the two electrodes near the tip Strengthening is equivalent to reducing the size of the contact electrodes, reducing the effective phase transition volume, and reducing power consumption. In addition, due to the sufficient reserves of available phase-change materials, the structure also has good fatigue characteristics, which improves the working reliability of the device.
发明内容Contents of the invention
为解决现有技术中存在的上述问题,本发明提出了一种垂直结构全限制相变存储器的自对准制备方法。本发明对于快速实现小单元功耗、大器件工作可靠性、与现有的CMOS工艺兼容,具有非常好的产业化应用前景。In order to solve the above-mentioned problems existing in the prior art, the present invention proposes a self-aligned preparation method of a fully confined phase-change memory with a vertical structure. The invention has a very good industrial application prospect for quickly realizing the power consumption of small units, the working reliability of large devices, and being compatible with the existing CMOS technology.
本发明公开了一种垂直结构全限制相变存储器的自对准制备方法。该方法的具体步骤包括:The invention discloses a self-alignment preparation method of a vertical structure full-confinement phase-change memory. The concrete steps of this method include:
步骤1:在衬底101上淀积第一电热绝缘材料层102A,然后用“光刻-薄膜淀积-剥离”的方法在第一电热绝缘材料层102A上制备底部电极层103,并淀积第二电热绝缘材料层102B钝化表面,并用“光刻-剥离”的方法制备辅助电极层104;Step 1: Deposit the first electrothermal insulating material layer 102A on the substrate 101, and then prepare the bottom electrode layer 103 on the first electrothermal insulating material layer 102A by "photolithography-film deposition-lift-off" method, and deposit Passivate the surface of the second electrothermal insulating material layer 102B, and prepare the auxiliary electrode layer 104 by "photolithography-lift-off" method;
步骤2:在第二电热绝缘材料层102B和辅助电极层104的上表面,旋涂并光刻出光刻胶掩模100,并通过该掩模干法刻蚀出深度到达底部电极层103上表面的通孔,并淀积一层锥形电极层105;Step 2: On the upper surface of the second electrothermal insulation material layer 102B and the auxiliary electrode layer 104, spin-coat and photoetch a photoresist mask 100, and dry etch through the mask to a depth reaching the upper surface of the bottom electrode layer 103. through holes, and deposit a tapered electrode layer 105;
步骤3:去除光刻胶掩模100,剥离形成锥尖不高于辅助电极层104上表面的锥形电极105A;Step 3: removing the photoresist mask 100, and peeling off to form a tapered electrode 105A whose tapered tip is not higher than the upper surface of the auxiliary electrode layer 104;
步骤4:在辅助电极层104及锥形电极105A的上方,采用“光刻-薄膜淀积-剥离”的方法制备一层相变材料层106;Step 4: On the auxiliary electrode layer 104 and the tapered electrode 105A, a layer of phase change material layer 106 is prepared by the method of "photolithography-film deposition-lift-off";
步骤5:退火并用碱性溶液腐蚀相变材料层106,形成仅位于通孔内的局域化相变材料层106A;Step 5: annealing and etching the phase-change material layer 106 with an alkaline solution to form a localized phase-change material layer 106A located only in the through holes;
步骤6:在第二电热绝缘材料层102B、辅助电极层104及局域化相变材料层106A的上方,通过“光刻-薄膜淀积-剥离”的方法制备顶部电极层107,并用淀积第三电热绝缘材料层102C钝化表面;Step 6: On the second electrothermal insulating material layer 102B, the auxiliary electrode layer 104 and the localized phase change material layer 106A, prepare the top electrode layer 107 by the method of "photolithography-film deposition-lift-off", and deposit Passivating the surface of the third electrothermal insulating material layer 102C;
步骤7:在第三电热绝缘材料层102C上表面,采用“光刻-刻蚀-薄膜淀积-剥离”的方法制备接触深度到达底部电极层103和顶部电极层107上表面的第一测试电极108A和第二测试电极108B,完成器件制备。Step 7: On the upper surface of the third electrothermal insulating material layer 102C, the first test electrode whose contact depth reaches the upper surface of the bottom electrode layer 103 and the top electrode layer 107 is prepared by the method of "photolithography-etching-film deposition-lift-off" 108A and the second test electrode 108B to complete the device preparation.
填孔工艺的实施质量很大程度上相关于孔的深宽比,本发明涉及的制备方法相变材料的填孔无需借助于光刻掩模,降低了要填孔的深宽比,一方面,采用无掩模相变材料填充,退火并湿法腐蚀形成局域化相变材料的方法,降低了填孔工艺中的深宽比,提高了薄膜的填充质量,且制备工艺为自对准工艺,降低了工艺实施难度;另一方面,该结构的锥形电极能够把两个电极间的电场在锥尖端附近强化,相当于减小了接触电极的尺寸,减小了有效相变体积,降低了功耗。此外,由于可用的相变材料储备充分,该结构还具有较好的疲劳特性,提高了器件的工作可靠性。The implementation quality of the hole filling process is largely related to the aspect ratio of the hole. The preparation method of the present invention does not need to use a photolithographic mask to fill the hole of the phase change material, which reduces the aspect ratio of the hole to be filled. On the one hand , using maskless phase change material filling, annealing and wet etching to form a localized phase change material method, which reduces the aspect ratio in the hole filling process and improves the filling quality of the film, and the preparation process is self-aligned process, which reduces the difficulty of process implementation; on the other hand, the tapered electrode of this structure can strengthen the electric field between the two electrodes near the tip of the cone, which is equivalent to reducing the size of the contact electrode and reducing the effective phase transition volume. Reduced power consumption. In addition, due to the sufficient reserves of available phase-change materials, the structure also has good fatigue characteristics, which improves the working reliability of the device.
解决了以往研发此类垂直结构由CMP技术的研发瓶颈所导致的研发周期长、难度大、成本高、适用性差的缺点,并在制备精度、制备效率、经济性以及与现有的CMOS工艺兼容性等方面具有很大的优越性。It solves the shortcomings of long research and development cycle, high difficulty, high cost and poor applicability caused by the research and development bottleneck of CMP technology in the past research and development of such vertical structures, and is compatible with the existing CMOS process in terms of preparation accuracy, preparation efficiency, economy and It has great advantages in terms of sex and so on.
附图说明Description of drawings
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明作进一步的详细说明,其中:In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings, wherein:
图1是本发明提供的垂直结构全限制相变存储器的自对准制备方法的流程图;Fig. 1 is a flow chart of the self-aligned preparation method of the vertical structure fully confined phase change memory provided by the present invention;
图2-8是垂直结构全限制相变存储器的自对准制备工艺流程示意图。2-8 are schematic diagrams of the self-aligned preparation process of the vertical fully confined phase-change memory.
具体实施方式detailed description
请参阅图1所示,本发明提供一种垂直结构全限制相变存储器的自对准制备方法,一方面,采用无掩模相变材料填充、退火并湿法腐蚀形成局域化相变材料的方法,不仅降低了填孔工艺中的深宽比,提高了薄膜的填充质量,而且该相变材料填充工艺为自对准工艺,工艺实施难度低;另一方面,该结构的锥形电极能够把两个电极间的电场在锥尖端附近强化,相当于减小了接触电极的尺寸,减小了有效相变体积,降低了功耗。此外,由于可用的相变材料储备充分,该结构还具有较好的疲劳特性,提高了器件的工作可靠性。Please refer to Fig. 1, the present invention provides a self-aligned preparation method of a vertical fully-confined phase-change memory. On the one hand, a maskless phase-change material is used to fill, anneal and wet-etch to form a localized phase-change material. The method not only reduces the aspect ratio in the hole filling process and improves the filling quality of the film, but also the filling process of the phase change material is a self-alignment process, and the process is difficult to implement; on the other hand, the tapered electrode of the structure The electric field between the two electrodes can be strengthened near the tip of the cone, which is equivalent to reducing the size of the contact electrode, reducing the effective phase transition volume, and reducing power consumption. In addition, due to the sufficient reserves of available phase-change materials, the structure also has good fatigue characteristics, which improves the working reliability of the device.
图1示出了本发明提出的一种垂直结构全限制相变存储器的自对准制备方法流程图。图2-8给出了本发明提出的一种垂直结构全限制相变存储器的自对准制备工艺流程图。本发明提供一种垂直结构全限制相变存储器的自对准制备方法,该方法包括:FIG. 1 shows a flow chart of a self-aligned preparation method for a fully confined phase-change memory with a vertical structure proposed by the present invention. Figures 2-8 show a flow chart of a self-aligned fabrication process for a vertical fully confined phase-change memory proposed by the present invention. The invention provides a self-aligned preparation method of a vertical structure fully confined phase change memory, the method comprising:
步骤1:在衬底101上淀积第一电热绝缘材料层102A,然后用“光刻-薄膜淀积-剥离”的方法在第一电热绝缘材料层102A上制备底部电极层103,并淀积第二电热绝缘材料层102B钝化底部电极层103,并用“光刻-剥离”的方法制备辅助电极层104;Step 1: Deposit the first electrothermal insulating material layer 102A on the substrate 101, and then prepare the bottom electrode layer 103 on the first electrothermal insulating material layer 102A by "photolithography-film deposition-lift-off" method, and deposit Passivating the bottom electrode layer 103 with the second electrothermal insulating material layer 102B, and preparing the auxiliary electrode layer 104 by "photolithography-lift-off" method;
其中,所述衬底101的材料可以为硅、氮化镓、蓝宝石、碳化硅、砷化镓或玻璃;作用在于提供器件制备所必须的平坦化支撑。Wherein, the material of the substrate 101 can be silicon, gallium nitride, sapphire, silicon carbide, gallium arsenide or glass; the function is to provide planarization support necessary for device fabrication.
其中,第一电热绝缘层102A的设计目的在于提供器件的电热绝缘环境,其特征厚度不超过300纳米。第二电热绝缘材料层102B的设计目的在于形成孔内的锥形电极,并实现孔内限制型的相变材料。第二电热绝缘材料层102B的设计厚度直接决定了可淀积相变材料的设计厚度,其设计厚度为50到300纳米;Among them, the design purpose of the first electrothermal insulation layer 102A is to provide an electrothermal insulation environment for the device, and its characteristic thickness is not more than 300 nanometers. The purpose of the design of the second electrical and thermal insulation material layer 102B is to form a tapered electrode in the hole and realize a confinement phase change material in the hole. The design thickness of the second electrothermal insulating material layer 102B directly determines the design thickness of the depositable phase change material, and its design thickness is 50 to 300 nanometers;
其中,底部电极层103的设计作用在于对局域化的相变材料内施加电脉冲诱导相变,其设置厚度介于20到200纳米;辅助电极层104的设计作用提供相变材料湿法腐蚀的诱导层,实验发现处于晶态的在导电衬底和绝缘类衬底上相变材料在碱性溶液中湿法腐蚀速率差异超过一个数量级。磁控溅射后的相变材料处于非晶态,不溶于碱性溶液,经过200-500℃的退火,可以将相变材料设置到晶态。因此,通过对圆孔上方淀积一个薄层的金属层,用作相变材料腐蚀过程中的导电类衬底,提高相变材料在碱性溶液中的腐蚀速率,其设计厚度小于20纳米;Among them, the design function of the bottom electrode layer 103 is to apply an electric pulse to induce a phase change in the localized phase change material, and its setting thickness is between 20 and 200 nanometers; the design function of the auxiliary electrode layer 104 is to provide phase change material wet etching The experiment found that the difference in the wet etching rate of the phase change material in the crystalline state on the conductive substrate and the insulating substrate in the alkaline solution exceeds an order of magnitude. The phase-change material after magnetron sputtering is in an amorphous state and is insoluble in alkaline solution. After annealing at 200-500°C, the phase-change material can be set to a crystalline state. Therefore, by depositing a thin layer of metal layer on the top of the round hole, it is used as a conductive substrate in the corrosion process of the phase change material to improve the corrosion rate of the phase change material in the alkaline solution, and its design thickness is less than 20 nanometers;
步骤2:在第二电热绝缘材料层102B和辅助电极层104的上表面,旋涂并光刻出光刻胶掩模100,并通过该掩模干法刻蚀出深度到达底部电极层103上表面的通孔,并淀积一层锥形电极层105;Step 2: On the upper surface of the second electrothermal insulation material layer 102B and the auxiliary electrode layer 104, spin-coat and photoetch a photoresist mask 100, and dry etch through the mask to a depth reaching the upper surface of the bottom electrode layer 103. through holes, and deposit a tapered electrode layer 105;
其中,光刻胶掩模100的设计作用在于提供圆孔的刻蚀掩模,另一方面增加薄膜填充的深宽比,目的在于促使孔上方的薄膜并口,在孔内形成锥形。光刻胶掩模100的设计厚度200~500纳米。光刻胶掩模100的材料是SU-8光刻胶、ZEP光刻胶、HSQ光刻胶、PMMA光刻胶、AZ系列光刻胶;通过旋涂法、光学光刻、激光直写、电子束曝光、离子束直写中的任意一种或几种方法的组合制备;Among them, the design function of the photoresist mask 100 is to provide an etching mask for the circular hole, on the other hand, to increase the aspect ratio of the film filling, so as to promote the parallel opening of the film above the hole and form a tapered shape in the hole. The designed thickness of the photoresist mask 100 is 200-500 nanometers. The material of photoresist mask 100 is SU-8 photoresist, ZEP photoresist, HSQ photoresist, PMMA photoresist, AZ series photoresist; Preparation by any one of electron beam exposure, ion beam direct writing or a combination of several methods;
步骤3:去除光刻胶掩模100,剥离形成锥尖不高于辅助电极层104上表面的锥形电极105A;Step 3: removing the photoresist mask 100, and peeling off to form a tapered electrode 105A whose tapered tip is not higher than the upper surface of the auxiliary electrode layer 104;
其中,锥尖的顶部尺度和相变材料的淀积厚度决定了有效相变体积的大小。锥尖的顶部不高于辅助电极层104的设计,目的在于后期将相变材料填充在圆孔内,提高相变材料的加热效率;Among them, the top scale of the cone tip and the deposition thickness of the phase change material determine the size of the effective phase change volume. The top of the cone tip is not higher than the design of the auxiliary electrode layer 104, the purpose is to fill the phase change material in the circular hole in the later stage, and improve the heating efficiency of the phase change material;
步骤4:在辅助电极层104及锥形电极105A的上方,采用“光刻-薄膜淀积-剥离”的方法制备一层相变材料层106;Step 4: On the auxiliary electrode layer 104 and the tapered electrode 105A, a layer of phase change material layer 106 is prepared by the method of "photolithography-film deposition-lift-off";
其中,相变材料层106是GeSbTe系列合金,是通过溅射法、蒸镀法、化学气相淀积法、激光辅助淀积法、原子层淀积法、热氧化法或金属有机物热分解法中的一种制备;Wherein, the phase-change material layer 106 is a GeSbTe series alloy, which is formed by sputtering, evaporation, chemical vapor deposition, laser-assisted deposition, atomic layer deposition, thermal oxidation or metal-organic thermal decomposition. a preparation of
步骤5:退火并用碱性溶液腐蚀相变材料层106,形成仅位于通孔内的局域化相变材料层106A;Step 5: annealing and etching the phase-change material layer 106 with an alkaline solution to form a localized phase-change material layer 106A located only in the through holes;
其中,退火方式可以选用真空、氮气、氩气氛围下,快速退火,温度限定在200-500℃;相变材料的初始淀积状态为非晶态,相变材料的第一相变温度通常介于150℃左右,采用200-500℃的退火处理,可以将相变材料设置到晶态;Among them, the annealing method can be selected under vacuum, nitrogen, and argon atmosphere, rapid annealing, and the temperature is limited to 200-500 ° C; the initial deposition state of the phase change material is amorphous, and the first phase transition temperature of the phase change material is usually between At about 150°C, the phase change material can be set to a crystalline state by annealing at 200-500°C;
步骤6:在第二电热绝缘材料层102B、辅助电极层104及局域化相变材料层106A的上方,通过“光刻-薄膜淀积-剥离”的方法制备顶部电极层107,并用淀积第三电热绝缘材料层102C钝化顶部电极层107;Step 6: On the second electrothermal insulating material layer 102B, the auxiliary electrode layer 104 and the localized phase change material layer 106A, prepare the top electrode layer 107 by the method of "photolithography-film deposition-lift-off", and deposit Passivating the top electrode layer 107 with the third electrothermal insulating material layer 102C;
步骤7:在第三电热绝缘材料层102C上表面,采用“光刻-刻蚀-薄膜淀积-剥离”的方法制备接触深度到达底部电极层103和顶部电极层107上表面的第一测试电极108A和第二测试电极108B,完成器件制备。Step 7: On the upper surface of the third electrothermal insulating material layer 102C, the first test electrode whose contact depth reaches the upper surface of the bottom electrode layer 103 and the top electrode layer 107 is prepared by the method of "photolithography-etching-film deposition-lift-off" 108A and the second test electrode 108B to complete the device preparation.
其中,所述第一、第二、第三、第四和第五电热绝缘材料层102A、102B和102C的材料可以为氮氧化合物、氮化物或氧化物,或以上其中几种的组合,作用在于提供器件工作的电热绝缘环境,可以相同也可以不相同。由于其功能相同,编号中仅从最后一位的字母顺序加以区分。其中,为了更好地实现电热绝缘特性,第一电热绝缘材料层102A优选地选用LPCVD方法生长的氮化硅或者热氧化方法生长的氧化硅。同时考虑到薄膜淀积工艺的温度兼容性,按照电机薄膜的顺序(第二102B和第三102C),排在后面的薄膜的淀积温度不高于前序的薄膜的淀积温度;所述第一、二和三电热绝缘材料层102A、102B和102C,通过溅射法、蒸镀法、化学气相淀积法、激光辅助淀积法、原子层淀积法或热氧化法或金属有机物热分解法中的一种或者几种的组合进行制备。Wherein, the materials of the first, second, third, fourth and fifth electric insulation material layers 102A, 102B and 102C can be nitrogen oxide compounds, nitrides or oxides, or a combination of several of the above. It is to provide an electrothermal insulation environment for the device to work, which may be the same or different. Since their functions are the same, only the alphabetical order of the last digit is distinguished in the numbering. Wherein, in order to better realize the electric and thermal insulation properties, the first electric and thermal insulating material layer 102A is preferably selected from silicon nitride grown by LPCVD method or silicon oxide grown by thermal oxidation method. Considering the temperature compatibility of the film deposition process simultaneously, according to the order of the motor films (the second 102B and the third 102C), the deposition temperature of the film that is arranged behind is not higher than the deposition temperature of the film of the previous sequence; The first, second and third electrothermal insulating material layers 102A, 102B and 102C are formed by sputtering, vapor deposition, chemical vapor deposition, laser assisted deposition, atomic layer deposition or thermal oxidation or metal organic thermal One or a combination of several decomposition methods for preparation.
其中,底部电极层103、辅助电极层104、锥形电极层105、锥形电极105A、顶部电极107、第一测试电极108A和第二测试电极108B的材料是钨、氮化钛、镍、铝、钛、金、银、铜、铂金属单质、及其氧化物中的一种或几种的组合,可以通过溅射法、蒸镀法、化学气相淀积法、原子层沉积法、金属有机物热分解法中的一种或者几种制备。Wherein, the materials of bottom electrode layer 103, auxiliary electrode layer 104, tapered electrode layer 105, tapered electrode 105A, top electrode 107, first test electrode 108A and second test electrode 108B are tungsten, titanium nitride, nickel, aluminum , titanium, gold, silver, copper, platinum metal, and one or more combinations of oxides, can be used by sputtering, evaporation, chemical vapor deposition, atomic layer deposition, metal organics One or several preparations in the thermal decomposition method.
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.
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