CN104051623B - The preparation method of multidigit high integration vertical stratification memorizer - Google Patents
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Abstract
Description
技术领域 technical field
本发明涉及微纳技术领域，特别涉及一种多位高集成度垂直结构存储器的制备方法。 The invention relates to the field of micro-nano technology, in particular to a method for preparing a multi-bit highly integrated vertical structure memory.
背景技术 Background technique
高新技术产业和基础服务设施的加速发展对于快速计算和高效存储的要求越来越高，而CPU处理能力的提升对存储芯片的速度和功耗的依赖性越来越显著，因此如何发展高效存储成为未来急需突破的关键技术之一。相变存储器PCRAM(phase change random access memory)具有非挥发性，与目前大多数的存储器相比，具有器件尺寸小、功耗低、读取速度快、抗辐照、能实现多级存储以及与现有的CMOS工艺兼容等诸多优点。具有类似器件结构，基于金属氧化物的电阻存储器RRAM由于其结构简单、成分精确可控、与逻辑工艺兼容等优点。PCRAM和RRAM被认为最有可能取代目前的SRAM、DRAM、FLASH等主流产品而成为未来主流存储的半导体存储器。 The accelerated development of high-tech industries and basic service facilities has higher and higher requirements for fast computing and efficient storage, and the improvement of CPU processing capabilities is increasingly dependent on the speed and power consumption of memory chips. Therefore, how to develop efficient storage It will become one of the key technologies that urgently need a breakthrough in the future. Phase change memory PCRAM (phase change random access memory) is non-volatile. Compared with most current memories, it has the advantages of small device size, low power consumption, fast reading speed, radiation resistance, multi-level storage and compatibility with Compatibility with existing CMOS processes and many other advantages. With a similar device structure, metal oxide-based resistive memory RRAM has the advantages of simple structure, precise and controllable composition, and compatibility with logic processes. PCRAM and RRAM are considered to be most likely to replace the current mainstream products such as SRAM, DRAM, and FLASH, and become semiconductor memories for future mainstream storage.
PCRAM以硫系化合物为存储介质，依靠电流的热效应控制相变材料在晶态(低阻)和非晶态(高阻)之间转化实现信息的写入与擦除，依靠探测存储区域电阻的变化实现信息的读出。目前，相变存储器面临的最主要问题是操作电流过大，对驱动电路的要求较高，限制了存储功耗的降低、存储速度的提升和存储密度的提高。对于PCRAM操作电流过大的技术瓶颈，常规的解决方法(例如垂直器件中的插塞电极制备)对于光学光刻分辨率、CMP、MOCVD等工艺的依赖性较强，难于实现大面积、高精度、经济、高效地制备。而制备精度较高的电子束曝光、聚焦粒子束刻蚀等线性加工技术虽然能实现较高的制备精度，但受限于加工的速度无法实现大面积衬底上 精细图形的高效制备。 PCRAM uses chalcogenide compounds as the storage medium, and relies on the thermal effect of the current to control the transformation of the phase change material between the crystalline state (low resistance) and the amorphous state (high resistance) to realize the writing and erasing of information, and relies on the detection of the resistance of the storage area Changes enable the readout of information. At present, the main problem faced by phase-change memory is that the operating current is too large and the requirements on the drive circuit are high, which limits the reduction of storage power consumption, the improvement of storage speed and the increase of storage density. For the technical bottleneck of excessive PCRAM operating current, conventional solutions (such as the preparation of plug electrodes in vertical devices) are highly dependent on optical lithography resolution, CMP, MOCVD and other processes, and it is difficult to achieve large-area, high-precision , Economical and efficient preparation. Although linear processing technologies such as electron beam exposure and focused particle beam etching with high preparation accuracy can achieve high preparation accuracy, they cannot achieve efficient preparation of fine patterns on large-area substrates due to the limited processing speed.
电阻存储器(Resistance RandomAccess Memory，RRAM)是基于一些介质材料的电诱导阻变效应发展起来的非挥发存储器。它以简单的MIM(Metal-Insulator-Metal)电容结构为功能器件。电容结构中间的绝缘层是具有电诱导阻变特性的材料，其材料电阻会在特定外加电信号下发生可逆的非挥发的变化。这种可逆的阻值变化就形成了存储器工作的基础。 Resistance Random Access Memory (RRAM) is a non-volatile memory developed based on the electrically induced resistive switching effect of some dielectric materials. It uses a simple MIM (Metal-Insulator-Metal) capacitor structure as a functional device. The insulating layer in the middle of the capacitor structure is a material with electrically induced resistive switching properties, and its material resistance will undergo a reversible and non-volatile change under a specific external electrical signal. This reversible change in resistance forms the basis of memory operation.
对于PCRAM和RRAM来说，最具有产业化发展前景的是垂直结构，但垂直结构的制备产业化过程中都离不开CMP工艺。相比较其它工艺来说，对于新材料的刻蚀和CMP工艺优化则是一个比较耗时、耗钱的过程，这也是新型存储材料验证要面临的最大瓶颈。 For PCRAM and RRAM, the most industrialized development prospect is the vertical structure, but the industrialization process of the preparation of the vertical structure is inseparable from the CMP process. Compared with other processes, the etching and CMP process optimization for new materials is a relatively time-consuming and costly process, which is also the biggest bottleneck in the verification of new storage materials.
发明内容 Contents of the invention
为解决现有技术中存在的上述问题，本发明提出了一种多位高集成度垂直结构存储器的制备方法。本发明对于快速实现小单元功耗及大单位面积集成度，与现有的CMOS工艺兼容，具有非常好的产业化应用前景。 In order to solve the above-mentioned problems in the prior art, the present invention proposes a method for preparing a multi-bit highly integrated vertical structure memory. The invention is compatible with the existing CMOS process for quickly realizing small unit power consumption and large unit area integration, and has very good industrial application prospects.
本发明提供一种多位高集成度垂直结构存储器的制备方法，该方法包括： The invention provides a method for preparing a multi-bit highly integrated vertical structure memory, the method comprising:
步骤1：在衬底上，淀积第一电热隔离材料层，旋涂掩模层并光刻形成第一掩模开槽；然后，在第一掩模开槽及第一电热隔离材料层暴露的上表面上，淀积第一电极材料层，并去除第一掩模开槽，剥离形成第一下电极；其次，在第一电热隔离材料层及第一下电极暴露的上表面，淀积第二电热隔离材料层； Step 1: On the substrate, deposit the first electrothermal isolation material layer, spin coat the mask layer and form the first mask slot by photolithography; then, open the first mask and expose the first electrothermal isolation material layer On the upper surface of the first electrode material layer, the first electrode material layer is deposited, and the first mask is removed to open the groove, and the first lower electrode is peeled off to form the first lower electrode; secondly, on the exposed upper surface of the first electric thermal isolation material layer and the first lower electrode, deposit The second layer of electrically insulating material;
步骤2：在第二电热隔离材料层上，旋涂掩模层并光刻形成第二掩模开槽；然后，在第二掩模开槽及第二电热隔离材料层暴露的上表面，淀积第二电极材料层，并去除第二掩模开槽，剥离形成第二下电极；其次，在第二电热隔离材料层及第二下电极暴露的上表面，淀积第三电热隔离材料层； Step 2: Spin-coat a mask layer on the second electrothermal isolation material layer and form a second mask groove by photolithography; then, deposit Deposit the second electrode material layer, remove the second mask to open the groove, and peel off to form the second lower electrode; secondly, deposit the third electrothermal isolation material layer on the exposed upper surface of the second electrothermal isolation material layer and the second lower electrode ;
步骤3：在第三电热隔离材料层上旋涂掩模层，并光刻形成第三掩模开槽；然后，在第三掩模开槽及第三电热隔离材料层暴露的上表面淀积第三电极材料层，并去除第三掩模开槽，剥离形成第三下电极；其次，在第三电 热隔离材料层及第三下电极暴露的上表面，淀积第四电热隔离材料层； Step 3: Spin-coat a mask layer on the third electrothermal isolation material layer, and form a third mask groove by photolithography; then, deposit The third electrode material layer, and removing the third mask to open the groove, peeling off to form the third lower electrode; secondly, depositing the fourth electrothermal isolation material layer on the exposed upper surface of the third electrothermal isolation material layer and the third lower electrode;
步骤4：在第四电热隔离材料层上，旋涂掩模层并光刻形成第四掩模开槽；然后，在第四掩模开槽及第四电热隔离材料层暴露的上表面，依次淀积存储材料层及第四电极材料层，并去除第四掩模开槽，剥离形成条形存储区及垂直叠加在条形存储区正上方的上电极；其次，在第四电热隔离材料层及上电极暴露的上表面，淀积第五电热隔离材料层； Step 4: Spin-coat the mask layer on the fourth electrothermal isolation material layer and form a fourth mask slot by photolithography; then, on the fourth mask slot and the exposed upper surface of the fourth electrothermal isolation material layer, sequentially Deposit the storage material layer and the fourth electrode material layer, and remove the fourth mask to open the groove, peel off to form the strip-shaped storage area and the upper electrode vertically stacked directly above the strip-shaped storage area; secondly, in the fourth electrothermal isolation material layer and the exposed upper surface of the upper electrode, depositing a fifth layer of electrothermal isolation material;
步骤5：在第五电热隔离材料层上旋涂掩模层，并光刻形成第五掩模开槽；然后，通过第五掩模开槽，在第五、第四、第三、第二电热隔离材料层上，各开孔至第一、第二、第三下电极的上表面；其次，在第五掩模开槽及第一、第二、第三下电极暴露的上表面，淀积第五电极材料层，并去除第五掩模开槽并剥离形成三个第一测试电极； Step 5: Spin-coat a mask layer on the fifth electrothermal isolation material layer, and form grooves in the fifth mask by photolithography; On the layer of electrothermal isolation material, holes are opened to the upper surfaces of the first, second, and third lower electrodes; secondly, grooves are opened in the fifth mask and the exposed upper surfaces of the first, second, and third lower electrodes are deposited. depositing the fifth electrode material layer, and removing the fifth mask to open the groove and stripping to form three first test electrodes;
步骤6：在第五电热隔离材料层及三个第一测试电极暴露的上表面上旋涂掩模层，并光刻形成第六掩模开槽；然后，通过第六掩模开槽，在第五电热隔离材料层开孔至上电极的上表面；其次，在第六掩模开槽及上电极暴露的上表面，淀积第六电极材料层，并去除第六掩模开槽并剥离形成三个第二测试电极。 Step 6: Spin-coat a mask layer on the exposed upper surfaces of the fifth electrothermal isolation material layer and the three first test electrodes, and form grooves in the sixth mask by photolithography; then, open grooves through the sixth mask, The fifth electrothermal isolation material layer is opened to the upper surface of the upper electrode; secondly, the sixth electrode material layer is deposited on the sixth mask groove and the exposed upper surface of the upper electrode, and the sixth mask groove is removed and peeled off to form Three second test electrodes.
本发明公开了一种多位高集成度垂直结构存储器的制备方法。该方法采用薄膜淀积工艺和腐蚀工艺制备多位高集成度垂直结构存储器。该方法一方面，通过控制下电极薄膜的淀积厚度，有效可控与下电极边缘接触的存储材料的有效存储体积，从而达到降低单个存储bit的功耗的目的；另一方面，通过将下电极与电热隔离层材料交替淀积，可实现多位存储，从而提高存储密度；其次，由于与该种方法所述器件结构的研发和生产工艺较好地兼容于当前晶体管的主流工艺，研发及产业化转移成本低，利用该方法所述的器件结构可以快速实现产业化布局。本方法在高精度光刻手段，及高精度的薄膜淀积与腐蚀工艺辅助下，解决了以往研发此类垂直结构由CMP技术的研发瓶颈所导致的研发周期长、难度大、成本高、适用性差的缺点，并在制备精度、制备效率、经济性以及与现有的CMOS工艺兼容性等方面具有很大的优越性。 The invention discloses a preparation method of a multi-bit highly integrated vertical structure memory. The method adopts a thin film deposition process and an etching process to prepare a multi-bit highly integrated vertical structure memory. In this method, on the one hand, by controlling the deposition thickness of the lower electrode film, the effective storage volume of the storage material in contact with the edge of the lower electrode can be effectively controlled, thereby achieving the purpose of reducing the power consumption of a single storage bit; Alternate deposition of electrodes and electrothermal isolation layer materials can realize multi-bit storage, thereby increasing storage density; secondly, because the research and development and production process of the device structure described in this method are better compatible with the current mainstream technology of transistors, research and development and The cost of industrialization transfer is low, and the device structure described in this method can be used to quickly realize the industrialization layout. With the help of high-precision photolithography and high-precision film deposition and corrosion technology, this method solves the long research and development cycle, difficulty, high cost and applicable It has the disadvantages of poor performance, and has great advantages in terms of preparation accuracy, preparation efficiency, economy, and compatibility with existing CMOS processes.
附图说明 Description of drawings
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明，其中： In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings, wherein:
图1是本发明提供的多位高集成度垂直结构存储器的制备方法的流程图； Fig. 1 is the flow chart of the preparation method of multi-bit highly integrated vertical structure memory provided by the present invention;
图2是基于多位高集成度垂直结构存储器的制备工艺流程总装后结构示意图； Figure 2 is a schematic diagram of the fabrication process based on multi-bit highly integrated vertical structure memory after assembly;
图3是本发明提出的器件结构的三维结构示意图。 Fig. 3 is a three-dimensional schematic diagram of the device structure proposed by the present invention.
具体实施方式 detailed description
请参阅图1、图2和图3所示，本发明提供一种多位高集成度垂直结构存储器的制备方法，该方法包括： Referring to Fig. 1, Fig. 2 and Fig. 3, the present invention provides a method for preparing a multi-bit highly integrated vertical structure memory, the method comprising:
1)在衬底101上，淀积第一电热隔离材料层102A，并在第一电热隔离材料层102A上，旋涂掩模层，并光刻形成第一掩模开槽； 1) On the substrate 101, a first electrothermal isolation material layer 102A is deposited, and a mask layer is spin-coated on the first electrothermal isolation material layer 102A, and a first mask groove is formed by photolithography;
其中衬底101的材料可以为硅、氮化镓、蓝宝石、碳化硅、砷化镓或玻璃；作用在于提供器件制备所必须的平坦化支撑。 The material of the substrate 101 can be silicon, gallium nitride, sapphire, silicon carbide, gallium arsenide or glass; the function is to provide planarization support necessary for device fabrication.
2)在第一掩模开槽及第一电热隔离材料层102A暴露的上表面上，淀积第一电极材料层； 2) Depositing a first electrode material layer on the first mask opening and the exposed upper surface of the first electrothermal isolation material layer 102A;
3)腐蚀去除第一掩模开槽，剥离形成第一下电极104A； 3) Etching and removing the grooves in the first mask, and peeling off to form the first lower electrode 104A;
4)在第一电热隔离材料层102A及第一下电极104A暴露的上表面，淀积第二电热隔离材料层102B； 4) Depositing the second electrothermal isolation material layer 102B on the exposed upper surface of the first electrothermal isolation material layer 102A and the first lower electrode 104A;
其中，所淀积的第一电极材料薄膜的厚度，一定程度上决定了下电极与存储材料层的边缘接触面积。边缘接触面积越小，对应的器件的有效存储体积越小，相应的单个存储bit的功耗就越低。电热隔离层与下电极交替淀积，一方面可以保证各个下电极间的电热隔离，另一方面，也提高了存储密度，降低了单位bit上的工艺成本。 Wherein, the thickness of the deposited first electrode material film determines to a certain extent the edge contact area between the lower electrode and the storage material layer. The smaller the edge contact area, the smaller the effective storage volume of the corresponding device, and the lower the power consumption of a corresponding single storage bit. Electrothermal isolation layers are deposited alternately with the lower electrodes. On the one hand, it can ensure the electrical and thermal isolation between each lower electrode. On the other hand, it also improves the storage density and reduces the process cost per bit.
5)在第二电热隔离材料层102B上旋涂掩模层，并光刻形成第二掩模开槽； 5) Spin-coat a mask layer on the second electrothermal isolation material layer 102B, and form a second mask slot by photolithography;
6)在第二掩模开槽及第二电热隔离材料层102B暴露的上表面淀积第二电极材料层； 6) Depositing a second electrode material layer on the upper surface of the second mask opening and the exposed upper surface of the second electrothermal isolation material layer 102B;
7)腐蚀去除第二掩模开槽，剥离形成第二下电极104B； 7) Etching and removing the grooves in the second mask, and peeling off to form the second lower electrode 104B;
8)在第二电热隔离材料层102B及第二下电极104B暴露的上表面，淀积第三电热隔离材料层102C； 8) Depositing a third electrothermal isolation material layer 102C on the exposed upper surface of the second electrothermal isolation material layer 102B and the second lower electrode 104B;
9)在第三电热隔离材料层102C上旋涂掩模层，并光刻形成第三掩模开槽； 9) Spin-coat a mask layer on the third electrothermal isolation material layer 102C, and form a third mask groove by photolithography;
10)在第三掩模开槽及第三电热隔离材料层102C暴露的上表面淀积第三电极材料层； 10) Depositing a third electrode material layer on the upper surface of the third mask opening and the exposed upper surface of the third electrothermal isolation material layer 102C;
11)腐蚀去除第三掩模开槽，剥离形成第三下电极104C； 11) Etching and removing the grooves in the third mask, and peeling off to form the third lower electrode 104C;
12)在第三电热隔离材料层102C及第三下电极104C暴露的上表面，淀积第四电热隔离材料层102D； 12) Depositing a fourth electrothermal isolation material layer 102D on the exposed upper surface of the third electrothermal isolation material layer 102C and the third lower electrode 104C;
13)在第四电热隔离材料层102D上旋涂掩模层，并光刻形成第四掩模开槽； 13) Spin-coat a mask layer on the fourth electrothermal isolation material layer 102D, and form a fourth mask slot by photolithography;
14)在第四掩模开槽及第四电热隔离材料层102D暴露的上表面，依次淀积存储材料层及第四电极材料层； 14) Depositing a storage material layer and a fourth electrode material layer in sequence on the fourth mask opening and the exposed upper surface of the fourth electrothermal isolation material layer 102D;
15)腐蚀去除第四掩模开槽，剥离形成条形存储区105及垂直叠加在条形存储区105正上方的上电极106； 15) Etching and removing the groove in the fourth mask, peeling off to form the strip-shaped storage area 105 and the upper electrode 106 vertically stacked directly above the strip-shaped storage area 105;
16)在第四电热隔离材料层102D及上电极106暴露的上表面，淀积第五电热隔离材料层102E； 16) Depositing the fifth electrothermal isolation material layer 102E on the exposed upper surface of the fourth electrothermal isolation material layer 102D and the upper electrode 106;
17)在第五电热隔离材料层102E上旋涂掩模层，并光刻形成第五掩模开槽； 17) Spin-coat a mask layer on the fifth electrothermal isolation material layer 102E, and form a fifth mask groove by photolithography;
18)通过第五掩模开槽，在第五电热隔离材料层102E、第四电热隔离材料层102D、第三电热隔离材料层102C、第二电热隔离材料层102B上，各开孔至第一下电极104A、第二下电极104B和第三下电极104C的上表面； 18) Grooving through the fifth mask, on the fifth electrothermal isolation material layer 102E, the fourth electrothermal isolation material layer 102D, the third electrothermal isolation material layer 102C, and the second electrothermal isolation material layer 102B, respectively opening holes to the first the upper surfaces of the lower electrode 104A, the second lower electrode 104B, and the third lower electrode 104C;
19)在第五掩模开槽及第一下电极104A、第二下电极104B、第三下电极104C暴露的上表面，淀积第五电极材料层； 19) Depositing a fifth electrode material layer on the fifth mask groove and the exposed upper surfaces of the first lower electrode 104A, the second lower electrode 104B, and the third lower electrode 104C;
20)去除第五掩模开槽并剥离形成三个第一测试电极107； 20) removing the groove of the fifth mask and peeling off to form three first test electrodes 107;
21)在第五电热隔离材料层102E及三个第一测试电极107暴露的上表面上旋涂掩模层，并光刻形成第六掩模开槽； 21) Spin-coat a mask layer on the exposed upper surfaces of the fifth electrothermal isolation material layer 102E and the three first test electrodes 107, and form sixth mask grooves by photolithography;
22)通过第六掩模开槽，在第五电热隔离材料层102E开孔至上电极106的上表面； 22) opening grooves through the sixth mask, and opening holes in the fifth electrothermal isolation material layer 102E to the upper surface of the upper electrode 106;
23)在第六掩模开槽及上电极106暴露的上表面，淀积第六电极材料 层； 23) Deposit a sixth electrode material layer on the sixth mask opening and the exposed upper surface of the upper electrode 106;
24)去除第六掩模开槽并剥离形成三个第二测试电极108。 24) Remove the opening of the sixth mask and lift off to form three second test electrodes 108 .
所述第一、第二、第三、第四和第五电热隔离材料层102A、102B、102C、102D和102E的材料可以为氮氧化合物、氮化物或氧化物，或以上其中多种的组合，作用在于提供器件工作的电热绝缘环境，可以相同也可以不相同。由于其功能相同，编号中仅从最后一位的字母顺序加以区分。其中，为了更好地实现电热绝缘特性，第一电热绝缘材料层102A优选地选用LPCVD方法生长的氮化硅或者热氧化方法生长的氧化硅。同时考虑到薄膜淀积工艺的温度兼容性，按照电机薄膜的顺序(第二102B、第三102C、第四102D和第五102E)，排在后面的薄膜的淀积温度不高于前序的薄膜的淀积温度；所述第一、二、三、四和五电热绝缘材料层102A、102B、102C、102D和102E，通过溅射法、蒸镀法、化学气相淀积法、激光辅助淀积法、原子层淀积法或热氧化法或金属有机物热分解法中的一种或者几种的组合进行制备。 The material of the first, second, third, fourth and fifth electrically insulating material layers 102A, 102B, 102C, 102D and 102E may be oxynitride, nitride or oxide, or a combination of them , the function is to provide an electrothermal insulation environment for the device to work, which can be the same or different. Since their functions are the same, only the alphabetical order of the last digit is distinguished in the numbering. Wherein, in order to better realize the electric and thermal insulation properties, the first electric and thermal insulating material layer 102A is preferably selected from silicon nitride grown by LPCVD method or silicon oxide grown by thermal oxidation method. At the same time, considering the temperature compatibility of the film deposition process, according to the order of the motor film (second 102B, third 102C, fourth 102D and fifth 102E), the deposition temperature of the film behind the sequence is not higher than that of the previous sequence. The deposition temperature of the film; the first, second, third, fourth and fifth layers of electrothermal insulating material 102A, 102B, 102C, 102D and 102E, by sputtering, evaporation, chemical vapor deposition, laser-assisted deposition One or a combination of deposition method, atomic layer deposition method, thermal oxidation method or metal organic compound thermal decomposition method.
所述掩模层、第一、二、三、四和五掩模开槽的材料是SU-8光刻胶、ZEP光刻胶、HSQ光刻胶、PMMA光刻胶、AZ系列光刻胶；通过旋涂法、光学光刻、激光直写、电子束曝光、离子束直写中的任意一种或几种方法的组合制备。 The material for the mask layer, first, second, third, fourth and fifth mask grooves is SU-8 photoresist, ZEP photoresist, HSQ photoresist, PMMA photoresist, AZ series photoresist ; Prepared by any one or a combination of methods of spin coating, optical lithography, laser direct writing, electron beam exposure, and ion beam direct writing.
所述第一、二、三、四、五和六电极材料层、第一、二和三下电极104A、104B和104C、上电极106、三个第一测试电极107、三个第二测试电极的材料可以是钨、氮化钛、镍、铝、钛、金、银、铜、铂金属单质、及其氧化物中的一种或及其组合；通过旋涂法、化学气相淀积法、原子层沉积法、金属有机物热分解法中的一种或者几种制备。 The first, second, third, fourth, fifth and sixth electrode material layers, first, second and third lower electrodes 104A, 104B and 104C, upper electrode 106, three first test electrodes 107, three second test electrodes The material can be one or a combination of tungsten, titanium nitride, nickel, aluminum, titanium, gold, silver, copper, platinum metal element, and its oxide; by spin coating, chemical vapor deposition, One or more of the atomic layer deposition method and metal organic compound thermal decomposition method.
条形存储区105的材料是GeSbTe系列合金，或者是由GeSbTe系列合金、TiO2、Ta2O5、CeO2、HfOx、NiO、AlOx、TiOx、TaOx组成的二层或三层叠层。通过溅射法、蒸镀法、化学气相淀积法、激光辅助淀积法、原子层淀积法、热氧化法或金属有机物热分解法中的一种制备。 The material of the bar-shaped storage area 105 is a GeSbTe series alloy, or a two-layer or three-layer stack composed of a GeSbTe series alloy, TiO 2 , Ta 2 O 5 , CeO 2 , HfO x , NiO, AlO x , TiO x , and TaO x layer. It is prepared by one of sputtering method, vapor deposition method, chemical vapor deposition method, laser-assisted deposition method, atomic layer deposition method, thermal oxidation method or metal organic compound thermal decomposition method.
图3示出了利用本发明提出的上述方法制备的存储器的立体结构示意图。为了能够突出核心的存储单元结构，其中第五电热隔离材料层102E没有在三维立体机构示意图中标出。 FIG. 3 shows a schematic diagram of a three-dimensional structure of a memory device prepared by the method proposed in the present invention. In order to highlight the core memory cell structure, the fifth electrothermal isolation material layer 102E is not marked in the schematic diagram of the three-dimensional mechanism.
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。 The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080149913A1 (en) * | 2006-12-26 | 2008-06-26 | Hiroyasu Tanaka | Semiconductor memory device and method of manufacturing the same |
| US20100178729A1 (en) * | 2009-01-13 | 2010-07-15 | Yoon Hongsik | Resistance-Type Random Access Memory Device Having Three-Dimensional Bit Line and Word Line Patterning |
| CN101794862A (en) * | 2010-02-24 | 2010-08-04 | 中国科学院半导体研究所 | Manufacturing method of vertical phase-change memory |
| CN101894854A (en) * | 2009-05-22 | 2010-11-24 | 旺宏电子股份有限公司 | Phase change memory cell with vertical channel access transistor and memory plane |
| CN102881708A (en) * | 2011-07-13 | 2013-01-16 | 海力士半导体有限公司 | Semiconductor intergrated circuit device, method of manufacturing same, and method of driving same |
| US20130048938A1 (en) * | 2011-08-25 | 2013-02-28 | National Institute Of Advanced Industrial Science And Technology | Phase change memory device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080149913A1 (en) * | 2006-12-26 | 2008-06-26 | Hiroyasu Tanaka | Semiconductor memory device and method of manufacturing the same |
| US20100178729A1 (en) * | 2009-01-13 | 2010-07-15 | Yoon Hongsik | Resistance-Type Random Access Memory Device Having Three-Dimensional Bit Line and Word Line Patterning |
| CN101894854A (en) * | 2009-05-22 | 2010-11-24 | 旺宏电子股份有限公司 | Phase change memory cell with vertical channel access transistor and memory plane |
| CN101794862A (en) * | 2010-02-24 | 2010-08-04 | 中国科学院半导体研究所 | Manufacturing method of vertical phase-change memory |
| CN102881708A (en) * | 2011-07-13 | 2013-01-16 | 海力士半导体有限公司 | Semiconductor intergrated circuit device, method of manufacturing same, and method of driving same |
| US20130048938A1 (en) * | 2011-08-25 | 2013-02-28 | National Institute Of Advanced Industrial Science And Technology | Phase change memory device |
Non-Patent Citations (1)
| Title |
|---|
| 侧墙技术在相变存储器中的应用;付英春 等;《微纳电子技术》;20120515;第49卷(第5期);第328-335页 * |
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