[go: up one dir, main page]

CN101272034B - 电极图形以及引线接合方法 - Google Patents

电极图形以及引线接合方法 Download PDF

Info

Publication number
CN101272034B
CN101272034B CN2008100830350A CN200810083035A CN101272034B CN 101272034 B CN101272034 B CN 101272034B CN 2008100830350 A CN2008100830350 A CN 2008100830350A CN 200810083035 A CN200810083035 A CN 200810083035A CN 101272034 B CN101272034 B CN 101272034B
Authority
CN
China
Prior art keywords
wire bonding
electrode
pattern
recognized
short side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008100830350A
Other languages
English (en)
Other versions
CN101272034A (zh
Inventor
久义浩
山口勉
田中秀幸
松尾和则
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN101272034A publication Critical patent/CN101272034A/zh
Application granted granted Critical
Publication of CN101272034B publication Critical patent/CN101272034B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

在针对在眼孔上粘结次粘着基台和半导体芯片的封装件的安装方式中，由于组装装置的精度的影响，眼孔的中心线和激光二极管的中心线倾斜，并且用于引线接合的Au球露出到电极外。引线接合用电极图形具有引线接合基准图形和引线接合识别图形，将从引线接合基准图形到引线接合位置的距离和从引线接合识别图形到引线接合位置的距离设定为预定的值，由此，能够精度良好地进行引线接合。

Description

电极图形以及引线接合方法
技术领域
本发明涉及用于在半导体装置或衬底等的电极上进行引线接合的电极图形以及引线接合方法。
背景技术
在进行对电极和金属引线进行接线的引线接合时，需要在接合装置中示教(teaching)接合位置。通常，在用Au球等进行引线接合时，Au球以充分地收容在进行引线接合的电极内的方式设计。在半导体装置制造时的引线接合步骤中，作为用于把握引线接合装置应该进行接线的场所的技术，有特开2001-326241号公报中记载的技术。
在对激光二极管进行引线接合的情况下，引线接合用的电极图形作成细长的形状。在记录型激光二极管中，随着记录时的倍速上升而激光二极管要求的光输出日益增大，另一方面，低价格化的要求非常强。为了响应这些要求，为了得到高输出，使激光二极管纵向的长度变长，为了低价格化，缩短激光二极管的横向的长度，使从单一晶片内取得的芯片数增加。由此，例如在350mW级的记录型高输出激光二极管的情况下，成为纵向长度超过2000μm、横向长度为150μm以下这样的非常细长的形状。
在记录型高输出激光二极管的针对封装(package)的安装方式中，在眼孔(eyelet)上以AuSn焊料等连接次粘着基台(surmount)和激光二极管。并且，对激光二极管的电极和导线或眼孔进行引线接合，但是，为了在电极上的预定位置形成Au球，对电极端部的特征图形进行识别，接下来，在激光器的长度方向上错开预定量的场所对Au球进行接合。可知在眼孔上粘结次粘着基台和激光二极管时，由于组装装置的精度的影响，眼孔的中心线和激光二极管的中心线最大倾斜2°左右。
专利文献1特开2001-326241号公报
在激光二极管中心和眼孔中心没有倾斜的情况下，Au球可在电极中心进行接合。但是，存在倾斜时，存在Au球露出到电极外的问题。电极的长度方向的长度较长、短边方向的长度(电极宽度)较短时，针对短边方向的错开变大，Au球的露出量变多。如果在电极端部附近形成Au球，则可使由倾斜误差导致的Au球露出量变少，但是，在这种情况下，存在如下问题：在与Au球附近离开的场所，能够提供给激光二极管的电流密度改变，激光二极管难以正常地工作。由此，Au球需要形成在激光二极管中心附近。如记录型高输出激光二极管那样，在细长的电极图形上形成Au球的情况下，该影响更显著。
发明内容
本发明是为了解决上述问题而进行的，提供一种能够精度良好地进行引线接合的电极图形以及引线接合方法。
本发明的电极图形是具有短边和长边的引线接合用的电极图形，其特征在于，
具有引线接合基准图形和引线接合识别图形，该引线接合基准图形表示用于确定引线接合位置的基准位置，
并且，L和Lb满足如下关系，即，L≥14.3×(W-3d/4)
Lb≤14.3×(W-3d/4)，
其中，
L是所述基准位置与下述的线之间的距离，即，该线为：在粘结于所述电极图形上的引线接合用的金属部位处、通过与所述短边平行的方向上的宽度为最大的位置且与所述短边平行的方向上的线，
Lb：通过引线接合识别图形的所述长边方向的中心且与所述短边平行的方向上的线、和通过所述金属部位的与所述短边平行的方向上的宽度为最大的位置且与所述短边平行的方向上的线的距离，
d：在电极图形上所粘结的引线结合用金属部位的与所述短边平行的方向上的宽度的最大值，
W：电极图形的与短边平行的方向上的宽度。
附图说明
图1是示出本发明实施方式的电极图形的概要图。
图2是示出使用本发明实施方式的电极图形的半导体元件的概要图。
图3是示出本发明实施方式的电极图形的概要图。
图4是示出本发明实施方式的电极图形的概要图。
图5是示出本发明实施方式的电极图形的概要图。
具体实施方式
实施方式1
图1是示出本发明实施方式的引线接合用的电极图形的概要图。此外，图2是示出使用本发明实施方式的引线接合用的电极图形的半导体元件的概要图。下面，使用图1、图2进行说明。在图中，101是半导体衬底，203是次粘着基台，209是绝缘玻璃。在本发明的实施方式中，将在细长的激光二极管芯片上进行引线接合的半导体元件作为例子。在激光二极管芯片上，形成引线接合用的电极图形103。在进行该电极图形103上的引线接合的区域111内，形成直径为d的Au球109，进行引线接合。此时，在图2中示出的眼孔201的中心和激光二极管205的中心没有倾斜错开的状态(θ＝0)时，以中心在如下的长边方向的线上的方式形成Au球109并进行引线接合，该长边方向的线通过与电极图形103的短边平行的方向的中心。在电极图形103上形成成为引线接合识别图形107的特征图形。在本实施方式中，在电极图形103的长度方向的一个边上形成矩形的切口，作为引线接合识别图形107。以如下方式确定各尺寸。
L：电极图形的边缘部(电极端部105)和在引线接合区域111上所形成的Au球109的中心之间的最短距离，
Lb：通过引线接合识别图形107的长边方向的中心且与短边平行的方向的线、和在引线接合区域111上所形成的Au球109的中心之间最短距离，
d：Au球109的直径，
W：电极图形103的与短边平行的方向的宽度，
对于眼孔201中心和激光二极管205的中心的倾斜错开量θ来说，与组装装置精度相比，最大为2°。在引线接合区域111上形成Au球109时，将从引线接合区域111露出的量设为x时，x由下式表示。
x＝d/2-W/2+Ltanθ
在此，在露出量x容许到d/8的情况下，tan2°＝0.0349，L和Lb分别成为下式。
L＝14.3×(W-3d/4)
Lb＝14.3×(W-3d/4)
在本实施方式中，将电极端部105作为成为确定引线结合位置用的基准的引线接合基准图形。该引线接合基准图形和引线接合区域111内的直径为d的Au球109的中心的距离L为L≥14.3×(W-3d/4)的位置进行引线接合。此时，通过形成在电极图形103上的引线接合识别图形107的长度方向的中心且与短边平行的方向的线和Au球109的中心之间的距离Lb为Lb≤14.3×(W-3d/4)(μm)的方式进行定位。将记录型高输出激光二极管作为例子时，激光二极管的长度方向的长度为2000μm，宽度为120μm，使电极的宽度为80μm，Au球直径为80±10μm，L为286μm左右，没有引线接合识别图形时，Au球只能够形成在细长的电极的端部，所注入的电流密度在电极上端部和下端部改变，激光二极管的工作不稳定。在所希望的位置上形成本发明的引线接合识别图形，由此，可简单地消除所注入的电流密度的不均匀。
在本实施方式中，使用电极端部105作为引线接合基准图形，但是，除了电极端部以外，也能够将电极内的特征图形作为引线接合基准图形。例如，在电极图形103的四角之一，形成确认芯片前后等用的缺口，也可将该缺口作为引线接合基准图形。在本实施方式中，该缺口成为组合矩形后的形状，但是，圆形或三角形等其他形状也可以。此外，在本实施方式中，形成Au球109来进行引线接合，但是，在楔形接合的情况下不形成Au球，而是对引线前端进行超声波压焊，并进行接线。
实施方式2
在图3以及图4中示出本发明实施方式2的引线接合用的电极图形的概要图。在实施方式1中，如图1所示，将引线接合识别图形107作成矩形的缺口图形，但是，在本实施方式中，将引线接合识别图形作成如图3中所示的圆形的识别图形形状或如图4所示的三角形状。在圆形的引线接合识别图形307中，在使该引线接合识别图形307较小的情况或使用加工精度较低的刻蚀法的情况下，即使产生刻蚀塌边，形状仍为圆形不变，可防止识别错误。此外，在三角形状的引线接合识别图形407的情况下，与相同大小的四角形状相比，可使直线部的长度变长，所以，具有能够使由刻蚀塌边等导致的图形破坏的影响变小的效果。
引线接合识别图形307、407形成在电极图形303、403的长度方向的一边的侧部，由此，可以由剥离法(lift-off)容易地形成。此外，在使用刻蚀等方法的情况下，如图5所示，可以将引线接合识别图形507形成在电极图形503的内部。
实施方式3
本实施方式涉及识别引线接合识别图形并进行引线结合的方法。
参考图1以及图2，识别眼孔201的外形，由此，可得知引线接合识别图形107的大致位置。接下来，识别形成在电极图形103上的引线接合识别图形107。此时，若需要，则改变照相机(camera)放大率，来识别引线接合识别图形107。最后，以引线211、213进行引线接合，进行针对导线207、GND的接线。在使用该方法的情况下，在眼孔201上的激光二极管205由于设定错误、预对准的不良等或定位夹具的不良等而从预定的位置错开时，能够马上发现。即，在识别眼孔外形后，在预想位置没有引线接合识别图形，所以，装置因此停止。这能够使激光二极管粘结步骤中的位置错开次品的生产为最低限度，所以，具有抑制由继续产生次品而导致的损失的效果。
实施方式4
本实施方式涉及识别引线接合识别图形并进行引线结合的其他方法。
与实施方式3相同地，识别眼孔的外形，由此，可以得知引线接合识别图形的大致位置。接下来，识别成为引线接合基准的引线接合基准图形。在本实施方式中，使用电极端部105作为引线接合基准图形。接下来，识别形成在电极图形103上的引线接合识别图形107。此时，若需要，则改变照相机放大率，识别引线接合识别图形107。最后，进行引线接合。在使用该方法的情况下，暂时确认芯片的位置，所以，与实施方式3相比，能够准确地识别引线接合识别图形107的位置。此外，也可以将在电极图形103的四角之一所形成的缺口作为引线接合基准图形而在位置确认中使用。在本实施方式中，该缺口成为组合矩形后的形状，但是，也可以是圆形或三角形等其他形状。
实施方式5
本实施方式涉及识别引线接合识别图形并进行引线结合的其他方法。
首先，参考图1，识别眼孔的外形，由此，能够得知引线接合识别图形107的大致位置。接下来，识别形成在电极图形103上的引线接合识别图形107。此时，若需要，则改变照相机放大率，从而识别引线接合识别图形107。接下来，识别位于预想位置的电极端部105的图形，最后进行引线接合。在使用该方法的情况下，如实施方式3那样，除了能够检测粘结步骤中的位置错开以外，还能够立刻检测粘结了不同种类的激光二极管芯片时的不良。根据激光二极管芯片能够输出的光功率，激光二极管长度方向的长度不同，所以，在不同种类的芯片的情况下，不能够识别电极端部的图形，装置停止，所以，具有抑制继续产生不同种类芯片搭载不良引起的损失的效果。此外，也可以将在电极图形103的四角之一上所形成的缺口用于电极端部的确认。在本实施方式中，该缺口成为组合矩形后的形状，但是，也可以是圆形或三角形等其他形状。
并且，本发明涉及具有短边和长边的电极图形，但是，电极图形的短边方向的宽度W越小，激光二极管的中心线相对于眼孔的中心线的的倾斜错开引起的影响越大。在W较大的情况下，针对错开的容限变大，但是，W成为100μm以下时，该容限几乎不存在。因此，本发明在W为100μm以下的情况下特别有效。
并且，本发明对记录型高输出激光二极管进行了说明，但是，除此以外，也可应用于进行红色激光二极管或蓝紫色激光二极管、通信用激光二极管、LED、其他半导体装置、或者封装或衬底上等的布线图形等的引线接合的电极图形。

Claims (7)

1.一种具有短边和长边的引线接合用的电极，其特征在于，
具有电极端部和引线接合识别图形，该电极端部表示用于确定引线接合位置的基准位置，
并且，L和Lb满足如下关系，即，L≥14.3×(W-3d/4)
                             Lb≤14.3×(W-3d/4)
其中，
L是所述基准位置与下述的线之间的距离，即，该线为：在粘结于所述电极上的引线接合用的金属部位处、通过与所述短边平行的方向上的宽度为最大的位置且与所述短边平行的方向上的线，
Lb：通过所述电极的所述长边方向的所述引线接合识别图形的中心且与所述短边平行的方向上的线、和通过所述金属部位的与所述短边平行的方向上的宽度为最大的位置且与所述短边平行的方向上的线的距离，
d：在电极上所粘结的引线结合用金属部位的与所述短边平行的方向上的宽度最大值，
W：电极的与短边平行的方向上的宽度。
2.根据权利要求1的电极，其特征在于，
粘结在所述电极上的所述引线接合用金属部位是Au球。
3.根据权利要求1的电极，其特征在于，
粘结在所述电极上的所述引线接合用金属部位是用于楔形接合而挤压后的引线端部。
4.根据权利要求1的电极，其特征在于，
所述W为100μm以下。
5.一种对权利要求1的电极进行引线接合的引线接合方法，其特征在于，
在对封装外形进行识别之后，识别所述引线接合用识别图形，确定引线接合位置，进行引线接合。
6.一种对权利要求1的电极进行引线接合的引线接合方法，其特征在于，
在对封装外形进行识别之后，识别所述电极端部，并且，在识别所述引线接合用识别图形之后，进行引线接合。
7.一种对权利要求1的电极进行引线接合的引线接合方法，其特征在于，
在对封装外形进行识别之后，识别所述引线接合用识别图形，并且，在识别电极端的图形之后，进行引线接合。
CN2008100830350A 2007-03-19 2008-03-18 电极图形以及引线接合方法 Active CN101272034B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-070684 2007-03-19
JP2007070684 2007-03-19
JP2008008066A JP5176557B2 (ja) 2007-03-19 2008-01-17 電極パターンおよびワイヤボンディング方法
JP2008-008066 2008-01-17

Publications (2)

Publication Number Publication Date
CN101272034A CN101272034A (zh) 2008-09-24
CN101272034B true CN101272034B (zh) 2010-09-29

Family

ID=39985396

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100830350A Active CN101272034B (zh) 2007-03-19 2008-03-18 电极图形以及引线接合方法

Country Status (4)

Country Link
JP (1) JP5176557B2 (zh)
KR (1) KR100941106B1 (zh)
CN (1) CN101272034B (zh)
TW (1) TWI387171B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5441590B2 (ja) * 2009-09-29 2014-03-12 大王製紙株式会社 パンツタイプ使い捨ておむつ
JP6901902B2 (ja) * 2017-04-27 2021-07-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102706879B1 (ko) * 2021-12-24 2024-09-13 주식회사 유라코퍼레이션 Pcb기판

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1630189A (zh) * 2003-12-19 2005-06-22 Tdk株式会社 安装基板和使用它的电子部件

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291126A (ja) 1986-06-11 1987-12-17 Fuji Xerox Co Ltd パタ−ン認識マ−ク
JPS63133638A (ja) * 1986-11-26 1988-06-06 Toshiba Corp ワイヤボンデイング方法
JP2621420B2 (ja) * 1988-09-28 1997-06-18 日本電気株式会社 半導体装置のボンディングパッド
JP2992427B2 (ja) * 1993-07-16 1999-12-20 株式会社カイジョー ワイヤボンディング装置及びその方法
JP3611948B2 (ja) * 1997-05-16 2005-01-19 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
JP2982794B1 (ja) 1998-06-17 1999-11-29 日本電気株式会社 半導体装置
JP2001024303A (ja) 1999-07-09 2001-01-26 Nippon Avionics Co Ltd 認識マーク
JP4352579B2 (ja) * 2000-05-16 2009-10-28 沖電気工業株式会社 半導体チップ及びその製造方法
US6789724B2 (en) * 2001-07-06 2004-09-14 Erico International Corporation Welding apparatus and method
AU2003220938A1 (en) * 2002-05-28 2003-12-12 Hitachi Chemical Co., Ltd. Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them
US7042098B2 (en) 2003-07-07 2006-05-09 Freescale Semiconductor,Inc Bonding pad for a packaged integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1630189A (zh) * 2003-12-19 2005-06-22 Tdk株式会社 安装基板和使用它的电子部件

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
JP特开2000-12603A 2000.01.14
JP特开2001-21303A 2001.01.26
JP特开2001-326241A 2001.11.22
JP特开平10-321672A 1998.12.04

Also Published As

Publication number Publication date
TW200843265A (en) 2008-11-01
KR20080085687A (ko) 2008-09-24
JP2008263165A (ja) 2008-10-30
KR100941106B1 (ko) 2010-02-10
CN101272034A (zh) 2008-09-24
TWI387171B (zh) 2013-02-21
JP5176557B2 (ja) 2013-04-03

Similar Documents

Publication Publication Date Title
US20070081313A1 (en) Surface mounting semiconductor device
US20130171776A1 (en) Semiconductor device and method for manufacturing the same
CN100483660C (zh) 半导体器件及其测试方法
US20150262922A1 (en) Semiconductor device
JP2008186891A (ja) モールドパッケージおよびその製造方法ならびにモールドパッケージの実装構造
CN101272034B (zh) 电极图形以及引线接合方法
US8318548B2 (en) Method for manufacturing semiconductor device
US6107676A (en) Leadframe and a method of manufacturing a semiconductor device by use of it
WO1998043297A1 (fr) Substrat pour dispositif a semi-conducteurs, araignee de connexions, semi-conducteur et procede de fabrication des memes, carte et equipement electronique
US7179666B2 (en) Method for manufacturing an electronic circuit device and electronic circuit device
US10304759B2 (en) Electronic device and method of making same
US20080286959A1 (en) Downhill Wire Bonding for QFN L - Lead
US7550673B2 (en) Electrode pattern and wire bonding method
CN100505345C (zh) 发光二极管的引线架
JP5205189B2 (ja) 半導体装置の製造方法
JP2007309987A (ja) 光モジュール及びその製造方法
JP2010003909A (ja) 半導体装置の製造方法
EP3166142A1 (en) Bond wire connection and method of manufacturing the same
US20240234331A9 (en) Method of manufacturing semiconductor device
CN100565861C (zh) 半导体器件及其制造方法
JP2008091768A (ja) 半導体レーザ装置および電子機器
JP2021048234A (ja) 半導体レーザ光源装置
HK1249963A1 (zh) 製造半導體器件的方法
US20040262723A1 (en) Semiconductor device
EP1688771A1 (en) Optical modulator module

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant