CN101272034B - Electrode pattern and wire bonding method - Google Patents
Electrode pattern and wire bonding method Download PDFInfo
- Publication number
- CN101272034B CN101272034B CN2008100830350A CN200810083035A CN101272034B CN 101272034 B CN101272034 B CN 101272034B CN 2008100830350 A CN2008100830350 A CN 2008100830350A CN 200810083035 A CN200810083035 A CN 200810083035A CN 101272034 B CN101272034 B CN 101272034B
- Authority
- CN
- China
- Prior art keywords
- wire bonding
- electrode
- pattern
- recognized
- short side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 18
- 239000002184 metal Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 238000009434 installation Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 229920000535 Tan II Polymers 0.000 description 1
- 235000005811 Viola adunca Nutrition 0.000 description 1
- 240000009038 Viola odorata Species 0.000 description 1
- 235000013487 Viola odorata Nutrition 0.000 description 1
- 235000002254 Viola papilionacea Nutrition 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
In an installation way of a packaging member aiming at a basal table and a semiconductor chip bonded to bonding time on an eyelet, central lines of the eyelet and a laser diode are inclined on account of influence of precision of an assembly device, and Au ball for down-lead jointing is exposed outside an electrode. Electrode images for the down-lead jointing include down-lead jointing benchmark image and down-lead jointing identification image, distances between the down-lead jointing benchmark image and the down-lead jointing position, as well as between the down-lead jointing identification image and the down-lead jointing position are set as a predetermined value, therefore the down-lead jointing can be carried out excellently.
Description
Technical Field
The present invention relates to an electrode pattern and a wire bonding method for wire bonding to an electrode of a semiconductor device, a substrate, or the like.
Background
In wire bonding for connecting an electrode and a metal wire, it is necessary to teach (teaching) a bonding position in a bonding apparatus. In general, when wire bonding is performed using an Au ball or the like, the Au ball is designed to be sufficiently accommodated in an electrode for wire bonding. In a wire bonding step in the manufacture of a semiconductor device, as a technique for identifying a place where a wire bonding device should perform wire bonding, there is a technique described in japanese unexamined patent application, first publication No. 2001-326241.
When a laser diode is wire bonded, an electrode pattern for wire bonding is formed in an elongated shape. In the recording laser diode, the light output required of the laser diode is increasing with the increase of the double speed at the time of recording, and on the other hand, the demand for the price reduction is very strong. In response to these demands, the length of the laser diode in the vertical direction is increased to obtain high output, and the length of the laser diode in the horizontal direction is shortened to reduce the cost, thereby increasing the number of chips to be obtained from a single wafer. Thus, for example, in the case of a 350mW class recording high-power laser diode, the laser diode has a very long and thin shape having a vertical length of more than 2000 μm and a lateral length of 150 μm or less.
In a package mounting method of a recording high-power laser diode, a submount (submount) and the laser diode are connected to an eyelet (eyelet) by AuSn solder or the like. Further, the electrodes of the laser diode are wire-bonded to the lead wires or the eyelets, but in order to form the Au balls at predetermined positions on the electrodes, the characteristic patterns of the electrode ends are recognized, and then the Au balls are bonded at positions shifted by a predetermined amount in the longitudinal direction of the laser. It is known that when the submount and the laser diode are bonded to the eyelet, the center line of the eyelet and the center line of the laser diode are inclined at about 2 ° at maximum due to the influence of the accuracy of the assembly apparatus.
Japanese patent application laid-open No. 2001-326241 of patent document 1
In the case where there is no tilt in the laser diode center and the center of the eyelet, the Au ball may be bonded at the center of the electrode. However, when the inclination is made, there is a problem that the Au ball is exposed to the outside of the electrode. When the length of the electrode in the longitudinal direction is long and the length of the electrode in the short side direction (electrode width) is short, the displacement in the short side direction becomes large, and the amount of the Au ball exposed becomes large. If the Au ball is formed in the vicinity of the electrode end, the amount of the Au ball exposed due to the tilt error can be reduced, but in this case, there is a problem as follows: in a place away from the vicinity of the Au ball, the current density that can be supplied to the laser diode changes, and the laser diode is difficult to operate normally. Thus, the Au ball needs to be formed near the center of the laser diode. This effect is more pronounced when Au balls are formed on a long and narrow electrode pattern, as in a recording-type high-output laser diode.
Disclosure of Invention
The present invention has been made to solve the above-described problems, and provides an electrode pattern and a wire bonding method capable of performing wire bonding with high accuracy.
The electrode pattern of the present invention is an electrode pattern for wire bonding having a short side and a long side,
having a wire bonding reference pattern representing a reference position for determining a wire bonding position and a wire bonding identification pattern,
and L and Lb satisfy the relationship that L.gtoreq.14.3 × (W-3d/4)
Lb≤14.3×(W-3d/4),
Wherein,
l is the distance between the reference position and the line: a line passing through a position where the width in a direction parallel to the short side is maximum and in a direction parallel to the short side at a metal portion for wire bonding bonded to the electrode pattern,
lb: a distance between a line passing through a position of the metal portion where a width in a direction parallel to the short side is maximum and a line passing through a direction parallel to the short side, the line being parallel to the short side at a center in the long side direction of the recognition pattern by wire bonding,
d: the maximum value of the width of the wire bonding metal portion bonded to the electrode pattern in the direction parallel to the short side,
w: a width of the electrode pattern in a direction parallel to the short side.
Drawings
Fig. 1 is a schematic view showing an electrode pattern according to an embodiment of the present invention.
Fig. 2 is a schematic view showing a semiconductor element using an electrode pattern according to an embodiment of the present invention.
Fig. 3 is a schematic diagram showing an electrode pattern according to the embodiment of the present invention.
Fig. 4 is a schematic diagram showing an electrode pattern according to the embodiment of the present invention.
Fig. 5 is a schematic view showing an electrode pattern according to the embodiment of the present invention.
Detailed Description
Embodiment mode 1
Fig. 1 is a schematic diagram showing an electrode pattern for wire bonding according to the embodiment of the present invention. Fig. 2 is a schematic view showing a semiconductor device using an electrode pattern for wire bonding according to an embodiment of the present invention. Next, description will be given with reference to fig. 1 and 2. In the figure, 101 denotes a semiconductor substrate, 203 denotes a submount, and 209 denotes insulating glass. In the embodiments of the present invention, a semiconductor element that is wire-bonded on an elongated laser diode chip is taken as an example. On the laser diode chip, an electrode pattern 103 for wire bonding is formed. In a region 111 where wire bonding is performed on the electrode pattern 103, an Au ball 109 having a diameter d is formed and wire bonding is performed. At this time, in a state where the center of the eyelet 201 and the center of the laser diode 205 are not obliquely shifted (θ is 0) shown in fig. 2, the Au ball 109 is formed so that the center is on a line in the longitudinal direction passing through the center in the direction parallel to the short side of the electrode pattern 103, and wire bonding is performed. A characteristic pattern to be a wire bonding recognition pattern 107 is formed on the electrode pattern 103. In this embodiment, a rectangular cutout is formed in one side in the longitudinal direction of the electrode pattern 103 as the wire bonding recognition pattern 107. Each size is determined in the following manner.
L: the shortest distance between the edge portion of the electrode pattern (electrode end portion 105) and the center of the Au ball 109 formed on the wire bonding region 111,
lb: by the shortest distance between the line in the direction parallel to the short side at the center in the long side direction of the wire bonding recognition pattern 107 and the center of the Au ball 109 formed on the wire bonding area 111,
d: the diameter of the Au ball 109 is such that,
w: the width of the electrode pattern 103 in the direction parallel to the short side,
the amount of the inclination shift θ between the center of the eye 201 and the center of the laser diode 205 is 2 ° at maximum, compared with the assembly accuracy. When the amount of exposure from wire bonding region 111 when forming Au ball 109 on wire bonding region 111 is x, x is expressed by the following equation.
x=d/2-W/2+Ltanθ
When the exposure amount x is allowed to d/8, tan2 ° -0.0349, L and Lb are expressed by the following expressions, respectively.
L=14.3×(W-3d/4)
Lb=14.3×(W-3d/4)
In the present embodiment, the electrode end portion 105 is used as a wire bonding reference pattern serving as a reference for determining a wire bonding position. The wire bonding is performed at a position where the distance L between the wire bonding reference pattern and the center of the Au ball 109 having the diameter d in the wire bonding region 111 is not less than 14.3 (W-3 d/4). At this time, the positioning is performed in such a manner that the distance Lb between the center of the wire bonding recognition pattern 107 formed on the electrode pattern 103 in the longitudinal direction and the line in the direction parallel to the short side and the center of the Au ball 109 is Lb ≦ 14.3 × (W-3d/4) (μm). Taking a recording-type high-output laser diode as an example, the length of the laser diode in the longitudinal direction was 2000 μm and the width was 120 μm, the width of the electrode was 80 μm, the diameter of the Au ball was 80 ± 10 μm, and the L was about 286 μm, and when no wire bonding recognition pattern was provided, the Au ball could be formed only at the end of the elongated electrode, and the density of the injected current was changed at the upper end and the lower end of the electrode, and the operation of the laser diode was unstable. The wire bonding recognition pattern of the present invention is formed at a desired position, whereby unevenness in the density of the injected current can be easily eliminated.
In the present embodiment, the electrode end 105 is used as the wire bonding reference pattern, but a characteristic pattern in the electrode other than the electrode end can be used as the wire bonding reference pattern. For example, a notch for checking the front and rear sides of the chip may be formed at one of the four corners of the electrode pattern 103, and this notch may be used as a wire bonding reference pattern. In the present embodiment, the notch has a shape in which rectangles are combined, but other shapes such as a circle and a triangle may be used. In the present embodiment, the Au ball 109 is formed and wire bonding is performed, but in the case of wedge bonding, the Au ball is not formed, and the wire is bonded by ultrasonic pressure bonding to the lead end.
Embodiment mode 2
Fig. 3 and 4 are schematic diagrams of electrode patterns for wire bonding according to embodiment 2 of the present invention. In embodiment 1, the wire bonding recognition pattern 107 is formed in a rectangular notch pattern as shown in fig. 1, but in the present embodiment, the wire bonding recognition pattern is formed in a circular recognition pattern shape as shown in fig. 3 or in a triangular shape as shown in fig. 4. In the case where the wire bonding recognition pattern 307 having a circular shape is made small or an etching method with low processing accuracy is used, even if etching sagging occurs, the shape is not changed to a circular shape, and recognition errors can be prevented. In the case of the triangular wire bonding recognition pattern 407, the length of the straight portion can be made longer than that of a rectangular shape having the same size, and therefore, there is an effect that the influence of pattern collapse due to etching sagging or the like can be reduced.
The wire bonding recognition patterns 307 and 407 are formed on one side portion in the longitudinal direction of the electrode patterns 303 and 403, and thus can be easily formed by lift-off. In addition, in the case of using a method such as etching, as shown in fig. 5, the wire bonding recognition pattern 507 may be formed inside the electrode pattern 503.
Embodiment 3
The present embodiment relates to a method of recognizing a wire bonding recognition pattern and performing wire bonding.
Referring to fig. 1 and 2, the outline of the eyelet 201 is recognized, and the approximate position of the wire bonding recognition pattern 107 can be known. Next, the wire bonding recognition pattern 107 formed on the electrode pattern 103 is recognized. At this time, if necessary, the magnification of the camera (camera) is changed to recognize the wire bonding recognition pattern 107. Finally, the wires 211 and 213 are wire-bonded to connect the wires 207 and GND. In the case of using this method, when the laser diode 205 on the eyelet 201 is displaced from a predetermined position due to a setting error, a misalignment failure, or the like, or a positioning jig failure, it can be immediately found. That is, after the eyelet outline is recognized, the recognition pattern is not wire-bonded at the expected position, and therefore the apparatus is stopped. This can minimize the production of defective products due to positional shifts in the laser diode bonding step, and therefore has the effect of suppressing the loss due to the continued production of defective products.
Embodiment 4
The present embodiment relates to another method of recognizing a wire bonding recognition pattern and performing wire bonding.
As in embodiment 3, the outline of the eyelet is recognized, and the approximate position of the wire bonding recognition pattern can be known. Next, a wire bonding reference pattern to be a wire bonding reference is identified. In the present embodiment, the electrode end portion 105 is used as a wire bonding reference pattern. Next, the wire bonding recognition pattern 107 formed on the electrode pattern 103 is recognized. At this time, if necessary, the camera magnification is changed to recognize the wire bonding recognition pattern 107. Finally, wire bonding is performed. In the case of using this method, the position of the chip is temporarily confirmed, and therefore, the position of the wire bonding recognition pattern 107 can be accurately recognized as compared with embodiment 3. Further, the notch formed at one of the four corners of the electrode pattern 103 may be used as a wire bonding reference pattern for position confirmation. In the present embodiment, the notch has a shape in which rectangles are combined, but may have another shape such as a circle or a triangle.
Embodiment 5
The present embodiment relates to another method of recognizing a wire bonding recognition pattern and performing wire bonding.
First, referring to fig. 1, the outline of the eyelet is recognized, and thereby the approximate position of the wire bonding recognition pattern 107 can be known. Next, the wire bonding recognition pattern 107 formed on the electrode pattern 103 is recognized. At this time, if necessary, the camera magnification is changed to recognize the wire bonding recognition pattern 107. Next, the pattern of the electrode end 105 located at the expected position is recognized, and finally, wire bonding is performed. In the case of using this method, as in embodiment 3, it is possible to detect a positional shift in the bonding step and also to detect a defect at once when a different type of laser diode chip is bonded. Since the length of the laser diode in the longitudinal direction is different depending on the optical power that can be output from the laser diode chip, the pattern of the electrode end cannot be recognized and the apparatus is stopped when the chip is of a different type, and therefore, there is an effect of suppressing the loss due to the continued occurrence of a mounting failure of a chip of a different type. Further, the notch formed at one of the four corners of the electrode pattern 103 may be used for confirmation of the electrode end. In the present embodiment, the notch has a shape in which rectangles are combined, but may have another shape such as a circle or a triangle.
The present invention also relates to an electrode pattern having a short side and a long side, but the smaller the width W in the short side direction of the electrode pattern, the greater the influence of the inclination shift of the center line of the laser diode with respect to the center line of the eyelet. When W is large, the margin for misalignment increases, but when W is 100 μm or less, the margin is almost nonexistent. Therefore, the present invention is particularly effective when W is 100 μm or less.
Further, although the present invention has been described with respect to a recording type high-output laser diode, the present invention is also applicable to an electrode pattern for wire bonding such as a red laser diode, a blue-violet laser diode, a laser diode for communication, an LED, another semiconductor device, or a wiring pattern on a package or a substrate.
Claims (7)
1. An electrode for wire bonding having a short side and a long side,
having an electrode tip representing a reference position for determining a wire bonding position and a wire bonding recognition pattern,
and L and Lb satisfy the relationship that L.gtoreq.14.3 × (W-3d/4)
Lb≤14.3×(W-3d/4)
Wherein,
l is the distance between the reference position and the line: a line passing through a position where the width in a direction parallel to the short side is maximum and in a direction parallel to the short side at a metal portion for wire bonding bonded to the electrode,
lb: a distance between a line passing through the center of the wire bonding recognition pattern in the longitudinal direction of the electrode and extending in a direction parallel to the short side and a line passing through a position of the metal portion where the width in the direction parallel to the short side is maximum and extending in the direction parallel to the short side,
d: the maximum value of the width of the wire bonding metal portion bonded to the electrode in the direction parallel to the short side,
w: the width of the electrode in a direction parallel to the short sides.
2. The electrode according to claim 1,
the metal portion for wire bonding bonded to the electrode is an Au ball.
3. The electrode according to claim 1,
the metal portion for wire bonding bonded to the electrode is a wire end portion extruded for wedge bonding.
4. The electrode according to claim 1,
the W is 100 μm or less.
5. A wire bonding method of wire bonding the electrode according to claim 1,
after the package outer shape is recognized, the recognition pattern for wire bonding is recognized, the wire bonding position is determined, and wire bonding is performed.
6. A wire bonding method of wire bonding the electrode according to claim 1,
after the package outer shape is recognized, the electrode end portion is recognized, and after the recognition pattern for wire bonding is recognized, wire bonding is performed.
7. A wire bonding method of wire bonding the electrode according to claim 1,
after the package outer shape is recognized, the recognition pattern for wire bonding is recognized, and after the pattern of the electrode terminal is recognized, wire bonding is performed.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-070684 | 2007-03-19 | ||
JP2007070684 | 2007-03-19 | ||
JP2008-008066 | 2008-01-17 | ||
JP2008008066A JP5176557B2 (en) | 2007-03-19 | 2008-01-17 | Electrode pattern and wire bonding method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101272034A CN101272034A (en) | 2008-09-24 |
CN101272034B true CN101272034B (en) | 2010-09-29 |
Family
ID=39985396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008100830350A Active CN101272034B (en) | 2007-03-19 | 2008-03-18 | Electrode pattern and wire bonding method |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP5176557B2 (en) |
KR (1) | KR100941106B1 (en) |
CN (1) | CN101272034B (en) |
TW (1) | TWI387171B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5441590B2 (en) * | 2009-09-29 | 2014-03-12 | 大王製紙株式会社 | Pants-type disposable diaper |
JP6901902B2 (en) * | 2017-04-27 | 2021-07-14 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and their manufacturing methods |
KR102706879B1 (en) * | 2021-12-24 | 2024-09-13 | 주식회사 유라코퍼레이션 | Printed Circuit Board |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1630189A (en) * | 2003-12-19 | 2005-06-22 | Tdk株式会社 | Mounting substrate and electronic component using the same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62291126A (en) | 1986-06-11 | 1987-12-17 | Fuji Xerox Co Ltd | Pattern recognition mark |
JPS63133638A (en) * | 1986-11-26 | 1988-06-06 | Toshiba Corp | Wire bonding |
JP2621420B2 (en) * | 1988-09-28 | 1997-06-18 | 日本電気株式会社 | Bonding pads for semiconductor devices |
JP2992427B2 (en) * | 1993-07-16 | 1999-12-20 | 株式会社カイジョー | Wire bonding apparatus and method |
JP3611948B2 (en) * | 1997-05-16 | 2005-01-19 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor device and manufacturing method thereof |
JP2982794B1 (en) | 1998-06-17 | 1999-11-29 | 日本電気株式会社 | Semiconductor device |
JP2001024303A (en) | 1999-07-09 | 2001-01-26 | Nippon Avionics Co Ltd | Recognition mark |
JP4352579B2 (en) * | 2000-05-16 | 2009-10-28 | 沖電気工業株式会社 | Semiconductor chip and manufacturing method thereof |
US6789724B2 (en) * | 2001-07-06 | 2004-09-14 | Erico International Corporation | Welding apparatus and method |
WO2003100850A1 (en) * | 2002-05-28 | 2003-12-04 | Hitachi Chemical Co., Ltd. | Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them |
US7042098B2 (en) | 2003-07-07 | 2006-05-09 | Freescale Semiconductor,Inc | Bonding pad for a packaged integrated circuit |
-
2008
- 2008-01-17 JP JP2008008066A patent/JP5176557B2/en active Active
- 2008-03-04 TW TW097107465A patent/TWI387171B/en active
- 2008-03-05 KR KR1020080020362A patent/KR100941106B1/en active Active
- 2008-03-18 CN CN2008100830350A patent/CN101272034B/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1630189A (en) * | 2003-12-19 | 2005-06-22 | Tdk株式会社 | Mounting substrate and electronic component using the same |
Non-Patent Citations (4)
Title |
---|
JP特开2000-12603A 2000.01.14 |
JP特开2001-21303A 2001.01.26 |
JP特开2001-326241A 2001.11.22 |
JP特开平10-321672A 1998.12.04 |
Also Published As
Publication number | Publication date |
---|---|
TW200843265A (en) | 2008-11-01 |
CN101272034A (en) | 2008-09-24 |
KR100941106B1 (en) | 2010-02-10 |
KR20080085687A (en) | 2008-09-24 |
JP5176557B2 (en) | 2013-04-03 |
TWI387171B (en) | 2013-02-21 |
JP2008263165A (en) | 2008-10-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20070081313A1 (en) | Surface mounting semiconductor device | |
CN101981679B (en) | Bonding apparatus and bonding method | |
CN100483660C (en) | Semiconductor device, method and apparatus for testing same, and method for manufacturing semiconductor device | |
US20150262922A1 (en) | Semiconductor device | |
CN101272034B (en) | Electrode pattern and wire bonding method | |
US8318548B2 (en) | Method for manufacturing semiconductor device | |
WO1998043297A1 (en) | Substrate for semiconductor device, lead frame, semiconductor device and method for manufacturing the same, circuit board, and electronic equipment | |
GB2323474A (en) | A leadframe for a semiconductor device | |
US7179666B2 (en) | Method for manufacturing an electronic circuit device and electronic circuit device | |
US10304759B2 (en) | Electronic device and method of making same | |
US20080286959A1 (en) | Downhill Wire Bonding for QFN L - Lead | |
US7550673B2 (en) | Electrode pattern and wire bonding method | |
CN100505345C (en) | Lead frame of light-emitting diode | |
JP5205189B2 (en) | Manufacturing method of semiconductor device | |
JP2007309987A (en) | Optical module and manufacturing method therefor | |
JP2010003909A (en) | Method of manufacturing semiconductor device | |
JP4430062B2 (en) | IC chip mounting package manufacturing method | |
EP3166142A1 (en) | Bond wire connection and method of manufacturing the same | |
US20240234331A9 (en) | Method of manufacturing semiconductor device | |
CN100565861C (en) | Semiconductor device and manufacture method thereof | |
JP2008091768A (en) | Semiconductor laser device, and electronic instrument | |
JP2021048234A (en) | Semiconductor laser light source device | |
HK1249963A1 (en) | Method of manufacturing semiconductor device | |
US20040262723A1 (en) | Semiconductor device | |
EP1688771A1 (en) | Optical modulator module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |