CN100550396C - Pixel and forming method thereof, storage capacitor, display panel and photoelectric device - Google Patents

Abstract

A pixel and a method for forming the same, as well as a storage capacitor, a display panel and an optoelectronic device. The storage capacitor is disposed on a substrate, and the storage capacitor includes a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is disposed on the substrate, the first dielectric layer covers the semiconductor layer and the substrate, and the first conductive layer is partially disposed on the first dielectric layer. The second dielectric layer is disposed on the first conductive layer, and the sides of the second dielectric layer and the first conductive layer have an inclination. The second conductive layer is partially disposed on the second dielectric layer. The present invention can increase the capacitance value of the storage capacitor and maintain the stability of the pixel image.

Description

Pixel and its forming method, storage capacitor, display panel and optoelectronic device

technical field

The invention relates to a flat panel display, in particular to a storage capacitor of the flat panel display.

Background technique

The display area of a flat panel display is composed of several pixels. Each pixel has a pixel electrode and a thin film transistor connected to the pixel electrode, and the signal line transmits a signal to the thin film transistor to turn on or off. After the pixel electrode provides the voltage, the thin film transistor will be turned off until the voltage is written into or deleted from the pixel electrode again when the thin film transistor is turned on by the scan line next time.

However, in order to maintain the voltage originally written into the pixel electrode before the next scan line turns on the thin film transistor, a storage capacitor (Storage Capacitor, C _st ) is needed to increase the overall capacitance, so that the voltage written into the pixel electrode can be kept constant. longer time. The amount of electricity that a storage capacitor can store is proportional to the area of its two electrodes and inversely proportional to the distance between its two electrodes.

使得存储电容的电量的存储能力受到进一步的限制。为了能提升存储电容的电容值，以保持像素呈像的稳定性成为一重要的课题。However, due to the increasingly higher requirements for product resolution, the pixel size is gradually reduced. In order not to affect the aperture ratio, the area of the storage capacitor must be compressed, resulting in a decrease in capacitance. In addition, the thickness of the dielectric layer of the storage capacitor manufactured by the known manufacturing process must be at least greater than 3000 angstroms

The storage capacity of the electric quantity of the storage capacitor is further restricted. In order to increase the capacitance of the storage capacitor, maintaining the stability of the pixel image becomes an important issue.

Contents of the invention

The invention provides a storage capacitor and a manufacturing method thereof, which can increase the capacitance value of the storage capacitor.

The present invention proposes a storage capacitor, which includes a semiconductor layer disposed on a substrate, a first dielectric layer covering the semiconductor layer and the substrate, a first conductive layer disposed on part of the first dielectric layer, and disposed on the second dielectric layer. A second dielectric layer on a conductive layer, and a second conductive layer disposed on part of the second dielectric layer. The stacked sides of the second dielectric layer and the first conductive layer have a taper.

The storage capacitor as described above, wherein at least one of the first conductive layer and the second conductive layer comprises a transparent material, a non-transparent material, or a combination thereof.

In the above storage capacitor, at least one of the first dielectric layer and the second dielectric layer comprises organic material, inorganic material or a combination thereof.

The storage capacitor as described above, wherein the semiconductor layer comprises single crystal silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, or a combination thereof.

The above-mentioned storage capacitor, wherein the semiconductor layer is doped with N-type, P-type or a combination thereof.

In the above storage capacitor, the semiconductor layer includes at least one first doped region and at least one non-doped region.

In the above storage capacitor, the semiconductor layer includes at least one first doped region, at least one non-doped region and at least one lightly doped region.

The above storage capacitor, further comprising an etching stop layer having at least a first portion disposed on a portion of the second dielectric layer.

The storage capacitor as described above, further comprising an etch stop layer having at least one first portion and at least one second portion, the first portion is disposed on one of the two ends of the second dielectric layer, and the second portion It is disposed on the other end away from the second dielectric layer.

The storage capacitor as described above, wherein the thickness of the second dielectric layer is substantially less than 3000 angstroms

The storage capacitor as described above, wherein the thickness of the second dielectric layer is substantially less than 1000 angstroms

至3000埃 The above-mentioned storage capacitor, wherein the thickness of the second dielectric layer is substantially between 200 angstroms

to 3000 Angstroms

The above storage capacitor, wherein the second conductive layer is electrically connected to the semiconductor layer.

The above storage capacitor, wherein the etch stop layer includes a silicon-containing material layer.

The storage capacitor proposed by the present invention is suitable for a kind of pixel. The pixel is arranged on the substrate and includes a switching element area and a capacitor area. The pixel includes a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer, an inner dielectric layer, a source/drain, a protection layer and a second conductive layer. The semiconductor layer is arranged on the substrate, and the first dielectric layer covers the semiconductor layer and the substrate. The first conductive layer is respectively disposed on the first dielectric layer in the switching element area and the capacitor area. The second dielectric layer is located on the first conductive layer. Part of the etch stop layer is disposed on the second dielectric layer in the switching element region. The inner dielectric layer covers the substrate. The source/drain is disposed on a part of the inner dielectric layer of the switching element region, and is electrically connected to the semiconductor layer on the switching element region. A protective layer is used to cover the substrate. The second conductive layer is disposed on a part of the protective layer, and is electrically connected to one of the source/drain electrodes, and is disposed on a part of the second dielectric layer through at least one opening in the protective layer and the inner dielectric layer. .

The aforementioned pixel, wherein at least one of the first conductive layer and the second conductive layer comprises a transparent material, a non-transparent material, or a combination thereof.

In the aforementioned pixel, at least one of the first dielectric layer, the second dielectric layer and the inner dielectric layer comprises organic material, inorganic material or a combination thereof.

The aforementioned pixel, wherein the semiconductor layer comprises single crystal silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, or a combination thereof.

The aforementioned pixel, wherein at least one of the semiconductor layer on the switching element region and the capacitor region is doped with N-type, P-type semiconductor layer or a combination thereof.

The aforementioned pixel, wherein at least one of the switching element region and the semiconductor layer on the capacitor region includes at least one first doped region and at least one non-doped region.

The above pixel, wherein at least one of the switching element region and the semiconductor layer on the capacitor region includes at least one first doped region, at least one non-doped region and at least one lightly doped region.

The aforementioned pixel, wherein another part of the etch stop layer has at least a first part disposed on a part of the second dielectric layer.

The above pixel, wherein another part of the etch stop layer has at least one first part and at least one second part, the first part is arranged on one of the two ends of the second dielectric layer, and the second part is arranged on on the other end away from the second dielectric layer.

The above pixel, wherein the etch stop layer includes a silicon-containing material layer.

The aforementioned pixel, wherein the stacked sides of the second dielectric layer and the first conductive layer substantially have a taper.

The pixel as above, wherein the thickness of the second dielectric layer is substantially less than 3000 Angstroms

The pixel as above, wherein the thickness of the second dielectric layer is substantially less than 1000 Angstroms

至3000埃 The pixel as described above, wherein the thickness of the second dielectric layer is substantially between 200 Angstroms

to 3000 Angstroms

The aforementioned pixel further includes a connecting layer for electrically connecting the switching element region and the semiconductor layer on the capacitor region.

The aforementioned pixel, wherein the connecting layer comprises single crystal silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, transparent material, non-transparent material, or a combination thereof.

The pixel provided by the present invention is applicable to a display panel, and the display panel includes the above-mentioned pixel and signal lines.

The display panel provided by the invention is suitable for being assembled into a display. The display includes a backlight source and the above-mentioned display panel. The backlight is the main source of light for the display.

The display provided by the invention can be applied to an optoelectronic device. The optoelectronic device includes electronic components and the above-mentioned display.

The invention further provides a manufacturing method of a pixel, the pixel is arranged on a substrate and has a switching element area and a capacitor area. The method includes: forming at least one semiconductor layer on the substrate of the switching element region and the capacitor region; forming at least one first dielectric layer to cover the semiconductor layer and the substrate; sequentially forming at least one first conductive layer, at least one second a dielectric layer and at least one etch stop layer on the first dielectric layer; patterning the first conductive layer, the second dielectric layer and the etch stop layer to form a gate stack on the switching element area and on the capacitor area forming a capacitor stack; forming at least one inner dielectric layer to cover the gate stack, the capacitor stack and the first dielectric layer; forming at least one source/drain on a part of the inner dielectric layer in the switching element region, wherein The source/drain is electrically connected to the semiconductor layer in the switching element region; at least one protective layer is formed to cover the source/drain and the inner dielectric layer; the protective layer and the inner dielectric layer are patterned to form a contact window and opening in the protection layer, and the opening exposes the etching stop layer; selectively etching the etching stop layer until part of the second dielectric layer is exposed; and forming at least one second conductive layer on part of the protection layer, wherein The second conductive layer is electrically connected to one of the source/drain electrodes through the contact window, and is disposed on the exposed part of the second dielectric layer through the opening in the protective layer.

The above forming method, wherein at least one of the first conductive layer and the second conductive layer comprises a transparent material, a non-transparent material, or a combination thereof.

The above forming method, wherein at least one of the first dielectric layer, the second dielectric layer and the inner dielectric layer comprises organic material, inorganic material or a combination thereof.

The forming method as described above, wherein the semiconductor layer comprises single crystal silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, or a combination thereof.

The above forming method, wherein at least one of the semiconductor layer on the switching element region and the capacitor region is doped with N-type, P-type semiconductor layer or a combination thereof.

The forming method as described above, wherein at least one of the switching element region and the semiconductor layer on the capacitor region includes at least one first doped region and at least one non-doped region.

The above forming method, wherein at least one of the semiconductor layer on the switching element region and the capacitor region includes at least one first doped region, at least one non-doped region and at least one lightly doped region.

The above forming method, wherein the etch stop layer includes a silicon-containing material layer.

The above forming method, wherein the stacked sides of the second dielectric layer and the first conductive layer substantially have a slope.

The forming method as described above, wherein the thickness of the second dielectric layer is substantially less than 3000 Angstroms

The forming method as described above, wherein the thickness of the second dielectric layer is substantially less than 1000 Angstroms

至3000埃 The forming method as described above, wherein the thickness of the second dielectric layer is substantially 200 angstroms

to 3000 Angstroms

The above forming method, wherein the gate stack includes the first conductive layer, the second dielectric layer and the etch stop layer.

The forming method as described above, wherein the first conductive layer, the second dielectric layer and the etch stop layer are patterned so as to form a gate stack on the switching element region and a capacitor on the capacitor region During the stacking step, a yellow light process using masks with different transmittances is used to remove part of the etch stop layer on the gate stack.

The above forming method, wherein the gate stack includes the first conductive layer.

The above forming method, wherein the etch stop layer has a thickness of about 200 angstroms to about 3000 angstroms.

The above forming method, wherein, in the step of patterning the passivation layer and the ILD layer, the ILD layer and the etch stop layer have different etching rates.

The forming method as described above, wherein, in the step of selectively etching the etch stop layer, the etch stop layer and the second dielectric layer have different etching rates.

以下，使电容量大为提升外，还可依需求自行控制电容介电层的厚度，同时保有较佳的开口率。The invention can increase the capacitance value of the storage capacitor and maintain the stability of the pixel image. Compared with traditional storage capacitors, the above storage capacitors can not only reduce the thickness of the dielectric layer to 3000 Angstroms

In addition to greatly improving the capacitance, the thickness of the dielectric layer of the capacitor can also be controlled according to the requirements, while maintaining a better aperture ratio.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail with accompanying drawings.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the detailed description of the accompanying drawings is as follows:

FIG. 1 shows a top view of a pixel in a liquid crystal display according to an embodiment of the present invention.

2A-2E show top views of various layers of the pixel of FIG. 1 .

FIG. 3 shows a cross-sectional view of the pixel of FIG. 1 along line AA'.

4A-4F show cross-sectional views of the pixel of FIG. 3 at various process stages.

FIG. 5 shows a top view of a dual-gate pixel according to one embodiment of the present invention.

Fig. 6 is a schematic diagram of an optoelectronic device of the present invention.

Wherein, the reference signs are explained as follows:

100: pixel 102: switching element area

104: capacitor area 106: substrate

107: lightly doped region 108: semiconductor layer

109: channel region 110: first dielectric layer

112: first conductive layer 113: residual layer

114: Second dielectric layer 115: Residual layer

116: Sacrificial layer 117: Capacitor stack

118: Gate stack 120: Inner dielectric layer

122: source/drain 124: source/drain

126: protective layer 128: opening

130: Contact window 132: Pixel electrode

132a: Electrode 136: Signal line

134: Scanning line 140: Gate

138: grid 200: photoelectric device

210: Display panel 220: Electronic components

Detailed ways

Please refer to FIG. 1 , which shows a schematic top view of pixels in a liquid crystal display according to an embodiment of the present invention. In FIG. 1 , the pixel 100 is located on the substrate 106 in an area divided by the intersection of scan lines 134 and signal lines 136 , and has a switching element area 102 and a capacitor area 104 . In this embodiment, a capacitor stack 117 is provided at the capacitor area 104, and a thin film transistor is provided at the switching element area 102 for switching control of the pixel, wherein the gate stack 118 of the thin film transistor is connected to the scan line 134 The source/drain 122 is electrically connected to the signal line 136 and the semiconductor layer 108 at the switching element region 102, and the other source/drain 124 is electrically connected to the semiconductor layer 108 at the capacitor region 104 and the pixel electrode 132. sexual connection. In addition, the capacitor stack 117 at the capacitor region 104 is used as a storage capacitor. The capacitor stack 117 includes a part of the semiconductor layer 108, a part of the first conductive layer 112, an electrode 132a, and a dielectric layer (not shown) between two electrodes, wherein the electrode 132a is a part of the pixel electrode 132 .

2A-2E show top views of various layers of the pixel shown in FIG. 1 . As shown in FIG. 2A, firstly, there is a semiconductor layer 108 on the substrate 106, and the semiconductor layer 108 at the switching element region 102 pre-defines where the semiconductor layer 108 is the first doped region 105 and the channel region 109. , and the channel region 109 is also called an undoped region because it is not doped with any impurities.

Please refer to FIG. 2B, an insulating layer (not shown) formed by a first dielectric layer is provided on the semiconductor layer 108, and a first conductive layer 112, a second conductive layer 112, and a second Dielectric layer (not shown) and sacrificial layer (not shown). On the channel region 109 of the semiconductor layer 108 at the switching element region 102 , a gate stack 118 is disposed, and the gate stack 118 is connected to the scan line 134 . In this embodiment, after the first conductive layer is formed, that is, after the gate stack 118 is formed, the semiconductor layer is pre-defined by the first doping process where the first doped region 105 and the trench are defined. Where the channel region 109 is located, the first doped region and the channel region are formed as an example. In addition, in one of the two sides of the channel region 109 , the second doping process is performed using the gate stack 118 as a mask to selectively define the doped region 107 . Since the concentration of the doped region 107 is preferably substantially lower than that of the first doped region 105 , it is also called a lightly doped region 107 . The first doped region 105 is also called a heavily doped region or a source/drain region. Although the first doped region 105 , the channel region 109 and the lightly doped region 107 are formed at different times in this embodiment, they can also be formed at the same time. Secondly, the formation of the first doped region 105, the lightly doped region 107 and the channel region 109 can also be optionally formed by a yellow light process and an ion implantation process before the formation of the gate stack 118, for example: forming a light The photoresist is placed on the semiconductor layer 108 or the first dielectric layer, and the photoresist is formed into steps or slopes through the exposure process, and the first doping process is used to simultaneously form the first The doped region 105, the lightly doped region 107 and the channel region 109 may be formed by a yellow light process and an ion implantation process before the gate stack 118 is formed, for example: forming a photoresist in the first On the dielectric layer or the first conductive layer, the first dielectric layer and/or the first conductive layer are formed into a step (stepped) or a slope (taper) through the yellow light and etching process, and the first doping process is used to At the same time, the first doped region 105 , the lightly doped region 107 and the channel region 109 are formed. Secondly, the lightly doped region 107, the first doped region 105, and the channel region 109 are formed at different times. After the electrical layer is formed and one of the first conductive layer is formed, a photoresist is formed on the semiconductor layer 108, one of the first dielectric layer and the first conductive layer, and the photoresist is made through the exposure process. The predetermined lightly doped region 107 is exposed by the doping agent, and the lightly doped region 107 is formed by the second doping process.

Next, as shown in FIG. 2C , an interlayer dielectric layer (not shown) is provided on the substrate 106 to cover all the above-mentioned formed elements. On the inner layer dielectric layer on the side of the gate stack 118 away from the capacitor region 104 , there is provided a source/drain 122 electrically connected to the signal line 136 and the first doped region 105 of the semiconductor layer 108 . On the inner layer dielectric layer on the other side of the gate stack 118 close to the capacitor region 104, a source/drain 124 is electrically connected to the first doped region 105 of the semiconductor layer through a hole (not marked). .

Next, as shown in FIG. 2D , a protective layer (not shown) is disposed on the substrate to cover all components. And an opening 128 is formed in the passivation layer, an interlayer dielectric layer and a sacrificial layer (not shown) to expose the second dielectric layer 114 below, and a contact window 130 is provided in the passivation layer above the source/drain 124 to expose part of the source/drain 124 . In addition, the contact window 130 can optionally be substantially aligned or not aligned with a hole (not labeled).

Finally, as shown in FIG. 2E , a pixel electrode 132 is disposed on the protection layer (not shown), and fills the contact hole 130 and the opening 128, and then electrically connects the source/drain 124, and forms the capacitor stack 117. An electrode 132a. Preferably, the pixel electrode 132 is sequentially formed in the contact window 130 and the opening 128 .

Next, the structure of the storage capacitor and each layer of the pixel will be described in detail below, and in order to simplify the drawing and facilitate explanation, FIG. 3 is drawn corresponding to the line AA' of FIG. 1 . As shown in FIG. 3 , the substrate 106 and the semiconductor layer 108 thereon have a switching element region 102 and a capacitor region 104 . The capacitor stack 117 serving as a storage capacitor is located on the capacitor region 104 and includes a semiconductor layer 108 , a first dielectric layer 110 , a first conductive layer 112 , a second dielectric layer 114 and an electrode 132 a. Two sidewalls of the storage capacitor are covered by the ILD layer 120 . As shown in the figure, the first dielectric layer 110 covers the semiconductor layer 108 and the substrate 106 . On part of the first dielectric layer 110, there are the first conductive layer 112 and the second dielectric layer 114 in sequence. In addition, the stacked sides of the second dielectric layer 114 and the first conductive layer 112 substantially have a slope (taper), also known as a slope structure. The passivation layer 126 covers the formed structure. An opening 128 is formed in the passivation layer 126 to expose part or all of the second dielectric layer 114 . The pixel electrode 132 is partially disposed on the passivation layer 126 and disposed in the opening 128 , and the pixel electrode at the bottom of the opening 128 serves as an electrode 132 a of the storage capacitor. The residual layers 113, 115 are sacrificial layers remaining on the second dielectric layer 114 during the process of removing the sacrificial layer (not shown). Therefore, the residual layers 113, 115 can be selectively located on one end of the second dielectric layer 114, all located on one end of the second dielectric layer 114 (for example: only one or more residual layers 113/115), Or the residual layer 113, 115 does not exist on the second dielectric layer 114 of the capacitor region 104, but not limited thereto, the residual layer 113/115 can also be disposed on a part of the second dielectric layer 114, for example: located substantially away from On both ends of the second dielectric layer, substantially at the center of the second dielectric layer, or other positions, or a combination thereof. Secondly, the embodiment of the present invention is implemented with two residual layers as an example, and it can also be implemented with one residual layer or without a residual layer.

Next, please refer to FIG. 3 , there is a semiconductor layer 108 on the substrate 106 of the switching device region 102 , and the first dielectric layer 110 covers the semiconductor layer 108 and the substrate 106 . A gate stack 118 is located on the first dielectric layer 110 in the switching device region 102 . The gate stack 118 includes a first conductive layer 112 and a second dielectric layer 114 , and optionally includes a sacrificial layer 116 . The ILD layer 120 covers the substrate 106 . The source/drain electrodes 122 / 124 are disposed on a part of the interlayer dielectric layer 120 of the switching element region 102 and electrically connected to the semiconductor layer 108 on the switching element region 102 . The passivation layer 126 covers the substrate 106 . The pixel electrode 132 is disposed on a portion of the protective layer 126 and is electrically connected to the source/drain 124 . The semiconductor layer 108 has a channel region 109 located substantially below the gate stack 118, and at least one lightly doped region 107 is located on one of the two sides of the channel region 109. Embodiments of the present invention use the channel region The lightly doped regions 107 on both sides of 109 are an example, but not limited to this structure. The contact points between the source/drain electrodes 122 / 124 and the semiconductor layer 108 are respectively located outside the lightly doped region 107 , that is, connected to the first doped region 105 of the semiconductor layer 108 . In addition, at least one of the first dielectric layer, the second dielectric layer, the inner layer dielectric layer and the protective layer includes an organic material (such as: photoresist, polymethyl methacrylate, polycarbonate , polyalcohols, polyolefins, polyimides (polyimide), benzocyclobutene (Benzocyclobutene, BCB), parylene-N (PA), hydrocarbon-containing hydrogen silicide, or other materials, or a combination of the above ), inorganic materials (such as: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other materials, or a combination of the above), or a combination of the above.

Please refer to FIGS. 4A-4F , which show cross-sectional views of each process stage of the above-mentioned pixel in FIG. 3 according to the present invention. Please refer to FIG. 4A, which is a cross-sectional view corresponding to FIG. 2A along line AA'. The pixel is disposed on the substrate 106 and can be divided into a switching element area 102 and a capacitor area 104 . A semiconductor layer 108 is formed on the substrate 106 . Next, pattern the semiconductor layer 108, and after patterning, use a mask layer to cover part of the semiconductor layer 108 where the channel region is to be formed, and perform a first doping process on the semiconductor layer to form the first doped region 105 and the non-doped region, wherein the non-doped region serves as the channel region 109 . The formation method and patterning method of the semiconductor layer 108, for example, can be chemical vapor deposition and photolithography, but are not limited thereto, and other methods can also be selected, such as: coating method, screen printing method, inkjet printing method, or Other methods are used to form the patterned semiconductor layer 108 . In this embodiment, the semiconductor layer 108 can be a silicon-containing material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, or other silicon-containing materials, or any combination thereof. The above-mentioned first doping process can be N-doped or/and P-doped, so that the semiconductor layer 108 becomes an N-type semiconductor, a P-type semiconductor or a combination thereof.

Fig. 4B is a cross-sectional view corresponding to Fig. 2B along line AA'. First, after removing the mask layer, the first dielectric layer 110 is formed on the semiconductor layer 108 and the substrate 106 . On the first dielectric layer 110, a first conductive layer 112, a second dielectric layer 114 and a sacrificial layer 116 are formed. Preferably, the above-mentioned layers (first conductive layer 112, second dielectric layer 114 and sacrificial layer 116). Then, the first conductive layer 112, the second dielectric layer 114 and the sacrificial layer 116 are patterned, preferably, the above layers (the first conductive layer 112, the second dielectric layer 114 and the sacrificial layer 116) are patterned at the same time , so as to form the gate stack 118 and part of the capacitor stack 117 on the switching element region 102 and the capacitor region 104 respectively. In order to reduce the short channel effect, the gate stack 118 can be used as a mask to perform the second doping process, and then selectively form the lightly doped region 107 on at least one side of the channel region 109, so that the semiconductor layer 108 includes non- The doped region, the lightly doped region 107 and the first doped region 105 . However, the semiconductor layer may also selectively only include the non-doped region and the first doped region. Secondly, it must be noted that the above-mentioned doping process is a secondary doping process to form the non-doped region, the lightly doped region 107 and the first doped region 105 in the semiconductor layer, however, it is not limited to this, it can also be Selective simultaneous formation, for example: forming a photoresist on the patterned semiconductor layer 108, making the photoresist form a stepped or taper through an exposure process, and using the first doping process To form the first doped region 105, the lightly doped region 107 and the channel region 109 at the same time or through a yellow light process, an etching process and an ion implantation process, for example: etching the first dielectric layer to make it Steps or slopes are formed, and the first doped region 105 , the lightly doped region 107 and the channel region 109 are simultaneously formed by using the first doping process. In addition, in this embodiment, the first doping process is implemented when the semiconductor layer is patterned, but it is also optional to form a yellow light process, an etching process and an ion implantation process after the formation of the first dielectric layer. At least two of these processes are used so that the first doped region 105 , the lightly doped region 107 and the channel region 109 are formed simultaneously or not simultaneously in the patterned semiconductor layer. Or after forming the first dielectric layer, perform the first doping process to form the first doped region 105 and the channel region 109, and then form the gate stack or pattern the first conductive layer, and then use the gate A second doping procedure is performed on the electrode stack and/or the mask layer or a second doping procedure is performed on the patterned first conductive layer and/or the mask layer to form a lightly doped region. Or after forming the gate stack or patterning the first conductive layer, at least two of a yellow light process, an etching process, and an ion implantation process are formed, so that the patterned semiconductor layer is formed simultaneously or non-simultaneously. impurity region 105 , lightly doped region 107 and channel region 109 .

至3000埃

较佳地实质上小于1000埃

但不限于此。而牺牲层的厚度较佳地介于约200埃

至约3000埃

但不限于此。图案化之后的栅极堆叠及电容堆叠中至少一个堆叠侧边实质上具有一斜度(taper)，斜度实质上小于90度，较佳地，斜度实质上小于70度，但不限于此。另外，图案化第一导电层112、第二介电层114及牺牲层116的步骤时也可选择性地使用具有不同透光度的光掩模(如：半色调光掩模、绕射光掩模、栅状图案光掩模、或其它类似的光掩模)的黄光工艺，来形成栅极堆叠及电容堆叠，运用不同透光度的光掩模来进行蚀刻工艺可将栅极堆叠上方的牺牲层116一并删除。In this embodiment, during the step of patterning the first conductive layer 112 , the second dielectric layer 114 and the sacrificial layer 116 , a general photomask yellow light process can be used. In addition, the sacrificial layer 116 includes a silicon-containing material layer (such as: amorphous silicon, single crystal silicon, polycrystalline silicon, microcrystalline silicon, or other silicon-containing materials, or a combination thereof), and the thickness of the second dielectric layer 114 200 Angstroms in essence

to 3000 Angstroms

preferably substantially less than 1000 Angstroms

But not limited to this. The thickness of the sacrificial layer is preferably between about 200 Angstroms

to about 3000 Angstroms

But not limited to this. At least one side of the gate stack and the capacitor stack after patterning substantially has a taper, the taper is substantially less than 90 degrees, preferably, the taper is substantially less than 70 degrees, but not limited thereto . In addition, during the step of patterning the first conductive layer 112, the second dielectric layer 114 and the sacrificial layer 116, photomasks with different transmittances (such as: halftone photomask, diffractive photomask, etc.) can also be selectively used. mask, or other similar photomasks) to form gate stacks and capacitor stacks, using photomasks with different transmittances for etching processes can make the top of the gate stack The sacrificial layer 116 is also deleted.

Please refer to FIG. 4C, which is a cross-sectional view corresponding to FIG. 2C along line AA'. On the gate stack 118 , part of the capacitor stack 117 and the first dielectric layer 110 , an interlayer dielectric layer 120 is formed. Then, part of the interlayer dielectric layer 120 and the first dielectric layer 110 at the switching device region 102 are patterned to expose part of the surface of the semiconductor layer 108 . The formation method of the interlayer dielectric layer 120 can be, for example, chemical vapor deposition, but is not limited thereto, and other methods can also be selected, such as: coating method, screen printing method, inkjet printing method, or other methods to form The inner dielectric layer 120 . Next, source/drain electrodes 122 / 124 are formed on a part of the interlayer dielectric layer 120 of the switching element region 102 to be electrically connected to the first doped region 105 of the semiconductor layer 108 .

Please refer to FIG. 4D, which is a cross-sectional view corresponding to FIG. 2D along line AA'. On the source/drain electrodes 122/124 and the ILD layer 120, a passivation layer 126 is formed. Next, using the sacrificial layer 116 as an etching stop layer, the passivation layer 126 and the interlayer dielectric layer 120 are patterned to form contact windows 130 and openings 128 in the switching device region 102 and the capacitor region 104 respectively. Further, part or all of the sacrificial layer 116 is exposed at the opening 128 , and part or all of the source/drain 124 is exposed at the contact window 130 .

In the patterning process, if an etching method is used, in order to avoid over-etching, the ILD layer 120 and the sacrificial layer 116 have different etching rates for selective etching. Accordingly, after the ILD layer 120 at the opening 128 is deleted, the exposed surface of the sacrificial layer 116 tends to slow down the etching rate. Of course, other methods can also be used selectively to form the required patterning.

Next, FIG. 4E is also a cross-sectional view corresponding to FIG. 2D along line AA'. In FIG. 4E , the sacrificial layer 116 exposed at the opening 128 of the capacitive region 104 is patterned. When patterning the sacrificial layer 116 with an etching process, the residual layers 113 and 115 can be selectively left on both ends of the second dielectric layer 114 at the capacitor region 104 , or only part of the second dielectric layer 114 On either end, either residual layer 113 or 115 remains, or the residual layer 113 and 115 are completely deleted, or the residual layer 113/115 is disposed on a portion of the second dielectric layer, for example: located substantially away from the second dielectric layer. On both ends of the dielectric layer, substantially at the center of the second dielectric layer, or other locations, or a combination thereof, depending on whether the opening 128 fully or partially exposes the sacrificial layer 116 . However, no matter whether the sacrificial layer 116 remains on the second dielectric layer 114 or not, it will not affect the electrical properties of the entire storage capacitor.

Similarly, during patterning, in order to avoid excessive etching, the sacrificial layer 116 and the second dielectric layer 114 also have different etching rates, so after deleting the sacrificial layer 116 at the capacitor region 104, the exposed part of the first On the surface of the second dielectric layer 114, the etching rate will decrease again. Preferably, the etching selectivity ratio between the sacrificial layer 116 and the second dielectric layer 114 is substantially greater than or substantially equal to 2, that is, the etching rate of the sacrificial layer 116 is substantially greater than the etching rate of the second dielectric layer 114 . In the above embodiments of the present invention, the sacrificial layer 116 and the second dielectric layer 114 are respectively an amorphous silicon layer and a silicon oxide layer. A material whose etch rate is substantially greater than the etch rate of the second dielectric layer 114 . Therefore, taking the sacrificial layer 116 made of an amorphous silicon layer as an example, its etching rate is about 200A/min to about 10000A/min, and taking the second dielectric layer 114 made of a silicon oxide layer as an example, its etching rate The rate is approximately less than or approximately equal to 100A/min. Therefore, the etching selectivity ratio of the amorphous silicon layer and the silicon oxide layer is substantially about 2 to approximately 100, that is to say, the etching selectivity ratio of the two is substantially greater than or substantially equal to 2, and the etching of the amorphous silicon layer The rate is substantially greater than that of a silicon oxide layer, but not limited to the material and its associated information in this example.

Please refer to FIG. 4F, which is a cross-sectional view corresponding to FIG. 2E along line AA'. In FIG. 4F , a second conductive layer is formed on a portion of the passivation layer 126 for use as the pixel electrode 132 . The pixel electrode 132 formed on the source/drain 124 at the switching element region 102 can further be electrically connected to the first doped region 105 of the patterned semiconductor layer 108 . The pixel electrode 132 formed on the portion of the second dielectric layer 114 exposed by the opening 128 in the protective layer 126 at the capacitive region 104 serves as an electrode 132 a in the electrode stack 117 .

In the above embodiments, at least one of the first conductive layer and the second conductive layer includes a transparent material (such as: indium tin oxide, aluminum zinc oxide, indium zinc oxide, cadmium tin oxide, or other materials, or the above-mentioned Combination), non-transparent materials (such as: gold, silver, copper, iron, tin, lead, cadmium, molybdenum, neodymium, titanium, tantalum, tantalum, tungsten, or alloys of the above materials, or nitrides of the above materials, or Oxides of the above materials, or oxynitrides of the above materials, or other materials, or a combination of the above), or a combination of the above. As for at least one of the first dielectric layer, the second dielectric layer, the inner layer dielectric layer and the protective layer includes an organic material (such as: photoresist, polymethyl methacrylate, polycarbonate, poly Alcohols, polyolefins, or other materials, or a combination of the above), inorganic materials (such as: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other materials, or a combination of the above), or a combination of the above . Secondly, the pixel electrode of the present invention is an example of a transparent material (such as: indium tin oxide, aluminum zinc oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination of the above). Non-transparent materials (such as: gold, silver, copper, iron, tin, lead, cadmium, molybdenum, neodymium, titanium, tantalum, tantalum, tungsten, or alloys of the above materials, or nitrides of the above materials, or the above materials Oxides of the above materials, or nitrogen oxide compounds of the above materials, or other materials, or a combination of the above), or semi-transparent reflective materials (such as: part is a transparent material, while the other part is a non-transparent material, the material itself has a semi-transparent transflective properties, etc.).

In addition, the pixel described in the above-mentioned embodiments of the present invention may also have a double-gate structure or a double-gate structure, and the gates 138 and 140 shown in FIG. 5 are double-gate structures. Since various changes of the pixel structure are well known to those skilled in the art, details will not be repeated one by one. Secondly, the switching element on the switching element area of the above embodiment is an example of a top gate structure, but it is not limited thereto, other forms of top gate structure, bottom gate structure, other switching elements can also be used selectively. structure.

In addition, the structures of the gate stack and the capacitor stack in the pixel 100 in the above-mentioned embodiments of the present invention are based on the sacrificial layer 116 remaining on the second dielectric layer on the gate stack, but it is not limited thereto. It is also possible to selectively leave part of the sacrificial layer 116 on the second dielectric layer of the capacitor stack, the second dielectric layer on the gate stack without the sacrificial layer 116 , the second dielectric layer on the capacitor stack without the sacrificial layer 116 , or a combination of the above. Secondly, the semiconductor layer on the capacitive region and the switching element region in the above-mentioned embodiments of the present invention is an example that is integrally formed, but it is not limited thereto, and the semiconductor layer on the capacitive region and the switching element region can also be selected to be disconnected, The capacitor region and the semiconductor layer on the switching element region are connected through a connecting layer (not shown), or the semiconductor layer on the capacitor region and the switching element region is integrally formed, and then the capacitor region and the switching element region are connected through a connecting layer (not shown). Switches the semiconductor layer on the device region to increase its electron transport capability. Wherein, the material of the connection layer includes transparent materials (such as: indium tin oxide, aluminum zinc oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination of the above), non-transparent materials (such as: gold , silver, copper, iron, tin, lead, cadmium, molybdenum, neodymium, titanium, tantalum, tantalum, tungsten, or alloys of the above materials, or nitrides of the above materials, or oxides of the above materials, or nitrogen of the above materials Oxygen compounds, or silicon-containing materials, or other materials, or a combination of the above), or a combination of the above. In other words, the connection layer can be selectively formed at the same time when at least one of the first conductive layer, the semiconductor layer, the second conductive layer and the source/drain is formed.

Fig. 6 is a schematic diagram of an optoelectronic device of the present invention. Please refer to FIG. 6, the display panel 210 described in the above-mentioned embodiment of the present invention is also applied in an optoelectronic device 200, and the display panel 210 includes a matrix substrate (not shown) and a common electrode substrate corresponding to the matrix substrate (not shown), the matrix substrate has a plurality of pixels 100 described in the above-mentioned embodiments of the present invention. This optoelectronic device 300 also has an electronic element 220 connected with the display panel 210, such as: control elements, operating elements, processing elements, input elements, storage elements, driving elements, light emitting elements (such as: inorganic light emitting diodes, organic light emitting diodes, Cold cathode lamps, flat lamps, hot cathode lamps, external electrode lamps, or other types of lamps, or a combination of the above), sensing elements (such as: touch elements, light sensing elements, temperature sensing elements , image sensing element, or other types, or a combination of the above), a charging element, a heating element, a protection element, or other functional elements, or a combination of the above. The types of optoelectronic devices include portable products (such as mobile phones, video cameras, cameras, notebook computers, game consoles, watches, music players, e-mail transceivers, map navigators, electronic photos, or similar products), audio-visual products (such as AV projectors or similar products), screens, televisions, indoor or outdoor signage, or panels inside projectors, etc. In addition, the display panel 210 includes a liquid crystal display panel (such as a transmissive panel, a semi-transmissive panel, a reflective panel, a double-sided display panel, a vertical alignment panel (VA), an in-plane switching panel (IPS), a multi-domain vertical Alignment Panel (MVA), Twisted Nematic Panel (TN), Super Twisted Nematic Panel (STN), Patterned Vertical Alignment Panel (PVA), Super Patterned Vertical Alignment Panel (S-PVA), Improved Super Large Viewing Angle Panel (ASV), Frontier Field Switching Panel (FFS), Continuous Firework Array (CPA), Axisymmetric Microcell Panel (ASM), Optically Compensated Bend Array (OCB), Super Planar Switching panel (S-IPS), improved super in-plane switching panel (AS-IPS), extreme edge field switching panel (UFFS), polymer stabilized alignment panel (PSA), dual-view panel (dual-view), Triple-view panel, or color filter on array (COA) panel, or array on color filter (AOC) panel , or other types of panels, or a combination of the above), organic electroluminescent display panels, as for which panel to choose, it depends on the material that at least one of the pixel electrodes and drain electrodes in the panel is in electrical contact with, such as: liquid crystal layer, organic The light-emitting layer (such as: small molecules, polymers, or a combination of the above), or the combination of the above depends.

以下，使电容量大为提升外，还可依需求自行控制电容介电层的厚度，同时保有较佳的开口率。According to the above-mentioned embodiment of the present invention, compared with the traditional storage capacitor, the storage capacitor manufactured by the above manufacturing process can not only reduce the thickness of the dielectric layer to 3000 Angstroms

In addition to greatly improving the capacitance, the thickness of the dielectric layer of the capacitor can also be controlled according to the requirements, while maintaining a better aperture ratio.

Although the present invention has been disclosed above with an embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention should be determined by the scope defined by the appended claims.

Claims (50)

1. A storage capacitor, arranged on a substrate, comprising: at least one semiconductor layer disposed on the substrate; at least one first dielectric layer covering the semiconductor layer and the substrate; At least one first conductive layer is disposed on part of the first dielectric layer; at least one second dielectric layer disposed on the first conductive layer, the second dielectric layer having a slope to the stacked side of the first conductive layer; and At least one second conductive layer is disposed on part of the second dielectric layer. 2. The storage capacitor according to claim 1, wherein at least one of the first conductive layer and the second conductive layer comprises a transparent material, a non-transparent material, or a combination thereof. 3. The storage capacitor according to claim 1, wherein at least one of the first dielectric layer and the second dielectric layer comprises organic material, inorganic material or a combination thereof. 4. The storage capacitor according to claim 1, wherein the semiconductor layer comprises monocrystalline silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, or a combination thereof. 5. The storage capacitor according to claim 1, wherein the semiconductor layer is a doped N-type, P-type semiconductor layer or a combination thereof. 6. The storage capacitor as claimed in claim 1, wherein the semiconductor layer comprises at least one first doped region and at least one undoped region. 7. The storage capacitor according to claim 1, wherein the semiconductor layer comprises at least one first doped region, at least one non-doped region and at least one lightly doped region. 8. The storage capacitor of claim 1, further comprising an etch stop layer having at least a first portion disposed on a portion of the second dielectric layer. 9. The storage capacitor according to claim 1, further comprising an etch stop layer having at least one first portion and at least one second portion, the first portion being disposed on one of the two ends of the second dielectric layer , the second portion is disposed on the other end away from the second dielectric layer. 10. The storage capacitor as claimed in claim 1, wherein the thickness of the second dielectric layer is less than 3000 angstroms. 11. The storage capacitor as claimed in claim 1, wherein the thickness of the second dielectric layer is less than 1000 angstroms. 12. The storage capacitor as claimed in claim 1, wherein the second dielectric layer has a thickness ranging from 200 angstroms to 3000 angstroms. 13. The storage capacitor as claimed in claim 1, wherein the second conductive layer is electrically connected to the semiconductor layer. 14. The storage capacitor according to claim 8 or 9, wherein the etch stop layer comprises a silicon-containing material layer. 15. A pixel disposed on a substrate, and the pixel has at least one switching element region and at least one capacitor region, the pixel comprising: At least one semiconductor layer is formed on the substrate of the switching element region and the capacitor region respectively; at least one first dielectric layer covering the semiconductor layer and the substrate; At least one first conductive layer is respectively formed on a part of the first dielectric layer in the switching element region and the capacitor region; At least one second dielectric layer is formed on the first conductive layer of the switching element region and the capacitor region respectively; at least one etch stop layer, a part of the etch stop layer is formed on the second dielectric layer of the switching element region; At least one inner dielectric layer covers the substrate; at least one source/drain formed on a part of the interlayer dielectric layer of the switching element region, and electrically connected to the semiconductor layer on the switching element region; at least one protective layer covering the substrate; and At least one second conductive layer is disposed on part of the protective layer, and is electrically connected to one of the source/drain electrodes, and is disposed on part of the first conductive layer through at least one opening in the protective layer and the inner dielectric layer. on the second dielectric layer. 16. The pixel of claim 15, wherein at least one of the first conductive layer and the second conductive layer comprises a transparent material, a non-transparent material, or a combination thereof. 17. The pixel of claim 15, wherein at least one of the first dielectric layer, the second dielectric layer and the interlayer dielectric layer comprises an organic material, an inorganic material or a combination thereof. 18. The pixel of claim 15, wherein the semiconductor layer comprises monocrystalline silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, or a combination thereof. 19. The pixel according to claim 15, wherein at least one of the semiconductor layer on the switching element region and the capacitor region is a doped N-type, P-type semiconductor layer or a combination thereof. 20. The pixel of claim 15, wherein at least one of the semiconductor layer on the switching element region and the capacitor region comprises at least one first doped region and at least one non-doped region. 21. The pixel according to claim 15, wherein at least one of the semiconductor layer on the switching element region and the capacitor region comprises at least one first doped region, at least one non-doped region and at least one lightly doped region Miscellaneous area. 22. The pixel of claim 15, wherein another portion of the etch stop layer has at least a first portion disposed on a portion of the second dielectric layer. 23. The pixel according to claim 15, wherein another part of the etch stop layer has at least a first portion and at least a second portion, the first portion is disposed on one of the two ends of the second dielectric layer, the The second part is disposed on the other end away from the second dielectric layer. 24. The pixel of claim 15, wherein the etch stop layer comprises a silicon-containing material layer. 25. The pixel of claim 15, wherein stacked sides of the second dielectric layer and the first conductive layer have a slope. 26. The pixel of claim 15, wherein the thickness of the second dielectric layer is less than 3000 angstroms. 27. The pixel of claim 15, wherein the thickness of the second dielectric layer is less than 1000 angstroms. 28. The pixel as claimed in claim 15, wherein the second dielectric layer has a thickness ranging from 200 angstroms to 3000 angstroms. 29. The pixel as claimed in claim 15, further comprising a connection layer to electrically connect the switching element region and the semiconductor layer on the capacitor region. 30. The pixel as claimed in claim 29, wherein the connecting layer comprises monocrystalline silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, transparent material, non-transparent material, or a combination thereof. 31. A display panel comprising at least one signal line and the pixel according to claim 15. 32. An optoelectronic device comprising at least one electronic component and the display panel as claimed in claim 31. 33. A method for forming a pixel, the pixel is disposed on a substrate, and the pixel has at least one switching element region and at least one capacitor region, the method comprising: forming at least one semiconductor layer on the substrate of the switching element region and the capacitor region; forming at least one first dielectric layer to cover the semiconductor layer and the substrate; sequentially forming at least one first conductive layer, at least one second dielectric layer and at least one etch stop layer on the first dielectric layer; patterning the first conductive layer, the second dielectric layer and the etch stop layer to form a gate stack over the switching element region and a capacitor stack over the capacitor region; forming at least one interlayer dielectric layer to cover the gate stack, the capacitor stack and the first dielectric layer; forming at least one source/drain on a part of the interlayer dielectric layer of the switching element region, the source/drain being electrically connected to the semiconductor layer of the switching element region; forming at least one protective layer to cover the source/drain and the ILD; patterning the passivation layer and the interlayer dielectric layer to form a contact window and an opening in the passivation layer, and the opening exposes the etch stop layer; selectively etching the etch stop layer until a portion of the second dielectric layer is exposed; and forming at least one second conductive layer on a part of the protective layer, the second conductive layer is electrically connected to one of the source/drain electrodes through the contact window, and is disposed on the exposed portion of the exposed electrode through the opening in the protective layer part of the second dielectric layer. 34. The forming method of claim 33, wherein at least one of the first conductive layer and the second conductive layer comprises a transparent material, a non-transparent material, or a combination thereof. 35. The forming method of claim 33, wherein at least one of the first dielectric layer, the second dielectric layer, and the interlayer dielectric layer comprises an organic material, an inorganic material, or a combination thereof. 36. The forming method of claim 33, wherein the semiconductor layer comprises monocrystalline silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, or a combination thereof. 37. The forming method according to claim 33, wherein at least one of the semiconductor layer on the switching element region and the capacitor region is a doped N-type, P-type semiconductor layer or a combination thereof. 38. The forming method according to claim 33, wherein at least one of the semiconductor layer on the switching element region and the capacitor region comprises at least one first doped region and at least one non-doped region. 39. The forming method according to claim 33, wherein at least one of the semiconductor layer on the switching element region and the capacitor region comprises at least one first doped region, at least one non-doped region and at least one lightly doped region Miscellaneous area. 40. The forming method of claim 33, wherein the etch stop layer comprises a silicon-containing material layer. 41. The forming method of claim 33, wherein stacked sides of the second dielectric layer and the first conductive layer have a slope. 42. The forming method of claim 33, wherein the thickness of the second dielectric layer is less than 3000 angstroms. 43. The forming method of claim 33, wherein the thickness of the second dielectric layer is less than 1000 angstroms. 44. The forming method of claim 33, wherein the thickness of the second dielectric layer is 200 angstroms to 3000 angstroms. 45. The forming method of claim 33, wherein the gate stack comprises the first conductive layer, the second dielectric layer and the etch stop layer. 46. The forming method as claimed in claim 45, wherein the first conductive layer, the second dielectric layer and the etch stop layer are patterned so as to form a gate stack on the switching element region and on the capacitor In the step of forming the capacitor stack above the gate stack, a yellow light process using a photomask with different transmittances is used to remove part of the etch stop layer on the gate stack. 47. The forming method of claim 33, wherein the gate stack comprises the first conductive layer. 48. The forming method as claimed in claim 33, wherein the etch stop layer has a thickness of 200 angstroms to 3000 angstroms. 49. The forming method of claim 33, wherein, in the step of patterning the passivation layer and the ILD layer, the ILD layer and the etch stop layer have different etch rates. 50. The forming method of claim 33, wherein in the step of selectively etching the etch stop layer, the etch stop layer and the second dielectric layer have different etch rates.

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