CN101299441B - Thin film transistor, thin film transistor array substrate, display panel and photoelectric device - Google Patents

Abstract

The invention provides a thin film transistor, a thin film transistor array substrate, a display panel and a photoelectric device. The thin film transistor is configured on a substrate. The thin film transistor comprises a grid electrode, a dielectric layer, a semiconductor layer, a source electrode and a drain electrode. In addition, the dielectric layer is provided with at least one first dielectric block and at least one second dielectric block. The grid is formed on the base plate, the dielectric layer is formed on the base plate and covers the grid, and the semiconductor layer is formed on part of the dielectric layer. The source electrode and the drain electrode are respectively formed on partial areas of the semiconductor layer, so that the semiconductor layer positioned above the first dielectric block is not covered by the source electrode and the drain electrode, and the semiconductor layer positioned above the second dielectric block is covered by the source electrode and the drain electrode. Therefore, the thin film transistor has good electrical property.

Description

Thin film transistor, thin film transistor array substrate, display panel and optoelectronic device

technical field

The present invention relates to a display panel, a photoelectric device and a manufacturing method thereof, and in particular to a thin film transistor, a thin film transistor array substrate and a manufacturing method thereof.

Background technique

With the advancement of display technology, people can make life more convenient with the help of displays. In order to achieve light and thin displays, flat panel displays (Flat Panel Display, FPD) have become the mainstream at present, and liquid crystal displays ( Liquid Crystal Display, LCD) is the most popular.

Although liquid crystal displays have superior characteristics such as low power consumption, no radiation, and low electromagnetic interference, etc., improving the display quality of liquid crystal displays is still the most important issue. The display quality of a liquid crystal display can be determined by the electrical properties of the thin film transistors in the display panel, and the electrical properties can be viewed from different angles such as current, voltage, capacitance, etc. Among them, the larger the on current (On Current, I _ON ), the better , and the smaller the parasitic capacitance, the better.

In general, the selection of the dielectric layer of the thin film transistor will affect the electrical properties such as turn-on current, parasitic capacitance between the gate and the source (or drain). However, in order to reduce the parasitic capacitance between the gate and the source (or drain), the turn-on current (I _ON ) is usually reduced. Conversely, in order to increase the turn-on current (I _ON ), the parasitic capacitance cannot be suppressed effectively. Due to the above, designers cannot simultaneously meet the requirements of high turn-on current and low parasitic capacitance in the design of thin film transistors.

Contents of the invention

The invention provides a thin film transistor. The dielectric layer of the thin film transistor has two kinds of dielectric blocks to increase the turn-on current of the thin film transistor and reduce the capacitive effect between the gate and the source (or drain).

The present invention further provides a thin film transistor array substrate, and the thin film transistors in the thin film transistor array substrate have good electrical properties.

The present invention further provides a manufacturing method of a thin film transistor array substrate to manufacture the above thin film transistor array substrate.

The present invention further provides a display panel and an optoelectronic device, which have the above thin film transistor.

The present invention also provides a method for manufacturing the display panel and the optoelectronic device, so as to manufacture the above display panel and the optoelectronic device.

The invention provides a thin film transistor configured on a substrate. The thin film transistor includes a gate, a dielectric layer, a semiconductor layer, a source and a drain. In addition, the dielectric layer has at least one first dielectric block and at least one second dielectric block. The gate is formed on the substrate, the dielectric layer is formed on the substrate and covers the gate, and the semiconductor layer is formed on part of the dielectric layer. The source and the drain are respectively formed on a part of the semiconductor layer, so that the semiconductor layer above the first dielectric block is not covered by the source and the drain, and the semiconductor layer above the second dielectric block Covered by source and drain.

The present invention further provides a thin film transistor array substrate, which includes a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of the aforementioned thin film transistors, and a plurality of pixel electrodes. Scanning lines, data lines, thin film transistors and pixel electrodes are arranged on the substrate. In addition, each thin film transistor is electrically connected to each scan line, each data line and each pixel electrode, and the pixel electrode is electrically connected to one of the drains.

The present invention also proposes a manufacturing method of a thin film transistor array substrate, the method comprising: firstly, forming a plurality of scanning lines and a plurality of gates connected to the scanning lines on the substrate. Furthermore, a dielectric layer is formed on the substrate to cover the scanning lines and gates. Wherein, the dielectric layer includes a plurality of first dielectric blocks and a plurality of second dielectric blocks, and the dielectric constant of the first dielectric blocks is substantially greater than that of the second dielectric blocks. Then, a semiconductor layer is formed on the dielectric layer above the gate. Next, a plurality of data lines, a plurality of sources and a plurality of drains are formed on the substrate, and the sources and drains cover part of the semiconductor layer, so that the semiconductor layer above the first dielectric block is not covered by the source and the drain, and the semiconductor layer above the second dielectric block is covered by the source and the drain. Then, a plurality of pixel electrodes are formed on the substrate, and each pixel electrode is electrically connected to one of the drain electrodes respectively.

The present invention further proposes a display panel, which includes the above-mentioned thin film transistor array substrate.

The present invention also proposes an optoelectronic device, which includes the above thin film transistor array substrate.

The present invention also proposes a method for manufacturing a display panel, which includes the method for manufacturing a thin film transistor array substrate as described above.

The present invention also proposes a method for manufacturing an optoelectronic device, which includes the method for manufacturing a thin film transistor array substrate as described above.

In the display panel of the present invention, the dielectric layer of the thin film transistor can have two kinds of dielectric blocks. The dielectric layers of these two blocks can simultaneously increase the turn-on current of the thin film transistor and reduce the capacitive effect between the gate and the source (or drain), thereby improving the display quality of the display panel.

Description of drawings

FIG. 1A shows a partial top view of a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a flow chart of the manufacturing method of the thin film transistor array substrate of the present invention.

3A to 3J are partial cross-sectional schematic diagrams illustrating the manufacturing process of the thin film transistor according to the first embodiment of the present invention.

4A-4L are schematic partial cross-sectional views of the manufacturing process of the thin film transistor array substrate according to the second embodiment of the present invention.

FIGS. 5A-5G and FIGS. 3G-3J are schematic partial cross-sectional views of the manufacturing process of the thin film transistor according to the third embodiment of the present invention.

6A to 6M are schematic partial cross-sectional views of the manufacturing process of the thin film transistor array substrate according to the fourth embodiment of the present invention.

FIG. 7 is a schematic diagram of an optoelectronic device according to an embodiment of the present invention.

Figure number:

100: thin film transistor array substrate 102: first conductive layer

104: Second conductive layer 110: Substrate

120: Scanning line 130: Data line

140: thin film transistor 142: gate

144: Dielectric layer 144H: The first dielectric block

144H’: first dielectric material layer 144H”: part of the first dielectric material layer

144L': second dielectric material layer 144L: second dielectric block

144M, 144S: sacrificial pattern 144M’, 144S’: sacrificial material layer

144M": part of the sacrificial material layer 146, 146': semiconductor layer

146a, 146a': channel layer 146b, 146b': doped semiconductor layer

148D: Drain 148S: Source

150: Pixel electrode 160: Shared electrode

310: photoresist layer 700: optoelectronic device

710: Display panel 720: Electronic components

A: Shading area B: Semi-exposure area

C1-C1', C2-C2': section line d1～d6: film thickness

H: Contact window opening K: Dielectric constant

L: light source M2: second mask

PR ^- : Negative photoresist PV: Protective layer

S202, S204, S206, S208, S210: steps

Detailed ways

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

FIG. 1A shows a partial top view of a thin film transistor array substrate according to an embodiment of the present invention. Referring to FIG. 1A , the thin film transistor array substrate 100 of this embodiment includes, for example, a substrate 110 , a plurality of scan lines 120 , a plurality of data lines 130 , a plurality of thin film transistors 140 , a plurality of pixel electrodes 150 and a plurality of shared electrodes 160 . The scan lines 120 , the data lines 130 , the thin film transistors 140 , the pixel electrodes 150 and the common electrodes 160 are all disposed on the substrate 110 as an example, but not limited thereto. Wherein, the position where the pixel electrode 150 exists is also referred to as a visible area.

Fig. 1B shows a cross-sectional view of a thin film transistor according to an embodiment of the present invention, and Fig. 1B is a cross-sectional view along the section line C1-C1' according to Fig. 1A. Please refer to FIG. 1A and FIG. 1B at the same time, the thin film transistor 140 of this embodiment includes a gate 142 , a dielectric layer 144 , a semiconductor layer 146 , a source 148S and a drain 148D. Wherein, the gate electrode 142 is electrically connected to the scan line 120 , the source electrode 148S is electrically connected to the data line 130 , and the drain electrode 148D is electrically connected to the pixel electrode 150 .

Please continue to refer to FIG. 1B, the gate 142 is formed on the substrate 110, the dielectric layer 144 is formed on the substrate 110 and covers the gate 142, the semiconductor layer 146 is formed on a part of the dielectric layer 144, the source 148S and the drain 148D are respectively formed on partial regions of the semiconductor layer 146 . Preferably, the source 148S and the drain 148D are respectively formed on two ends of the semiconductor layer 146 . Wherein, the dielectric layer 144 may have at least one first dielectric block 144H and at least one second dielectric block 144L.

Based on the above, the dielectric constant (Dielectric Constant, K for short) of the first dielectric block 144H is substantially different from the dielectric constant of the second dielectric block 144L, preferably the dielectric constant of the first dielectric block 144H The constant may be substantially greater than the dielectric constant of the second dielectric block 144L. As shown in FIG. 1B, since the dielectric constant of the second dielectric block 144L is relatively small, when the source 148S, the drain 148D and the gate 142 have different potentials, the source 148S, the drain 148D and the gate 148 have different potentials. Capacitive effects between poles 142 can be made smaller. On the other hand, the high dielectric constant of the first dielectric block 144H can increase the turn-on current of the thin film transistor 140 .

FIG. 2 is a flow chart of the manufacturing method of the thin film transistor array substrate of the present invention. Please refer to FIG. 1A , FIG. 1B and FIG. 2 at the same time. First, in step S202 , a plurality of scan lines 120 and a plurality of gates 142 connected to the scan lines 120 are formed on the substrate 110 .

Furthermore, in step S204 , a dielectric layer 144 is formed on the substrate 110 to cover the scan line 120 and the gate electrode 142 . Wherein, the dielectric layer 144 includes a plurality of first dielectric blocks 144H and a plurality of second dielectric blocks 144L, and the dielectric constant of the first dielectric blocks 144H is substantially greater than that of the second dielectric blocks 144L. dielectric constant.

Then, in step S206 , a semiconductor layer 146 is formed on the dielectric layer 144 above the gate 142 .

Next, in step S208 , a plurality of data lines 130 , a plurality of source electrodes 148S and a plurality of drain electrodes 148D are formed on the substrate 110 , and the source electrodes 148S and the drain electrodes 148D cover a part of the semiconductor layer 146 . Preferably, the source 148S and the drain 148D are respectively formed on two ends of the semiconductor layer 146 . Wherein, the semiconductor layer 146 above the first dielectric block 144H is not covered by the source 148S and the drain 148D, and the semiconductor layer 146 above the second dielectric block 144L is covered by the source 148S and the drain 148D.

After that, in step S210 , a plurality of pixel electrodes 150 are formed on the substrate 110 , and each pixel electrode 150 is electrically connected to one of the drain electrodes 148D respectively.

It is worth noting that the steps in FIG. 2 do not represent an absolute sequence. The following embodiments will be combined with FIG. 2 to describe details and steps of the manufacturing method of the thin film transistor array substrate 100 in detail.

first embodiment

3A to 3J are partial cross-sectional schematic diagrams illustrating the manufacturing process of the thin film transistor according to the first embodiment of the present invention. 3A to 3J are cross-sectional views of the fabrication process of the thin film transistor 140 in FIG. 1B . Please refer to FIG. 3A first. First, a first conductive layer 102 and a first dielectric material layer 144H' are sequentially formed on the substrate 110. Referring to FIG.

Based on the above, a photoetching process is performed on the first conductive layer 102 and the first dielectric material layer 144H' by using a first mask (not shown). Therefore, the first conductive layer 102 and the first dielectric material layer 144H' are patterned to form the gate 142 and part of the first dielectric material layer 144H", as shown in FIG. 3B. Wherein, the pattern of the gate 142 and Portions of the first dielectric material layer 144H" are substantially the same.

In practice, the first conductive layer 102 is, for example, aluminum, gold, copper, molybdenum, chromium, titanium, silver, tin, neodymium, lead, tungsten, tantalum, the above-mentioned alloys, the above-mentioned nitrides, or other suitable materials, or the above-mentioned combination, and the first dielectric material layer 144H' can use a dielectric material with a dielectric constant K greater than or equal to about 6 and less than about 25, such as: silicon nitride, aluminum nitride, aluminum oxide, beryllium oxide, or other suitable material, or a combination of the above. Or, for example, hafnium silicon oxynitride (HfSiON), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), or a combination thereof with a dielectric constant K greater than or equal to 25. . . . and other dielectric materials with relatively large dielectric constants are examples, but not limited thereto, and other suitable materials can be selected in other embodiments.

After that, referring to FIG. 3C , a sacrificial material layer 144S′ is formed on the substrate 110 to cover the substrate 110 , the gate 142 and part of the first dielectric material layer 144H″. Next, please refer to FIG. 3C and FIG. 3D at the same time. As shown in FIG. 3C , a photolithography process is performed on a part of the first dielectric material layer 144H″ by using the second mask M2 together with the sacrificial material layer 144S′ to form the first dielectric block 144H, as shown in FIG. 3D .

It should be noted here that the second mask M2 in this embodiment is an example of a half tone mask (HalfToneMask, HTM), which can be used to perform a photolithography process to form the source electrode 148S and the drain electrode 148D (shown in Figure 1A and Figure 1B) pattern, wherein area A is a light-shielding area, and area B is a half-exposure (Half Tone Exposure) area. In other embodiments, two traditional masking processes can be used to obtain the same result, or inkjet method, screen printing method, or other suitable methods can be used to obtain the same result. In addition, the sacrificial material layer 144S' in this embodiment is, for example, a negative photoresist layer, but it is not limited thereto, and positive photoresist or other photosensitive polymers can also be used.

Please continue to refer to FIG. 3C and FIG. 3D , in detail, use the half-tone second mask M2 with a negative photoresist layer (sacrificial material layer 144S') to pattern the first dielectric material layer 144H' and the sacrificial material layer. material layer 144S'. Therefore, the part of the sacrificial material layer 144S' not shielded by the light-shielding region A can form the pattern of the first dielectric block 144H and the sacrificial pattern 144S under the light source L. In other words, the pattern of the first dielectric block 144H and the sacrificial pattern 144S are complementary to the patterns of the source 148S and the drain 148D (shown in FIGS. 1A and 1B ). More specifically, the part of the sacrificial material layer 144S' corresponding to the half-exposed region B forms the sacrificial pattern 144S with a smaller film thickness d2, and the remaining part of the sacrificial pattern 144S has a film thickness d1.

3E, a second dielectric material layer 144L' is formed on the substrate 110 to cover the first dielectric block 144H and the sacrificial pattern 144S, and the second dielectric material layer 144L' can use a dielectric constant of about Dielectric materials less than 6 and greater than 0, such as: silicon oxycarbide (SiOC), amorphous silicon (a-Si for short), silicon nitride, HSQ (hydrogen silsesquioxane), silicon oxide, silicon oxynitride, silicon phosphorus Glass (PSG), borophosphosilicate glass (BPSG), silicone glass, porous silicon compound, silicon-based polymer, MSQ (methylsilsesquioxane), polyimide, silicon polyimide, BCB (benzocyclobutenes), or other suitable material, or a combination of the above. Among them, silicon oxycarbide (SiOC, K is about 2.5-3), amorphous silicon (a-Si, K is about 3) ... and other dielectric materials with small dielectric constants are better choices, but still Not limited to this. In other embodiments, other suitable materials, or combinations of the above-mentioned materials may also be used.

Please refer to FIG. 3E and FIG. 3F at the same time. As shown in FIG. 3E , a lift-off process is performed to remove the sacrificial pattern 144S (the remaining negative photoresist layer), and while the lift-off process is performed, the sacrificial pattern 144S and part of the above first The two dielectric material layers 144L′ are lifted off simultaneously to form a second dielectric block 144L on the substrate 110 , as shown in FIG. 3F .

It can be seen from FIG. 3F that the dielectric layer 144 (the first dielectric block 144H and the second dielectric block 144L), preferably, can completely cover the substrate 110 and the gate 142, and the first dielectric The pattern of the segment 144H is a complementary pattern to the pattern of the second dielectric segment 144L. In addition, the dielectric constant of the first dielectric block 144H is substantially greater than that of the second dielectric block 144L. Up to now, the dielectric layer 144 having the first dielectric block 144H and the second dielectric block 144L has been substantially completed. In addition, preferably, the surfaces of the first dielectric block 144H and the second dielectric block 144L are located on the same plane as an example, but not limited thereto. Due to the precision of the lift-off process, the surface of the second dielectric block 144L may not be in the same plane as the surface of the first dielectric block 144H, and may be lower or higher than the surface of the first dielectric block 144H. The surface depends on the deposited thickness of the second dielectric block 144L or the conditions of the lift-off process (such as the material lift-off time for the lift-off process, subsequent processing, etc.).

Then referring to FIG. 3G, a semiconductor layer 146' is formed on the dielectric layer 144 above the gate 142. Referring to FIG. It is worth mentioning that the semiconductor layer 146' can be composed of a channel layer 146a' and a doped semiconductor layer 146b' arranged vertically as an example, but not limited thereto, and can also be arranged horizontally. Wherein, the material of the channel layer 146a' includes amorphous silicon as an example, but is not limited thereto, and may also include single crystal silicon, microcrystalline silicon, polycrystalline silicon, or other suitable materials, or a combination of the above, and the doped semiconductor layer 146b' The material includes N-type doped amorphous silicon or P-type doped amorphous silicon as an example, but is not limited thereto, and can also include N-type doped/P-type doped single crystal silicon, N-type doped/P-type doped Heterocrystalline silicon, N-type doped/P-type doped polysilicon, or other suitable materials, or a combination of the above. In this embodiment, the channel layer 146a' can be used as an electron channel between the source 148S and the drain 148D (shown in FIG. 1B ), and the doped semiconductor layer 146' can reduce the metal material (such as the source 148S and the drain 148D). The contact resistance between the material of the drain 148D) and the semiconductor material (such as the material of the channel layer 146a').

Next, the source 148S and the drain 148D can be formed on the substrate 110 , please refer to FIG. 3H and FIG. 3I at the same time. Specifically, as shown in FIG. 3H, a second conductive layer 104 is formed above the semiconductor layer 146', and the material of the second conductive layer 104 is, for example, aluminum, molybdenum, titanium, neodymium, gold, silver, copper, tin , lead, chromium, tantalum, the above oxides, the above nitrides, the above alloys, other suitable materials, or combinations of the above. Then, please refer to FIG. 3I , which uses the half-tone second mask M2 together with the photoresist layer 310 as an example to pattern the second conductive layer 104 and the semiconductor layer 146'. In other embodiments, the photoresist layer 310 can also be matched with a general mask having only the penetrating area and the light shielding area A. Referring to FIG. It should be noted that the film thickness d4 of the part of the photoresist layer 310 corresponding to the half-exposed area B is smaller than the film thickness d1 of the remaining part of the photoresist layer 310 .

Based on the above, after the photolithography process is performed with the second mask M2 and the photoresist layer 310 , the source electrode 148S, the drain electrode 148D and the channel layer 146a are formed, as shown in FIG. 3J . It can be known from FIG. 3J that part of the channel layer 146a located above the first dielectric block 144H is not covered by the source 148S and the drain 148D, while the doped semiconductor layer 146b located above the second dielectric block 144L is covered by the source. The electrode 148S overlaps the drain 148D. In other words, preferably, the pattern of the second dielectric block 144L is substantially the same as that of the source electrode 148S and the drain electrode 148D, but not limited thereto, the pattern of the second dielectric block 144L can also be the same as that of the source electrode 148S and the drain electrode 148D. The pattern of the electrode 148S is substantially different from that of the drain electrode 148D. So far, the thin film transistor 140 of the present invention has been roughly fabricated.

Based on the above, after the photolithography process is performed with the second mask M2 and the photoresist layer 310 , the source electrode 148S, the drain electrode 148D and the channel layer 146a are formed, as shown in FIG. 3J . It can be known from FIG. 3J that part of the channel layer 146a located above the first dielectric block 144H is not covered by the source 148S and the drain 148D, while the doped semiconductor layer 146b located above the second dielectric block 144L is covered by the source. The electrode 148S overlaps the drain 148D. In other words, preferably, the pattern of the second dielectric block 144L is substantially the same as that of the source 148S/drain 148D, but not limited thereto, the pattern of the second dielectric block 144L can also be the same as that of the source 148S/drain 148D. The patterns of electrode 148S/drain 148D are substantially different. So far, the thin film transistor 140 of the present invention has been roughly fabricated.

The dielectric layer 144 of the thin film transistor 140 in this embodiment may have two kinds of dielectric blocks, wherein the first dielectric block 144H not covered by the source 148S and the drain 148D has a larger dielectric constant, so it can be The turn-on current of the thin film transistor 140 is made higher. The second dielectric block 144L covered by the source 148S and the drain 148D has a lower dielectric constant, which can reduce the parasitic capacitance between the source 148S and the drain 148D and the gate 142 .

Applying the thin film transistor 140 of this embodiment to the thin film transistor array substrate 100 can make the thin film transistor array substrate 100 have better electrical properties. The structure and manufacturing method of the thin film transistor array substrate 100 will be described below with the second embodiment, as shown in FIGS. 4A-4L and FIG. 2 .

second embodiment

4A-4L are schematic partial cross-sectional views of the manufacturing process of the thin film transistor array substrate according to the second embodiment of the present invention, and FIGS. 4A-4L are cross-sectional views along the section line C2-C2' in FIG. 1A. Manufacturing method and first implementation of gate 142, dielectric layer 144 (first dielectric block 144H and second dielectric block 144L), semiconductor layer 146, source 148S, and drain 148D of thin film transistor array substrate 100 The thin film transistor 140 of the example is similar, and the cross-sections of its fabrication process are shown in FIGS.

Incidentally, as shown in FIG. 1A and FIG. 4B , the scan lines 120 and the shared electrode 160 in this embodiment and the gate 142 in the first embodiment are, for example, the first conductive layer 102, so preferably The scan line 120 , the common electrode 160 and the plurality of gates 142 connected to the scan line 120 can be patterned in the same process by using a first mask (not shown), but is not limited thereto. Therefore, in the process stage shown in FIG. 4D (please see it together with FIG. 1A ), the pattern of the first dielectric block 144H can be defined, for example, the first dielectric block 144H is above the common electrode 160 .

Similarly, as shown in FIG. 1A and FIG. 4J , the data line 130 in this embodiment and the source electrode 148S and drain electrode 148D in the first embodiment are, for example, the second conductive layer 104 . Therefore, preferably, the second mask M2 (shown in FIG. 4I ) can be used to complete the patterns of the data line 130 , the source electrode 148S and the drain electrode 148D in the same process, but not limited thereto. That is to say, preferably, the pattern of the second dielectric block 144L is substantially the same as the pattern of the source electrode 148S, the drain electrode 148D and the data line 130, but not limited thereto, the pattern of the second dielectric block 144L The pattern of the source electrode 148S, the drain electrode 148D and the data line 130 may also be substantially different.

Next, please refer to FIG. 1A and FIG. 4K . In this embodiment, after the source electrode 148S, the drain electrode 148D and the data line 130 are formed, a protection layer PV may be formed to cover the source electrode 148S/drain electrode 148D and the data line 130 . Wherein, the passivation layer PV has a contact opening H to expose the drain 148D. In detail, the protective layer PV can be a single-layer or multi-layer structure, and its material is an organic material (for example: photoresist, benzocyclobutene, cycloalkene, polyimide, polyamide, polyester Classes, polyalcohols, polyethylene oxides, polyphenylenes, resins, polyethers, polyketones, or other materials, or combinations of the above), inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination of the above), or a combination of the above. In this embodiment, the silicon nitride of inorganic material is taken as an example, but it is not limited thereto.

Referring to FIG. 4L thereafter, a pixel electrode 150 is formed on the protection layer PV, and the pixel electrode 150 is electrically connected to the drain electrode 148D through the contact window opening H. Referring to FIG. In practice, the method of forming the pixel electrode 150 is, for example, a physical vapor deposition (Physical Vapor Deposition, PVD) sputtering process. Generally speaking, the material of the pixel electrode 150 is reflective (such as gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys, the above metal oxides, etc.) , the above-mentioned metal nitrides, or a combination of the above), transparent and conductive (such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, hafnium oxide, zinc oxide, aluminum oxide, aluminum tin oxide, aluminum zinc oxide substances, cadmium tin oxide, cadmium zinc oxide, or a combination of the above), or a combination of the above. In this embodiment, the transparent conductive material ITO is taken as an example, but it is not limited thereto. Up to now, the TFT array substrate 100 of the present invention has been substantially completed.

third embodiment

In this embodiment, other materials are used to replace the negative photoresist layer (sacrificial material layer 144S', shown in FIG. 3C ) in the first embodiment. The manufacturing process of the thin film transistor 140 in this embodiment will be described in detail below. 5A to 5G and 3G to 3J are schematic partial cross-sectional views of the manufacturing process of the thin film transistor according to the third embodiment of the present invention, and FIGS. 5A to 5G and 3G to 3J are the completed thin films in FIG. 1B A cross-sectional view of the fabrication process of the transistor 140 . Referring to FIG. 5A , firstly, a first conductive layer 102 , a first dielectric material layer 144H' and a sacrificial material layer 144M' are sequentially formed on the substrate 110 .

Based on the above, a photoetching process is performed on the first conductive layer 102, the first dielectric material layer 144H' and a sacrificial material layer 144M' by using a first mask (not shown). Therefore, the first conductive layer 102, the first dielectric material layer 144H' and a sacrificial material layer 144M' are patterned to form the gate 142, a part of the first dielectric material layer 144H" and a part of the sacrificial material layer 144M", As shown in Figure 5B. Wherein, the pattern of the gate 142 , part of the first dielectric material layer 144H″ and part of the sacrificial material layer 144M″ are substantially the same.

In practice, the first conductive layer 102 is, for example, aluminum, gold, copper, molybdenum, chromium, titanium, silver, tin, neodymium, lead, tungsten, tantalum, the above-mentioned alloys, the above-mentioned nitrides, or other suitable materials, or the above-mentioned Combination, and the first dielectric material layer 144H' can use a dielectric material with a dielectric constant K greater than or equal to 6 and less than 25, for example: silicon nitride, aluminum nitride, aluminum oxide, beryllium oxide, or other suitable material, or a combination of the above. Or, for example, hafnium silicon oxynitride (HfSiON), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), or a combination thereof with a dielectric constant K greater than or equal to 25. . . . and other dielectric materials with relatively large dielectric constants are examples, but not limited thereto, and other suitable materials can be selected in other embodiments.

Then please refer to FIG. 5C and FIG. 5D . As shown in FIG. 5C, a layer of negative photoresist material ^PR- is formed on the substrate 110 as an example to cover the substrate 110, the gate 142, part of the first dielectric material layer 144H" and part of the sacrificial material layer 144M". . In other embodiments, positive photoresists or other photosensitive polymers may also be used. Then use the second mask M2 and the negative photoresist material ^PR to perform a photoetching process on the gate 142, the etched part of the first dielectric material layer 144H" and part of the sacrificial material layer 144M", and the first The dielectric block 144H and the sacrificial pattern 144M above the first dielectric block 144H are shown in FIG. 5D . Wherein, the sacrificial pattern 144M includes a mask layer, and the material of the mask layer (mask layer) is, for example, silicon nitride (SiNx).

It should be noted here that the second mask M2 of this embodiment is an example of a half tone mask (HTM), which can be used to perform a photolithography process to form the source electrode 148S and the drain electrode 148D (shown in FIG. 1A and FIG. 1B), wherein area A is a light-shielding area, and area B is a half-exposed area. In other embodiments, two traditional masking processes can be used to obtain the same result, or inkjet method, screen printing method, or other suitable methods can be used to obtain the same result. Therefore, in this embodiment, under the combination of the second mask M2 and the negative photoresist material PR−, the pattern of the first dielectric block 144H and the pattern of the sacrificial pattern 144M will be consistent with the source 148S and the drain 148D. The patterns are complementary. More specifically, the film thickness of part of the negative photoresist material ^PR- corresponding to the half-exposure area B is d6, and the film thickness of the remaining part of the negative photoresist material ^PR- is d5, and the film thickness d6 is smaller than that of the film The layer thickness d5 is small.

Next, a photoresist stripping process is performed on the negative photoresist material PR− in FIG. 5D , as shown in FIG. 5E . Next, please refer to FIG. 5F, a second dielectric material layer 144L' is formed on the substrate 110 to cover the substrate 110, the first dielectric block 144H and the sacrificial pattern 144M, and the second dielectric material layer 144L' can be used Dielectric materials with a dielectric constant of approximately less than 6 and greater than 0, such as: silicon oxycarbide (SiOC), amorphous silicon (a-Si), silicon nitride, HSQ (hydrogen silsesquioxane), silicon oxide, silicon oxynitride, phosphorus Silicon glass (PSG), borophosphosilicate glass (BPSG), organic silicon glass, porous silicon compound, silicon-based polymer, MSQ (methylsilsesquioxane), polyimide, silicon polyimide, BCB (benzocyclobutenes), or others Suitable materials, or a combination of the above. Among them, silicon oxycarbide (SiOC, K is about 2.5-3), amorphous silicon (a-Si, K is about 3) . However, it is not limited thereto, and other suitable materials or combinations of the above-mentioned materials can also be used in other embodiments.

Then please refer to FIG. 5F and FIG. 5G at the same time. As shown in FIG. 5F , the lift-off process is performed to remove the sacrificial pattern 144M, while the lift-off process is performed, the sacrificial pattern 144M and part of the second dielectric material layer 144L′ above it will be lifted off simultaneously, and A second dielectric block 144L is formed on the substrate 110, as shown in FIG. 5G. It is worth mentioning that in the chemical vapor deposition reaction chamber (CVD chamber), silicon nitride (SiNx) is less likely to react than the photoresist, so that the reactants remain on the inner wall of the chemical vapor deposition reaction chamber. In other words, in this embodiment, silicon nitride (SiNx) is used as the material of the sacrificial pattern 144M, which can effectively improve the cleanliness of the chemical vapor deposition reaction chamber.

It can be seen from FIG. 5G that the dielectric layer 144 (the first dielectric block 144H and the second dielectric block 144L), preferably, can completely cover the substrate 110 and the gate 142, and the first dielectric The pattern of the segment 144H is a complementary pattern to the pattern of the second dielectric segment 144L. In addition, the dielectric constant of the first dielectric block 144H is substantially greater than that of the second dielectric block 144L. Up to now, the dielectric layer 144 having the first dielectric block 144H and the second dielectric block 144L has been substantially completed. In addition, preferably, the surfaces of the first dielectric block 144H and the second dielectric block 144L are located on the same plane as an example, but not limited thereto. Due to the precision of the lift-off process, the surface of the second dielectric block 144L may not be in the same plane as the surface of the first dielectric block 144H, and may be lower or higher than the surface of the first dielectric block 144H. The surface depends on the deposited thickness of the second dielectric block 144L or the conditions of the lift-off process (such as the material lift-off time for the lift-off process, subsequent processing, etc.).

Next, the manufacturing method of forming the semiconductor layer 146 (including the channel layer 146a and a doped semiconductor layer 146b), the source electrode 148S and the drain electrode 148D is similar to that of the first embodiment. Please refer to FIGS. 3G to 3J to understand the manufacturing process. section, which will not be repeated here. As shown in FIG. 3J , it can be seen that preferably the pattern of the second dielectric block 144L is substantially the same as the pattern of the source electrode 148S and the drain electrode 148D, but not limited thereto, the pattern of the second dielectric block 144L is also The patterns of the source 148S and the drain 148D may be substantially different. So far, the thin film transistor 140 of the present invention has been roughly fabricated.

The dielectric layer 144 of the thin film transistor 140 in this embodiment is composed of two kinds of dielectric constants to reduce the parasitic capacitance between the source 148S and the drain 148D and the gate 142 and improve the performance of the thin film transistor. 140 turn-on current. In addition, silicon nitride (SiNx) is used as the material of the mask layer to improve the pollution problem caused by the photoresist to the chemical vapor deposition reaction chamber.

Applying the thin film transistor 140 of this embodiment to the thin film transistor array substrate 100 can make the thin film transistor array substrate 100 have better electrical properties, and can also reduce the pollution that is harmful to the machine during the process. The structure and manufacturing method of the thin film transistor array substrate 100 will be described below with the fourth embodiment, as shown in FIGS. 6A to 6M and FIG. 2 .

Fourth embodiment

6A-6M are schematic partial cross-sectional views of the manufacturing process of the thin film transistor array substrate according to the fourth embodiment of the present invention, and FIGS. 6A-6M are cross-sectional views along the section line C2-C2' in FIG. 1A. Formation of the gate 142, the dielectric layer 144 (the first dielectric block 144H and the second dielectric block 144L), the semiconductor layer 146, the source 148S and the drain 148D of the thin film transistor array substrate 100 of this embodiment Similar to the manufacturing process of the thin film transistor 140 in the third embodiment, the cross-sections of its manufacturing process are shown in FIGS. 6A-6K , which will not be repeated here.

Incidentally, as shown in FIG. 1A and FIG. 6B , the scan line 120 and the shared electrode 160 in this embodiment and the gate 142 in the third embodiment are, for example, the first conductive layer 102 , so the first conductive layer 102 can be used. A mask (not shown) completes the pattern of the scan line 120 , the common electrode 160 and a plurality of gates 142 connected to the scan line 120 in the same process. Therefore, in the process stage shown in FIG. 6E (please look at it together with FIG. 1A ), the pattern of the first dielectric block 144H can be defined, for example, the dielectric layer 144 (not shown) above the common electrode 160 is The first dielectric block 144H.

Next, a protection layer PV and a pixel electrode 150 are formed on the substrate 110 . The formation method of the protective layer PV and the pixel electrode 150 of the thin film transistor array substrate 100 of this embodiment is similar to the process method of the thin film transistor array substrate 100 of the fourth embodiment, and the cross-section of the manufacturing process is shown in FIG. 6L and FIG. 6M , which will not be elaborated here. Up to now, the TFT array substrate 100 of the present invention has been substantially completed.

Furthermore, it must be noted that, in the above-mentioned embodiments of the present invention, the dielectric constant of the first dielectric block 144H can be substantially greater than the dielectric constant of the second dielectric block 144L as a rule. Preferably, in addition to the materials listed in the first dielectric block 144H and the materials listed in the second dielectric block 144L, the materials listed in the first dielectric block 144H can also be selected at the same time. Both materials may have substantially different dielectric constants. Alternatively, the materials listed in the second dielectric block 144L can be selected from the materials listed in the second dielectric block 144L at the same time.

It must be noted that FIG. 1A of the present invention has a shared electrode 160 disposed on the substrate, and it has at least one body (not shown) parallel to the scan line 120 and a plurality of electrodes extending to the body and parallel to the data line 130. The extension part (not shown) is an example, but not limited thereto, and only one extension part may be included. Moreover, the main body and the extension part are not limited to this shape. In addition, in other embodiments, the shared electrode 160 may not be included, and then the capacitor is composed of a part of the gate line 120, an electrode (such as the pixel electrode 150) above the gate line 120, and the second electrode interposed between the two electrodes. A dielectric block 144H is formed, called capacitor on gate line (Cs on gate).

FIG. 7 is a schematic diagram of an optoelectronic device according to an embodiment of the present invention. Referring to FIG. 7 , the optoelectronic device 700 includes a display panel 710 and an electronic component 720 electrically connected thereto. The display panel 710 includes the thin film transistor array substrate 100 as described in the above embodiments.

Furthermore, according to different display modes, film layer designs and display media as distinctions, the display panel 710 includes a variety of different types. When the display medium is liquid crystal molecules, the display panel 710 may be a liquid crystal display panel. Common liquid crystal display panels include transmissive display panels, semi-transmissive display panels, reflective display panels, color filter on active layer (color filter on array) display panels, active layer on color filter Array on color filter display panel, vertical alignment (vertical alignment, VA) display panel, horizontal switching (in plane switch, IPS) display panel, multi-domain vertical alignment (multi-domain vertical alignment, MVA) Display panel, twisted nematic (twist nematic, TN) display panel, super twisted nematic (STN) display panel, patterned vertical alignment (patterned-silt vertical alignment, PVA) display panel, super pattern vertical Super patterned-silt vertical alignment (S-PVA) display panel, advanced large viewing angle (advance super view, ASV) display panel, fringe field switching (FFS) display panel, continuous fireworks arrangement (continuous pinwheel alignment, CPA) display panel, axially symmetrically aligned micro-cell mode (ASM) display panel, optical compensation banded (OCB) display panel, super horizontal switching (super in plane switching) , S-IPS) display panel, advanced super in plane switching (AS-IPS) display panel, ultra-fringe field switching (UFFS) display panel, polymer stabilized alignment display panel , a dual-view display panel, a triple-view display panel, a three-dimensional display panel, or other types of panels, or a combination thereof, are also called non-self-luminous display panels. If the display medium is an electroluminescent material, it is called an electroluminescent display panel (such as: a phosphorescent electroluminescent display panel, a fluorescent electroluminescent display panel, or a combination of the above), and it is also called a self-luminous display panel, and its The electroluminescent material can be an organic material, an inorganic material, or a combination of the above, and the molecular size of the above material includes small molecules, macromolecules, or the combination of the above. If the display medium includes both liquid crystal material and electroluminescent material, the display panel is called a hybrid display panel or a semi-self-luminous display panel.

In addition, the electronic component 720 includes a control component, an operating component, a processing component, an input component, a storage component, a driving component, a light emitting component, a protection component, a sensing component, a detection component, or other functional components, or a combination thereof. In general, the types of optoelectronic devices 700 include portable products (such as mobile phones, video cameras, still cameras, notebook computers, game consoles, watches, music players, e-mail transceivers, map navigators, digital photos, or similar products) ), audio-visual products (such as audio-visual projectors or similar products), screens, televisions, billboards, panels inside projectors, etc. In addition, the present invention proposes a method for manufacturing an optoelectronic device, which includes the method for manufacturing the display panel of the above-mentioned embodiments.

In summary, by using the manufacturing method of the thin film transistor array substrate of the present invention, the dielectric layer of the thin film transistor can have two kinds of dielectric constants. Among them, the dielectric block with high dielectric constant can make the thin film transistor generate higher turn-on current, and the dielectric block with low dielectric constant can reduce the capacitance effect between the gate and the source and drain. Therefore, thin film transistors have good electrical properties. Applying the thin film transistor to a display panel can improve the display quality of the display panel. In addition, in the third and fourth embodiments, for example, silicon nitride (SiNx), but not limited thereto, is used as a mask to complete the manufacture of the dielectric layer, so that the problem of contamination of the chemical vapor deposition reaction chamber is improved, Thereby reducing the cost of machine maintenance.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make some modifications and changes without departing from the spirit and scope of the present invention. modification, so the scope of protection of the present invention should be determined by what is defined in the claims.

Claims (17)

1. a thin-film transistor is disposed on the substrate, it is characterized in that, this thin-film transistor comprises:

One grid is formed on the described substrate;

One dielectric layer is formed on the substrate and covers described grid, and this dielectric layer has at least one first dielectric block and at least one second dielectric block;

Semi-conductor layer is formed on the described dielectric layer of part; And

One source pole and drain electrode, be formed on the subregion of described semiconductor layer respectively and all, covered so that be positioned at the semiconductor layer of described first dielectric block top, and the semiconductor layer that is positioned at above the described second dielectric block is covered by described source electrode and drain electrode by described source electrode and drain electrode;

Wherein, the dielectric constant of the described first dielectric block is greater than the dielectric constant of the described second dielectric block; The pattern complementation of the pattern of the described first dielectric block and the described second dielectric block.

2. thin-film transistor as claimed in claim 1 is characterized in that, described dielectric layer is to be covered on described substrate and the grid comprehensively.

3. thin-film transistor as claimed in claim 1 is characterized in that, the pattern of described source electrode and drain electrode is identical with the pattern of the described second dielectric block.

4. a thin-film transistor array base-plate is characterized in that, this array base palte comprises:

One substrate;

The multi-strip scanning line is disposed on the described substrate;

Many data wires are disposed on the described substrate;

The described thin-film transistor of a plurality of claims 1 is disposed on the described substrate, and each thin-film transistor is electrically connected at each scan line and data wire; And

A plurality of pixel electrodes are disposed on the described substrate and electrically connect with described one of them drain electrode.

5. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, the pattern complementation of the pattern of the described first dielectric block and the described second dielectric block.

6. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, the pattern of described source electrode and described drain electrode is identical with the pattern of the described second dielectric block.

7. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, the pattern of described source electrode, described drain electrode and described data wire is identical with the pattern of the described second dielectric block.

8. thin-film transistor array base-plate as claimed in claim 4, it is characterized in that, this array base palte comprises that also one shares electrode, is disposed at described pixel electrode below, and the wherein said first dielectric block is disposed between described shared electrode and the described pixel electrode.

9. the manufacture method of a thin-film transistor array base-plate is characterized in that, this method comprises:

On a substrate, form the grid that multi-strip scanning line and a plurality of and described scan line are connected;

On described substrate, form a dielectric layer, to cover described scan line and described grid, wherein this dielectric layer comprises a plurality of first dielectric blocks and a plurality of second dielectric block, and the dielectric constant of the described first dielectric block is greater than the dielectric constant of the described second dielectric block;

On the described dielectric layer of described grid top, form semi-conductor layer;

On described substrate, form many data wires, a plurality of source electrode and a plurality of drain electrodes, this source electrode and this drain electrode are covered on the subregion of described semiconductor layer, covered so that be positioned at this conductor layer of described first dielectric block top, and the semiconductor layer that is positioned at above the described second dielectric block is covered by this source electrode and drain electrode by this source electrode and drain electrode; And

On described substrate, form a plurality of pixel electrodes, and each pixel electrode electrically connects with one of them drain electrode respectively;

Wherein, the formation method of described first dielectric block and the described second dielectric block comprises:

On described substrate, form one first dielectric materials layer and a sacrificial material layer in regular turn;

Described first dielectric materials layer of patterning and described sacrificial material layer are to form the described first dielectric block and a plurality of sacrificial pattern that is positioned on the described first dielectric block;

On substrate, form one second dielectric materials layer, to cover described first dielectric block and described sacrificial pattern; And

Remove described sacrificial pattern, lifted off and form the described second dielectric block so that be positioned at described second dielectric materials layer of part on the described sacrificial pattern.

10. the manufacture method of thin-film transistor array base-plate as claimed in claim 9 is characterized in that, described sacrificial material layer comprises a minus photoresist layer, and the method for described first dielectric materials layer of patterning and described sacrificial material layer comprises:

Use a mask described minus photoresist layer of arranging in pairs or groups that described first dielectric materials layer is carried out a photoengraving technology, to form the described first dielectric block.

11. the manufacture method of thin-film transistor array base-plate as claimed in claim 9 is characterized in that, described sacrificial pattern comprises a mask layer, and the method for described first dielectric materials layer of patterning and described sacrificial material layer comprises:

Use the mask photoresist layer of arranging in pairs or groups that described first dielectric materials layer and described sacrificial material layer are carried out a photoengraving technology, to form described first dielectric block and described sacrificial pattern.

12. the manufacture method of thin-film transistor array base-plate as claimed in claim 11 is characterized in that, the material of described mask layer comprises silicon nitride.

13. the manufacture method of thin-film transistor array base-plate as claimed in claim 9, it is characterized in that, this method also is included in described pixel electrode below and forms a shared electrode, and the wherein said first dielectric block is disposed between described shared electrode and the described pixel electrode.

14. a display floater is characterized in that this display floater comprises thin-film transistor array base-plate as claimed in claim 1.

15. an electrooptical device is characterized in that this electrooptical device comprises thin-film transistor array base-plate as claimed in claim 14.

16. the manufacture method of a display floater is characterized in that, this method comprises the manufacture method of thin-film transistor array base-plate as claimed in claim 9.

17. the manufacture method of an electrooptical device is characterized in that, this method comprises the manufacture method of thin-film transistor array base-plate as claimed in claim 16.

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