CN100499140C

CN100499140C - Pixel structure and manufacturing method thereof

Info

Publication number: CN100499140C
Application number: CNB2007100913895A
Authority: CN
Inventors: 林祥麟; 林敬桓; 黄德群
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2007-03-30
Filing date: 2007-03-30
Publication date: 2009-06-10
Anticipated expiration: 2027-03-30
Also published as: CN101030587A

Abstract

The invention relates to a pixel structure and a manufacturing method thereof. The pixel structure comprises a grid electrode, a patterned dielectric layer, a patterned semiconductor layer, a patterned metal layer, a flat layer and a transparent pixel electrode. The grid and the patterned dielectric layer covering the grid are all arranged on the substrate. The patterned semiconductor layer on the patterned dielectric layer comprises a channel layer and a plurality of bumps above the gate. The patterned metal layer comprises a source electrode, a drain electrode and a reflective pixel electrode connected with the drain electrode. The source electrode and the drain electrode respectively cover a part of the channel layer. The reflective pixel electrode covers the bump. The grid, the patterned dielectric layer, the patterned semiconductor layer and the patterned metal layer form a transistor. The planarization layer on the transistor has a contact window exposing a portion of the reflective pixel electrode. The transparent pixel electrode on the flat layer is electrically connected to the reflective pixel electrode through a contact window. The pixel structure provided by the invention can be used for manufacturing a transflective liquid crystal display by using a single liquid crystal cell gap process.

Description

Dot structure and manufacture method thereof

Technical field

The invention relates to a kind of dot structure and manufacture method thereof, particularly relevant for a kind of dot structure and manufacture method thereof with reflecting electrode.

Background technology

Universalness along with LCD, many portable type electronic products also little by little improve for the requirement of the Presentation Function of LCD, particularly portable type electronic product for example mobile phone (mobilephone), personal digital assistant (Personal Digital Assistant, PDA) or palmtop computer (PocketPC) etc.These portable type electronic products not only have good picture display effect at indoor needs, also need keep suitable picture quality simultaneously under outdoor or the environment of high light.

Therefore, how to allow LCD under the environment of high light, possess good display quality, just become one of the important trend of the technical development of LCD.For these reasons, prior art develops and a kind of semi-penetrated semi-reflected liquid crystal display (transflective LCD), and this semi-penetrated semi-reflected liquid crystal display is out of doors under the bright light environments and have display effect clearly under the indoor environment equally.

In existing semi-penetrated semi-reflected liquid crystal display, dot structure has and is suitable for the reflecting electrode of external light source reflection is constituted the echo area.The display effect that presents in order to make in the echo area can be consistent with the display effect that penetrating region presented that does not have reflecting electrode; usually can utilize a bed hedgehopping layer with the reflecting electrode bed hedgehopping, to form the semi-penetrated semi-reflected liquid crystal display in double liquid-crystal box gap (dual cell gap).In addition, also usually under reflecting electrode, dispose a plurality of photoresist projections (bump) in the existing dot structure, to promote the reflectivity of reflective pixel electrode.Yet reflecting electrode on bed hedgehopping layer, the bed hedgehopping layer and photoresist projection (bumps) are comparatively complicated on making, and expend cost.From the above, make the manufacturing technology steps of dot structure of semi-penetrated semi-reflected liquid crystal display simple, cheap can to take into account its quality again real in being difficult for for cost of manufacture.

Summary of the invention

The present invention provides a kind of dot structure, can use single liquid crystal box gap (single cell gap) technology, makes semi-penetrated semi-reflected liquid crystal display.

The present invention provides a kind of one pixel structure process method in addition, with under the prerequisite of simplifying processing step, makes reflectivity height and the preferable dot structure of quality.

The present invention proposes a kind of dot structure, is suitable for being disposed on the substrate (substrate).This dot structure comprises grid, pattern dielectric layer (patterned dielectric layer), patterned semiconductor layer, patterned metal layer, flatness layer (overcoat layer) and transparent pixels electrode (transparent pixelelectrode).Gate configuration is on substrate, and pattern dielectric layer is disposed on the substrate with cover gate.Patterned semiconductor layer is disposed on the pattern dielectric layer, and patterned semiconductor layer comprises channel layer and a plurality of projection that is disposed at the grid top.In addition, patterned metal layer comprises source electrode, drain electrode and the reflective pixel electrode that is connected with drain electrode, wherein source electrode and drain electrode cover the subregion of channel layer respectively, and reflective pixel electrode covers projection and grid, pattern dielectric layer, patterned semiconductor layer and patterned metal layer transistor formed.Flatness layer is disposed on the transistor, and wherein flatness layer has contact hole (contacthole), to expose the subregion of reflective pixel electrode.The transparent pixels electrode is disposed on the flatness layer, and is electrically connected (electrically connect) with reflective pixel electrode by contact hole.

In one embodiment of this invention, the superiors of above-mentioned patterned semiconductor layer, available deposition or doping way form an ohmic contact layer, and wherein ohmic contact layer is disposed between source electrode and the channel layer and between drain electrode and the channel layer, in order to form a thin-film transistor.

In one embodiment of this invention, pattern dielectric layer has identical pattern with patterned semiconductor layer, and pattern dielectric layer is between substrate and patterned semiconductor layer.

In one embodiment of this invention, be not patterned the pattern dielectric layer that semiconductor layer covers and have one first thickness, and the pattern dielectric layer that patterned semiconductor layer covered has one second thickness.First thickness for example be less than or equal second thickness.

In one embodiment of this invention, above-mentioned pattern dielectric layer only is distributed between patterned semiconductor layer and the substrate.

In one embodiment of this invention, dot structure also comprises protective layer, is disposed between flatness layer and the transistor.

In one embodiment of this invention, the dielectric coefficient of above-mentioned flatness layer for example is 2 to 7, and the thickness of flatness layer for example is to be 0.5 micron to 6 microns.

In one embodiment of this invention, the pattern dielectric layer of above-mentioned projection and this projection below is defined as projection, and the thickness of projection is 0.1 micron to 1.5 microns.

In one embodiment of this invention, dot structure also comprises the common electrode wire that is disposed on the substrate, and wherein common electrode wire constitutes storage capacitors with the reflective pixel electrode that is positioned at its top.

The present invention proposes a kind of one pixel structure process method in addition.At first, provide substrate, and form grid on substrate.Then, form pattern dielectric layer on substrate, and the pattern dielectric layer cover gate.Then, form patterned semiconductor layer on pattern dielectric layer, and patterned semiconductor layer comprises channel layer and a plurality of projection that is disposed at the grid top.Subsequently, form patterned metal layer on substrate, patterned metal layer comprises source electrode, drain electrode and the reflective pixel electrode that is connected with drain electrode.Source electrode and drain electrode cover the subregion of channel layer respectively, and reflective pixel electrode covers projection and grid, pattern dielectric layer, patterned semiconductor layer and patterned metal layer transistor formed.Afterwards, form flatness layer on transistor, and on flatness layer, make contact hole, to expose the subregion of reflective pixel electrode.Then, form the transparent pixels electrode on flatness layer, the transparent pixels electrode is electrically connected with reflective pixel electrode by contact hole.

In one embodiment of this invention, after the above-mentioned formation patterned metal layer, also comprise forming protective layer with covering transistor.

In one embodiment of this invention, the dielectric coefficient of above-mentioned flatness layer is 2 to 7, and its thickness for example is to be 0.5 micron to 6 microns.

In one embodiment of this invention, when forming grid, also comprise forming common electrode wire on substrate, and common electrode wire constitutes storage capacitors with the reflective pixel electrode that is positioned at its top.

In the one pixel structure process method of the present invention, when forming patterned semiconductor layer, form a plurality of projections and reflective pixel electrode is covered on the projection,, the reflectivity of reflective pixel electrode is improved by control projection angle and thickness.In addition, in the dot structure of the present invention, flatness layer can be covered on the reflecting electrode, to adjust the electric field of reflective pixel electrode top, and then make the semitransparent and half-reflective liquid crystal display of using this dot structure when the demonstration of pattern of penetrating and reflective-mode, have identical display effect.

Description of drawings

Figure 1A to Fig. 1 E be one embodiment of the invention dot structure manufacturing process on look schematic diagram.

Fig. 2 A is respectively the profile that hatching line AA ', hatching line BB ' along Figure 1A to Fig. 1 E and hatching line CC ' are illustrated to Fig. 2 E.

Fig. 3 A is the three-dimensional structure diagram of the liquid crystal panel of one embodiment of the invention.

Fig. 3 B is the three-dimensional structure diagram of the liquid crystal panel of another embodiment of the present invention.

Drawing reference numeral

100,312: dot structure

100a: echo area

100b: penetrating region

110: substrate

120: grid

122: common electrode wire

124: scan line

126: the drive circuit connection gasket

130: pattern dielectric layer

140: patterned semiconductor layer

142: channel layer

142a, 144a: ohmic contact layer

144: projection

150: patterned metal layer

152: source electrode

154: drain electrode

156: reflective pixel electrode

158: data wire

160: transistor

172: protective layer

174: flatness layer

176: contact hole

180: the transparent pixels electrode

300A, 300B: liquid crystal panel

310A, 310B: first substrate

320: the second substrates

330: liquid crystal layer

Embodiment

In general, in dot structure, dispose reflective pixel electrode, this dot structure had make the ability of light reflection, if in dot structure, dispose the zone outside the reflective pixel electrode simultaneously, configuration transparent pixels electrode, then this dot structure display mode that can have penetrating simultaneously and reflect.By the description of prior art as can be known; desire to make this type of dot structure to have good quality; usually can in dot structure, make the bed hedgehopping layer of reflective pixel electrode bed hedgehopping and the photoresist projection that improves reflectivity; but this practice will cause the making flow process of dot structure to become numerous and diverse, make output and product yield descend.For this reason, the present invention proposes a kind of one pixel structure process method, with under the prerequisite that can simplify process complexity, makes the good dot structure of quality.

For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.

Figure 1A is the top view of the one pixel structure process method of one embodiment of the invention to Fig. 1 E, and Fig. 2 A is respectively the profile that hatching line AA ', hatching line BB ' along Figure 1A to Fig. 1 E and hatching line CC ' are painted to Fig. 2 E.Please, provide substrate 110, and on substrate 110, form grid 120 earlier simultaneously with reference to Figure 1A and Fig. 2 A.The mode that forms grid 120 for example is to form gate material layers (not illustrating) on substrate 110 with sputtering technology, subsequently by etching technics with gate material layers (not illustrating) patterning, to form grid 120.In the step of patterning grid material layer (not illustrating), can on substrate 110, form common electrode wire 122, the scan line 124 that is connected with grid 120 and drive circuit connection gasket 126 simultaneously.

In the selection of material, substrate 110 can be transparent substrates such as glass substrate, plastic base, and the material of gate material layers (not illustrating) can be to be applied to any conductive material of grid 120 making or the combination of multiple conductive material in the technical field of the invention.For example, the material of gate material layers (not illustrating) for example is aluminium (Al), copper (Cu), molybdenum (Mo), silver (Ag), gold (Au), or alloy that these metals constituted or complex metal layer.

Then, please on substrate 110, form pattern dielectric layer 130 simultaneously with reference to Figure 1B and Fig. 2 B, and on pattern dielectric layer 130, form patterned semiconductor layer 140.At this moment, pattern dielectric layer 130 cover gate 120, and patterned semiconductor layer 140 comprises channel layer 142 and a plurality of projection 144 that is disposed at grid 120 tops.

In detail, the method for formation pattern dielectric layer 130 and patterned semiconductor layer 140 may further comprise the steps.At first, dielectric materials layer (not illustrating) is formed on the substrate 110, then semiconductor material layer is formed on the dielectric materials layer by another depositing operation by a depositing operation.In addition, the superiors of semi-conducting material are an ohmic contact layer, and its available deposition or doping way form.Then, carry out Patternized technique to remove partly dielectric materials layer and semiconductor material layer, for example, dielectric materials layer and semiconductor material layer can be removed simultaneously, to form pattern dielectric layer 130 and patterned semiconductor layer 140.Wherein, the material of pattern dielectric layer 130 for example is dielectric materials such as silicon dioxide, silicon nitride or silicon oxynitride, and the material of patterned semiconductor layer 140 for example is amorphous silicon or polysilicon.

In detail, after carrying out above-mentioned Patternized technique, can above grid 120, form channel layer 142 and ohmic contact layer 142a.In the present embodiment, the thickness of pattern dielectric layer 130 for example is 2500 dust to 5000 dusts or thinner, and the thickness of channel layer 142 for example is 500 dust to 2000 dusts or thinner, and the thickness of ohmic contact layer 142a for example is 200 dust to 700 dusts or thinner.

Specifically, when carrying out above-mentioned Patternized technique, for example be to carry out etching technics as shielding, to form patterned semiconductor layer 140 by a patterning photoresist.Then, utilize identical patterning photoresist or serve as that etching technics is proceeded in shielding, to form pattern dielectric layer 130 with patterned semiconductor layer 140.At this moment, pattern dielectric layer 130 has identical pattern with patterned semiconductor layer 140, and pattern dielectric layer 130 is between substrate 110 and patterned semiconductor layer 140.Therefore, shown in Fig. 2 B, the pattern dielectric layer 130 under projection 144 and the projection 144 for example can form projection.

In the middle of other embodiment, the number that can be removed with the control dielectric materials layer by the manufacturing conditions of adjusting Patternized technique.So, the pattern dielectric layer 130 that is covered by projection 144 can not have first thickness, and the pattern dielectric layer 130 that projection 144 is covered then has second thickness.Wherein, the missionary society of second thickness and first thickness influences the projection thickness variation.In brief, Tu Qi thickness is adjustable.In fact, Tu Qi thickness for example is 0.1 micron to 1.5 microns.In addition, the projection 144 or the side of projection and the angle of substrate 110 upper surfaces also can be adjusted at 5 ° to 45 ° by the control of Patternized technique.

Then, please on substrate 110, form patterned metal layer 150 simultaneously with reference to Fig. 1 C and Fig. 2 C.The mode that forms patterned metal layer 150 for example is to form metal level on substrate 110, and carries out Patternized technique with metal layer patternization.Patterned metal layer 150 comprise source electrode 152, the drain electrode 154 and with the drain electrode 154 reflective pixel electrodes that are connected 156, wherein source electrode 152 and drain electrode 154 cover the subregion of channel layer 142 respectively, and reflective pixel electrode 156 covers projection 144 (or projection), and ohmic contact layer 144a is between reflective pixel electrode 156 and projection 144.Simultaneously, when forming patterned metal layer 150, the part ohmic contact layer 142a that also can remove grid 120 tops is to expose the part channel layer 142 of grid 120 tops.At this moment, grid 120, pattern dielectric layer 130, patterned semiconductor layer 140 and patterned metal layer 150 meeting transistor formeds 160.In addition, when forming patterned metal layer 150, also can in same step, form the data wire 158 that is connected with source electrode 152.

In the present embodiment, patterned metal layer 150 can constitute reflective pixel electrode 156 with the ambient light line reflection.Simultaneously, patterned metal layer 150 covers the reflection efficiency that then helps to improve reflective pixel electrode 156 on the projection 144.In brief, among the present invention reflective pixel electrode 156 is covered on the projection 144 (or projection), can promotes the reflective surface area and the reflectivity of reflective pixel electrode 156.In addition, in the present embodiment, the angle of projection 144 (or projection) side and substrate 110 upper surfaces can be adjusted between 5 ° to 45 ° by technology controlling and process, so that reflective pixel electrode 156 has good reflectivity.In fact, the superiors' material of reflective pixel electrode 156 for example is silver (Ag), an aluminium (Al) or other has the electric conducting material of good reflection rate.

Form after the patterned metal layer 150, for example can on substrate 110, form a protective layer 172, so that transistor 160 is covered.The mode that forms protective layer 172 for example is to form dielectric film layers such as silicon dioxide, silicon nitride or silicon oxynitride with chemical vapor deposition method, with protective transistor 160, and makes it keep excellent electrical property.

Thereupon, please form flatness layer 174 on transistor 160 simultaneously with reference to Fig. 1 D and Fig. 2 D, and on flatness layer 174, make contact hole 176, to expose the subregion of reflective pixel electrode 156.The mode that forms flatness layer 174 for example is that the organic dielectric materials layer is coated on the transistor 160, and utilize little shadow (photolithography) technology with form flatness layer 174 with and on contact hole 176.For instance, organic dielectric materials for example is acryl resin or photoresist material etc.In fact, the dielectric coefficient of flatness layer 174 for example is 2 to 7, and its thickness for example is 0.5 micron to 6 microns.

Then, please form transparent pixels electrode 180 on flatness layer 174 simultaneously with reference to Fig. 1 E and Fig. 2 E, wherein transparent pixels electrode 180 is electrically connected with reflective pixel electrode 174 by contact hole 176.The generation type of transparent pixels electrode 180 can be to form electrically conducting transparent materials such as indium tin oxide or indium-zinc oxide on flatness layer 174, and with electrically conducting transparent material patterning to form transparent pixels electrode 180.

At this moment, the dot structure 100 that is disposed on the substrate 110 comprises grid 120, pattern dielectric layer 130, patterned semiconductor layer 140, patterned metal layer 150, flatness layer 174 and transparent pixels electrode 180.Grid 120 is disposed on the substrate 110, and pattern dielectric layer 130 is disposed on the substrate 110 with cover gate 120.Patterned semiconductor layer 140 is disposed on the pattern dielectric layer 130.Patterned semiconductor layer 140 comprises channel layer 142 and a plurality of projection 144 that is disposed at grid 120 tops.In addition, patterned metal layer 150 comprise source electrode 152, the drain electrode 154 and with the drain electrode 154 reflective pixel electrodes that are connected 156, wherein source electrode 152 and drain electrode 154 cover the subregion of channel layer 142 respectively, and reflective pixel electrode 156 covers projection 144 (or projection), and grid 120, pattern dielectric layer 130, patterned semiconductor layer 140 and patterned metal layer 150 transistor formeds 160.Flatness layer 174 is disposed on the transistor 160, and wherein flatness layer 174 has contact hole 176, to expose the subregion of reflective pixel electrode 156.Transparent pixels electrode 180 is disposed on the flatness layer 174, and is electrically connected with reflective pixel electrode 156 by contact hole 176.

By Fig. 1 E as can be known, dot structure 100 has allows the transparent pixels electrode 180 of light penetration and with the reflective pixel electrode 156 of light reflection, and two kinds of pixel electrodes 156,180 are electrically connected to each other by contact hole 176.Therefore, dot structure 100 is a transflective pixel structure.In dot structure 100, flatness layer 174 can influence the electric field of reflective pixel electrode 156 tops, makes that the electric field of reflective pixel electrode 156 tops is different with the electric field of transparent pixels electrode 180 tops.Therefore, dot structure 100 is applied on the LCD, then can makes the reflective display region at reflective pixel electrode 156 places and the viewing area that penetrates at transparent pixels electrode 180 places present roughly the same display effect by the thickness adjustment of flatness layer 174.In other words, when dot structure 100 is applied to semi-penetrated semi-reflected liquid crystal display, be not easy to penetrate the unbalanced phenomenon of display frame between viewing area and the reflective display region.

At present, mostly the design of most semi-penetrated semi-reflected liquid crystal display is to adopt the configuration of bed hedgehopping layer, forms double liquid-crystal box gap (dual cell gap), so that penetrate display frame uniformity between viewing area and the reflective display region.In comparison, the design of dot structure 100 of the present invention, can be by adjusting flatness layer thickness or material (dielectric coefficient), under single cel-gap (single cell gap) structure, reach and penetrate display frame uniformity between viewing area and the reflective display region, therefore the manufacturing process of dot structure 100 is comparatively simple, and manufacturing cost is also comparatively cheap.Further say, in the existing semi-penetrated semi-reflected liquid crystal display with double liquid-crystal box gap, edge at the bed hedgehopping layer, the ordered state of liquid crystal molecule is not easy to be controlled, there is the phenomenon of light leak to produce easily, and then makes the display quality of semi-penetrated semi-reflected liquid crystal display glide.Relatively, because the dot structure 100 of present embodiment has single cel-gap, therefore be difficult for having the phenomenon of light leak to produce.

In addition, Fig. 3 A and Fig. 3 B illustrate the three-dimensional structure diagram of the liquid crystal panel of two kinds of embodiment of the present invention.Please earlier with reference to Fig. 3 A, liquid crystal panel 300A comprises the first substrate 310A, second substrate 320 and liquid crystal layer 330.Wherein, the first substrate 310A comprises the described dot structure 100 of the foregoing description of a plurality of arrayed, and second substrate 320 and the first substrate 310A subtend are provided with.330 of liquid crystal layers are arranged between the first substrate 310A and second substrate 320.

What deserves to be mentioned is that each dot structure 100 has an echo area 100a and a penetrating region 100b.Please be simultaneously with reference to Fig. 1 E and Fig. 3 A, the dot structure 100 of present embodiment for example is a transflective pixel structure 100, wherein reflective pixel electrode 156 is positioned at echo area 100a and transparent pixels electrode 180 is positioned at penetrating region 100b.

On the other hand, among the liquid crystal panel 300B, the dot structure 312 of the first substrate 310B can be a reflective pixel structure (as the dot structure 312 of Fig. 3 B).In detail, in the dot structure 312, reflective pixel electrode can be distributed in the whole viewing area.

In sum, dot structure of the present invention and manufacture method thereof have the advantage of the following stated at least:

1. in the dot structure of the present invention, projection is to utilize that existing rete is made in the transistor, and therefore the making of projection need not increase extra processing step.

2. in the dot structure of the present invention, the thickness and the external form of projection can change by control of process condition, and then improve the reflectivity that is covered in the reflective pixel electrode on the projection more efficiently.

3. dot structure of the present invention has single cel-gap, so be difficult for having the phenomenon of light leak to produce.

Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.

Claims

1. A pixel structure suitable for being configured on a substrate, wherein the pixel structure comprises:

a gate configured on the substrate;

a patterned dielectric layer disposed on the substrate to cover the gate;

A patterned semiconductor layer disposed on the patterned dielectric layer, the patterned semiconductor layer including a channel layer disposed above the gate and a plurality of bumps;

A patterned metal layer, including a source, a drain, and a reflective pixel electrode connected to the drain, wherein the source and the drain respectively cover part of the channel layer, and The reflective pixel electrode covers the bumps, and the gate, the patterned dielectric layer, the patterned semiconductor layer, the source and the drain constitute a transistor;

a planar layer disposed on the transistor, wherein the planar layer has a contact window to expose a part of the reflective pixel electrode; and

A transparent pixel electrode is arranged on the flat layer and electrically connected with the reflective pixel electrode through the contact window.

2. The pixel structure according to claim 1, wherein said patterned semiconductor layer further comprises an ohmic contact layer disposed between said source electrode and said channel layer and said between the drain and the channel layer.

3. The pixel structure according to claim 1, wherein the patterned dielectric layer has the same pattern as the patterned semiconductor layer, and the patterned dielectric layer is located on the between the substrate and the patterned semiconductor layer.

4. The pixel structure according to claim 1, wherein the patterned dielectric layer not covered by the patterned semiconductor layer has a first thickness, and is patterned by the patterned The patterned dielectric layer covered by the semiconductor layer has a second thickness, and the first thickness is less than or equal to the second thickness.

5. The pixel structure according to claim 1, wherein the patterned dielectric layer is only distributed between the patterned semiconductor layer and the substrate.

6 . The pixel structure according to claim 1 , further comprising a protection layer disposed between the planar layer and the transistor.

7. The pixel structure according to claim 1, wherein the dielectric constant of the planar layer is 2-7.

8. The pixel structure according to claim 1, wherein the flat layer has a thickness of 0.5 microns to 6 microns.

9. The pixel structure according to claim 1, wherein the bump and the patterned dielectric layer directly below the bump form a protrusion, and the thickness of the protrusion is 0.1 microns to 1.5 microns.

10. The pixel structure according to claim 1, characterized in that, the pixel structure further comprises a common electrode line disposed on the substrate, wherein the common electrode line is connected to the above-mentioned common electrode line The reflective pixel electrodes form a storage capacitor.

11. A method for manufacturing a pixel structure, characterized in that the method for manufacturing a pixel structure comprises:

providing a substrate;

forming a gate on the substrate;

forming a patterned dielectric layer on the substrate, and the patterned dielectric layer covers the gate;

forming a patterned semiconductor layer on the patterned dielectric layer, and the patterned semiconductor layer includes a channel layer and a plurality of bumps disposed above the gate;

forming a patterned metal layer on the substrate, the patterned metal layer includes a source, a drain and a reflective pixel electrode connected to the drain, wherein the source and the The drain electrodes cover part of the channel layer respectively, and the reflective pixel electrodes cover the bumps, and the grid, the patterned dielectric layer, and the pattern The semiconductor layer, the source and the drain form a transistor;

forming a flat layer on the transistor;

making a contact window on the planar layer to expose a part of the reflective pixel electrode; and

A transparent pixel electrode is formed on the planar layer, and the transparent pixel electrode is electrically connected with the reflective pixel electrode through the contact window.

12. The manufacturing method of the pixel structure according to claim 11, wherein the step of forming the patterned semiconductor layer comprises sequentially forming a semiconductor layer and an ohmic contact layer, wherein the ohmic contact layer It is arranged between the source electrode and the channel layer and between the drain electrode and the channel layer.

13. The method for manufacturing a pixel structure according to claim 11, wherein the patterned dielectric layer has the same pattern as the patterned semiconductor layer, and the patterned dielectric layer It is located between the substrate and the patterned semiconductor layer.

14. The method for manufacturing a pixel structure according to claim 11, wherein the patterned dielectric layer not covered by the patterned semiconductor layer has a first thickness, and is covered by the patterned semiconductor layer. The patterned dielectric layer covered by the patterned semiconductor layer has a second thickness, and the first thickness is less than or equal to the second thickness.

15. The method for manufacturing a pixel structure according to claim 11, wherein the patterned dielectric layer is only distributed between the patterned semiconductor layer and the substrate.

16 . The manufacturing method of the pixel structure according to claim 11 , further comprising forming a protection layer to cover the transistor after forming the patterned metal layer.

17. The manufacturing method of the pixel structure according to claim 11, wherein the thickness of the planar layer is 0.5 microns to 6 microns.

18. The method for manufacturing a pixel structure according to claim 11, wherein the bump and the patterned dielectric layer directly below the bump form a bump, and the The thickness of the protrusions is 0.1 micron to 1.5 micron.

19. The method for manufacturing a pixel structure according to claim 11, wherein while forming the gate, it also includes forming a common electrode line on the substrate, and the common electrode line A storage capacitor is formed with the reflective pixel electrode above it.

20. The method for manufacturing a pixel structure according to claim 11, wherein the steps of forming the patterned dielectric layer and forming the patterned semiconductor layer comprise:

sequentially forming a dielectric material layer and a semiconductor material layer on the substrate and covering the gate; and

Simultaneously patterning the dielectric material layer and the semiconductor material layer to form the patterned dielectric layer and the patterned semiconductor layer, wherein the patterned dielectric layer covers the gate pole, the patterned semiconductor layer includes the channel layer disposed above the gate and the bumps.