CN101030587A - Pixel structure and manufacturing method thereof - Google Patents

Abstract

The invention relates to a pixel structure and a manufacturing method thereof. The pixel structure comprises a grid electrode, a patterned dielectric layer, a patterned semiconductor layer, a patterned metal layer, a flat layer and a transparent pixel electrode. The grid and the patterned dielectric layer covering the grid are all arranged on the substrate. The patterned semiconductor layer on the patterned dielectric layer comprises a channel layer and a plurality of bumps above the gate. The patterned metal layer comprises a source electrode, a drain electrode and a reflective pixel electrode connected with the drain electrode. The source electrode and the drain electrode respectively cover a part of the channel layer. The reflective pixel electrode covers the bump. The grid, the patterned dielectric layer, the patterned semiconductor layer and the patterned metal layer form a transistor. The planarization layer on the transistor has a contact window exposing a portion of the reflective pixel electrode. The transparent pixel electrode on the flat layer is electrically connected to the reflective pixel electrode through a contact window. The pixel structure provided by the invention can be used for manufacturing a transflective liquid crystal display by using a single liquid crystal cell gap process.

Description

Pixel structure and manufacturing method thereof

technical field

The present invention relates to a pixel structure and a manufacturing method thereof, in particular to a pixel structure with reflective electrodes and a manufacturing method thereof.

Background technique

With the popularity of liquid crystal displays, many portable electronic products have gradually increased the display function requirements of liquid crystal displays, especially portable electronic products such as mobile phones (mobilephone), personal digital assistant (Personal Digital Assistant, PDA) or palm-sized Computer (PocketPC), etc. These portable electronic products not only need to have a good picture display effect indoors, but also need to maintain an appropriate picture quality outdoors or in a strong light environment.

Therefore, how to maintain a good display quality of the liquid crystal display in a strong light environment has become one of the important trends in the technical development of the liquid crystal display. Based on the above reasons, a transflective liquid crystal display (transflective LCD) has been developed in the prior art, and the transflective liquid crystal display also has a clear display effect in bright outdoor environments and indoor environments.

In the existing transflective liquid crystal display, the pixel structure has a reflective electrode suitable for reflecting the external light source to form a reflective area. In order to make the display effect presented in the reflective area consistent with the display effect presented in the transmissive area without reflective electrodes, a layer of layer is usually used to raise the reflective electrodes to form a dual cell gap. transflective LCD display. In addition, in the existing pixel structure, a plurality of photoresist bumps are usually arranged under the reflective electrode to improve the reflectivity of the reflective pixel electrode. However, the pad layer, reflective electrodes on the pad layer, and photoresist bumps are complex and costly to manufacture. Based on the above, it is not easy to make the pixel structure of the transflective liquid crystal display with simple manufacturing process steps, low manufacturing cost and high quality.

Contents of the invention

The present invention provides a pixel structure, which can be used to manufacture a semi-transmissive and semi-reflective liquid crystal display by using a single cell gap process.

The present invention also provides a method for manufacturing a pixel structure, so as to manufacture a pixel structure with high reflectivity and better quality under the premise of simplifying the process steps.

The present invention provides a pixel structure suitable for disposing on a substrate. The pixel structure includes a gate, a patterned dielectric layer, a patterned semiconductor layer, a patterned metal layer, an overcoat layer and a transparent pixel electrode. The gate is disposed on the substrate, and the patterned dielectric layer is disposed on the substrate to cover the gate. The patterned semiconductor layer is disposed on the patterned dielectric layer, and the patterned semiconductor layer includes a channel layer disposed above the gate and a plurality of bumps. In addition, the patterned metal layer includes a source, a drain, and a reflective pixel electrode connected to the drain, wherein the source and the drain respectively cover a part of the channel layer, and the reflective pixel electrode covers the bump, and the gate, patterned The dielectric layer, the patterned semiconductor layer and the patterned metal layer form a transistor. The planar layer is disposed on the transistor, wherein the planar layer has a contact hole to expose a part of the reflective pixel electrode. The transparent pixel electrode is disposed on the flat layer and is electrically connected to the reflective pixel electrode through the contact window.

In an embodiment of the present invention, the uppermost layer of the above-mentioned patterned semiconductor layer can be deposited or doped to form an ohmic contact layer, wherein the ohmic contact layer is disposed between the source electrode and the channel layer and between the drain electrode and the channel layer Between, to form a thin film transistor.

In an embodiment of the invention, the patterned dielectric layer and the patterned semiconductor layer have the same pattern, and the patterned dielectric layer is located between the substrate and the patterned semiconductor layer.

In an embodiment of the invention, the patterned dielectric layer not covered by the patterned semiconductor layer has a first thickness, and the patterned dielectric layer covered by the patterned semiconductor layer has a second thickness. The first thickness is, for example, smaller than or equal to the second thickness.

In an embodiment of the present invention, the above-mentioned patterned dielectric layer is only distributed between the patterned semiconductor layer and the substrate.

In an embodiment of the present invention, the pixel structure further includes a protection layer disposed between the flat layer and the transistor.

In an embodiment of the present invention, the dielectric constant of the planar layer is, for example, 2 to 7, and the thickness of the planar layer is, for example, 0.5 microns to 6 microns.

In an embodiment of the present invention, the above-mentioned bumps and the patterned dielectric layer below the bumps are defined as protrusions, and the thickness of the protrusions is 0.1 μm to 1.5 μm.

In an embodiment of the present invention, the pixel structure further includes a common electrode line disposed on the substrate, wherein the common electrode line and the reflective pixel electrode above it form a storage capacitor.

The invention further provides a method for manufacturing the pixel structure. Firstly, a substrate is provided, and a gate is formed on the substrate. Then, a patterned dielectric layer is formed on the substrate, and the patterned dielectric layer covers the gate. Then, a patterned semiconductor layer is formed on the patterned dielectric layer, and the patterned semiconductor layer includes a channel layer and a plurality of bumps disposed above the gate. Subsequently, a patterned metal layer is formed on the substrate, and the patterned metal layer includes a source, a drain, and a reflective pixel electrode connected to the drain. The source electrode and the drain electrode respectively cover part of the channel layer, and the reflective pixel electrode covers the bump, and the gate, the patterned dielectric layer, the patterned semiconductor layer and the patterned metal layer form a transistor. Afterwards, a flat layer is formed on the transistor, and a contact window is made on the flat layer to expose a part of the reflective pixel electrode. Then, a transparent pixel electrode is formed on the flat layer, and the transparent pixel electrode is electrically connected with the reflective pixel electrode through the contact window.

In an embodiment of the invention, the patterned dielectric layer and the patterned semiconductor layer have the same pattern, and the patterned dielectric layer is located between the substrate and the patterned semiconductor layer.

In an embodiment of the invention, the patterned dielectric layer not covered by the patterned semiconductor layer has a first thickness, and the patterned dielectric layer covered by the patterned semiconductor layer has a second thickness. The first thickness is, for example, smaller than or equal to the second thickness.

In an embodiment of the present invention, the above-mentioned patterned dielectric layer is only distributed between the patterned semiconductor layer and the substrate.

In an embodiment of the present invention, after forming the patterned metal layer, forming a protection layer to cover the transistor is further included.

In an embodiment of the present invention, the dielectric coefficient of the above-mentioned planar layer is 2 to 7, and its thickness is, for example, 0.5 μm to 6 μm.

In an embodiment of the present invention, the above-mentioned bump and the patterned dielectric layer below the bump are defined as protrusions, and the thickness of the protrusions is 0.1 μm to 1.5 μm.

In an embodiment of the present invention, while forming the gate, it also includes forming a common electrode line on the substrate, and the common electrode line and the reflective pixel electrode above it form a storage capacitor.

In the manufacturing method of the pixel structure of the present invention, while forming the patterned semiconductor layer, a plurality of bumps are formed and the reflective pixel electrodes are covered on the bumps. By controlling the angle and thickness of the bumps, the reflection of the reflective pixel electrodes can be made rate increased. In addition, in the pixel structure of the present invention, a flat layer can be covered on the reflective electrode to adjust the electric field above the reflective pixel electrode, so that the transflective liquid crystal display using this pixel structure can perform transmissive mode and reflective mode. When displayed, it has the same display effect.

Description of drawings

1A to 1E are schematic top views of the manufacturing process of the pixel structure according to an embodiment of the present invention.

2A to FIG. 2E are cross-sectional views along the section line AA', section line BB' and section line CC' of FIG. 1A to FIG. 1E respectively.

FIG. 3A is a three-dimensional structure diagram of a liquid crystal panel according to an embodiment of the present invention.

FIG. 3B is a three-dimensional structure diagram of a liquid crystal panel according to another embodiment of the present invention.

Reference number

100, 312: pixel structure

100a: reflective area

100b: Penetration zone

110: Substrate

120: grid

122: common electrode line

124: scan line

126: Drive circuit connection pad

130: patterned dielectric layer

140: Patterned semiconductor layer

142: Channel layer

142a, 144a: ohmic contact layer

144: Bump

150: patterned metal layer

152: source

154: drain

156: reflective pixel electrode

158: data line

160: Transistor

172: protective layer

174: flat layer

176: contact window

180: transparent pixel electrode

300A, 300B: LCD panel

310A, 310B: first substrate

320: second substrate

330: liquid crystal layer

Detailed ways

Generally speaking, disposing reflective pixel electrodes in the pixel structure can make the pixel structure have the ability to reflect light. It has both transmissive and reflective display modes. It can be seen from the description of the prior art that in order to make this type of pixel structure have good quality, a pad layer for padding the reflective pixel electrode and a photoresist bump to improve the reflectivity are usually made in the pixel structure, but this method will lead to The manufacturing process of the pixel structure becomes complicated, which reduces the output and product yield. Therefore, the present invention proposes a method for manufacturing a pixel structure, so as to manufacture a pixel structure with good quality under the premise of simplifying the process complexity.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with accompanying drawings.

1A to 1E are top views of a method for manufacturing a pixel structure according to an embodiment of the present invention, and FIGS. 2A to 2E are respectively along the section lines AA', BB' and CC of FIGS. 1A to 1E 'The profile drawn. Referring to FIG. 1A and FIG. 2A simultaneously, a substrate 110 is provided, and a gate 120 is formed on the substrate 110 . The way of forming the gate 120 is, for example, to form a gate material layer (not shown) on the substrate 110 by a sputtering process, and then pattern the gate material layer (not shown) by an etching process to form the gate 120 . In the step of patterning the gate material layer (not shown), the common electrode line 122 , the scan line 124 connected to the gate 120 and the driving circuit connection pad 126 can be formed on the substrate 110 at the same time.

In terms of material selection, the substrate 110 can be a light-transmitting substrate such as a glass substrate or a plastic substrate, and the material of the gate material layer (not shown) can be any of the materials used in the fabrication of the gate 120 in the technical field of the present invention. Conductive material or a combination of multiple conductive materials. For example, the material of the gate material layer (not shown) is aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), gold (Au), or an alloy composed of these metals. or composite metal layers.

Next, please refer to FIG. 1B and FIG. 2B simultaneously, a patterned dielectric layer 130 is formed on the substrate 110 , and a patterned semiconductor layer 140 is formed on the patterned dielectric layer 130 . At this time, the patterned dielectric layer 130 covers the gate 120 , and the patterned semiconductor layer 140 includes a channel layer 142 and a plurality of bumps 144 disposed above the gate 120 .

In detail, the method for forming the patterned dielectric layer 130 and the patterned semiconductor layer 140 includes the following steps. First, a dielectric material layer (not shown) is formed on the substrate 110 through a deposition process, and then a semiconductor material layer is formed on the dielectric material layer through another deposition process. In addition, the uppermost layer of semiconductor material is an ohmic contact layer, which can be formed by deposition or doping. Then, a patterning process is performed to remove part of the dielectric material layer and the semiconductor material layer. For example, the dielectric material layer and the semiconductor material layer can be removed at the same time to form the patterned dielectric layer 130 and the patterned semiconductor layer. Layer 140. Wherein, the material of the patterned dielectric layer 130 is, for example, a dielectric material such as silicon dioxide, silicon nitride, or silicon oxynitride, and the material of the patterned semiconductor layer 140 is, for example, amorphous silicon or polysilicon.

In detail, after the above patterning process is performed, the channel layer 142 and the ohmic contact layer 142 a may be formed on the gate 120 . In this embodiment, the thickness of the patterned dielectric layer 130 is, for example, 2500 angstroms to 5000 angstroms or less, the thickness of the channel layer 142 is, for example, 500 angstroms to 2000 angstroms or less, and the thickness of the ohmic contact layer 142a For example, it is 200 angstroms to 700 angstroms or thinner.

Specifically, when performing the above patterning process, for example, a patterned photoresist is used as a mask to perform an etching process to form the patterned semiconductor layer 140 . Next, the etching process is continued by using the same patterned photoresist or using the patterned semiconductor layer 140 as a mask to form the patterned dielectric layer 130 . At this time, the patterned dielectric layer 130 has the same pattern as the patterned semiconductor layer 140 , and the patterned dielectric layer 130 is located between the substrate 110 and the patterned semiconductor layer 140 . Therefore, as shown in FIG. 2B , the bump 144 and the patterned dielectric layer 130 directly below the bump 144 may form a bump, for example.

In other embodiments, the removed amount of the dielectric material layer can be controlled by adjusting the manufacturing conditions of the patterning process. In this way, the patterned dielectric layer 130 not covered by the bumps 144 may have a first thickness, while the patterned dielectric layer 130 covered by the bumps 144 has a second thickness. Wherein, the difference between the second thickness and the first thickness will affect the variation of the protrusion thickness. In short, the thickness of the protrusions can be adjusted. In practice, the thickness of the protrusions is, for example, 0.1 microns to 1.5 microns. In addition, the included angle between the bump 144 or the side of the protrusion and the upper surface of the substrate 110 can also be adjusted within 5° to 45° through the control of the patterning process.

Then, referring to FIG. 1C and FIG. 2C simultaneously, a patterned metal layer 150 is formed on the substrate 110 . The method of forming the patterned metal layer 150 is, for example, forming a metal layer on the substrate 110 and performing a patterning process to pattern the metal layer. The patterned metal layer 150 includes a source 152, a drain 154, and a reflective pixel electrode 156 connected to the drain 154, wherein the source 152 and the drain 154 respectively cover part of the channel layer 142, and the reflective pixel electrode 156 covers the bump 144 (or bump), the ohmic contact layer 144 a is located between the reflective pixel electrode 156 and the bump 144 . Meanwhile, when forming the patterned metal layer 150 , part of the ohmic contact layer 142 a above the gate 120 may also be removed to expose part of the channel layer 142 above the gate 120 . At this time, the gate 120 , the patterned dielectric layer 130 , the patterned semiconductor layer 140 and the patterned metal layer 150 will form a transistor 160 . In addition, when the patterned metal layer 150 is formed, the data line 158 connected to the source electrode 152 can also be formed in the same step.

In this embodiment, the patterned metal layer 150 can reflect external light to form the reflective pixel electrode 156 . At the same time, the patterned metal layer 150 covering the bump 144 helps to improve the reflection efficiency of the reflective pixel electrode 156 . In short, in the present invention, the reflective pixel electrodes 156 are covered on the bumps 144 (or protrusions), which can increase the reflective area and reflectivity of the reflective pixel electrodes 156 . In addition, in this embodiment, the included angle between the side surface of the bump 144 (or protrusion) and the upper surface of the substrate 110 can be adjusted to be between 5° and 45° through process control, so that the reflective pixel electrode 156 has good reflection Rate. In essence, the material of the uppermost layer of the reflective pixel electrode 156 is, for example, silver (Ag), aluminum (Al) or other conductive materials with good reflectivity.

After forming the patterned metal layer 150 , for example, a protection layer 172 may be formed on the substrate 110 to cover the transistor 160 . The protective layer 172 is formed, for example, by chemical vapor deposition to form a dielectric film such as silicon dioxide, silicon nitride, or silicon oxynitride to protect the transistor 160 and maintain good electrical properties.

Then, referring to FIG. 1D and FIG. 2D , a flat layer 174 is formed on the transistor 160 , and a contact window 176 is formed on the flat layer 174 to expose a part of the reflective pixel electrode 156 . The method of forming the flat layer 174 is, for example, coating an organic dielectric material layer on the transistor 160 and using a photolithography process to form the flat layer 174 and the contact window 176 thereon. For example, the organic dielectric material is acrylic resin or photoresist material. In essence, the dielectric constant of the flat layer 174 is, for example, 2 to 7, and its thickness is, for example, 0.5 microns to 6 microns.

Then, referring to FIG. 1E and FIG. 2E , a transparent pixel electrode 180 is formed on the flat layer 174 , wherein the transparent pixel electrode 180 is electrically connected to the reflective pixel electrode 174 through the contact window 176 . The transparent pixel electrode 180 can be formed by forming a transparent conductive material such as indium tin oxide or indium zinc oxide on the flat layer 174 , and patterning the transparent conductive material to form the transparent pixel electrode 180 .

At this point, the pixel structure 100 disposed on the substrate 110 includes a gate 120 , a patterned dielectric layer 130 , a patterned semiconductor layer 140 , a patterned metal layer 150 , a flat layer 174 and a transparent pixel electrode 180 . The gate 120 is disposed on the substrate 110 , and the patterned dielectric layer 130 is disposed on the substrate 110 to cover the gate 120 . The patterned semiconductor layer 140 is disposed on the patterned dielectric layer 130 . The patterned semiconductor layer 140 includes a channel layer 142 disposed above the gate 120 and a plurality of bumps 144 . In addition, the patterned metal layer 150 includes a source 152 , a drain 154 , and a reflective pixel electrode 156 connected to the drain 154 , wherein the source 152 and the drain 154 cover part of the channel layer 142 respectively, and the reflective pixel electrode 156 covers The bump 144 (or protrusion), and the gate 120 , the patterned dielectric layer 130 , the patterned semiconductor layer 140 and the patterned metal layer 150 form a transistor 160 . The flat layer 174 is disposed on the transistor 160 , wherein the flat layer 174 has a contact window 176 to expose a part of the reflective pixel electrode 156 . The transparent pixel electrode 180 is disposed on the planar layer 174 and electrically connected to the reflective pixel electrode 156 through the contact window 176 .

As can be seen from FIG. 1E , the pixel structure 100 has a transparent pixel electrode 180 that allows light to pass through and a reflective pixel electrode 156 that reflects light, and the two pixel electrodes 156 and 180 are electrically connected to each other through the contact window 176 . Therefore, the pixel structure 100 is a transflective pixel structure. In the pixel structure 100 , the planarization layer 174 affects the electric field above the reflective pixel electrode 156 such that the electric field above the reflective pixel electrode 156 is different from the electric field above the transparent pixel electrode 180 . Therefore, when the pixel structure 100 is applied to a liquid crystal display, the reflective display area where the reflective pixel electrode 156 is located and the transmissive display area where the transparent pixel electrode 180 is located can exhibit approximately the same display effect through adjusting the thickness of the flat layer 174 . In other words, when the pixel structure 100 is applied to a transflective liquid crystal display, it is not easy to cause an unbalanced display image between the transmissive display area and the reflective display area.

At present, most of the semi-transmissive and semi-reflective liquid crystal displays are designed with a layered configuration to form a dual cell gap (dual cell gap), so that the display screen between the transmissive display area and the reflective display area is uniform. . In contrast, the design of the pixel structure 100 of the present invention can achieve the transmissive display area and the reflective display area under the single cell gap structure by adjusting the flat layer thickness or material (dielectric coefficient). The display images are uniform and consistent, so the manufacturing process of the pixel structure 100 is relatively simple, and the manufacturing cost is also relatively low. Furthermore, in the existing transflective liquid crystal display with double liquid crystal cell gaps, at the edge of the pad layer, the alignment state of the liquid crystal molecules is less likely to be controlled, and light leakage is prone to occur, which in turn makes The display quality of transflective LCD monitors deteriorates. In contrast, since the pixel structure 100 of the present embodiment has a single liquid crystal cell gap, light leakage is less likely to occur.

In addition, FIG. 3A and FIG. 3B are three-dimensional structural diagrams of liquid crystal panels according to two embodiments of the present invention. Please refer to FIG. 3A , the liquid crystal panel 300A includes a first substrate 310A, a second substrate 320 and a liquid crystal layer 330 . Wherein, the first substrate 310A includes a plurality of pixel structures 100 described in the above embodiments arranged in an array, and the second substrate 320 is disposed opposite to the first substrate 310A. The liquid crystal layer 330 is disposed between the first substrate 310A and the second substrate 320 .

It is worth mentioning that each pixel structure 100 has a reflective region 100a and a transmissive region 100b. Please refer to FIG. 1E and FIG. 3A at the same time. The pixel structure 100 of this embodiment is, for example, a transflective pixel structure 100, wherein the reflective pixel electrode 156 is located in the reflective region 100a and the transparent pixel electrode 180 is located in the transmissive region 100b.

On the other hand, in the liquid crystal panel 300B, the pixel structure 312 of the first substrate 310B may be a reflective pixel structure (such as the pixel structure 312 in FIG. 3B ). In detail, in the pixel structure 312, the reflective pixel electrodes may be distributed in the entire display area.

To sum up, the pixel structure and its manufacturing method of the present invention have at least the following advantages:

1. In the pixel structure of the present invention, the bumps are fabricated by using the existing film layers in the transistor, so the fabrication of the bumps does not require additional process steps.

2. In the pixel structure of the present invention, the thickness and shape of the protrusion can be changed through the control of the process conditions, thereby more efficiently improving the reflectivity of the reflective pixel electrode covering the protrusion.

3. The pixel structure of the present invention has a single liquid crystal cell gap, so light leakage is not easy to occur.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (20)

1. a dot structure is suitable for being disposed on the substrate, it is characterized in that, described dot structure comprises:

One grid is disposed on the described substrate;

One pattern dielectric layer is disposed on the described substrate to cover described grid;

One patterned semiconductor layer is disposed on the described pattern dielectric layer, and described patterned semiconductor layer comprises that one is disposed at channel layer and a plurality of projection of described grid top;

One patterned metal layer, comprise one source pole, a drain electrode and a reflective pixel electrode that is connected with this drain electrode, wherein said source electrode and described drain electrode cover the subregion of described channel layer respectively, and described reflective pixel electrode covers described these projections, and described grid, described pattern dielectric layer, described patterned semiconductor layer, described source electrode and described drain electrode constitute a transistor;

One flatness layer is disposed on the described transistor, and wherein said flatness layer has a contact hole, to expose the subregion of described reflective pixel electrode; And

One transparent pixels electrode is disposed on the described flatness layer, and is electrically connected with described reflective pixel electrode by described contact hole.

2. dot structure according to claim 1 is characterized in that wherein said patterned semiconductor layer also comprises an ohmic contact layer, is disposed between described source electrode and the described channel layer and between described drain electrode and the described channel layer.

3. dot structure according to claim 1, it is characterized in that, wherein said pattern dielectric layer has identical pattern with described patterned semiconductor layer, and described pattern dielectric layer is between described substrate and described patterned semiconductor layer.

4. dot structure according to claim 1, it is characterized in that, wherein do not had one first thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and had one second thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and described first thickness is less than or equal to described second thickness.

5. dot structure according to claim 1 is characterized in that, wherein said pattern dielectric layer only is distributed between described patterned semiconductor layer and the described substrate.

6. dot structure according to claim 1 is characterized in that described dot structure also comprises a protective layer, is disposed between described flatness layer and the described transistor.

7. dot structure according to claim 1 is characterized in that the dielectric coefficient of wherein said flatness layer is about 2 to 7.

8. dot structure according to claim 1 is characterized in that, the thickness of wherein said flatness layer is about 0.5 micron to 6 microns.

9. dot structure according to claim 1 is characterized in that, the described pattern dielectric layer under wherein said projection and this projection forms a projection, and the thickness of described projection is about 0.1 micron to 1.5 microns.

10. dot structure according to claim 1, it is characterized in that, described dot structure comprises that also one is disposed at the common electrode wire on the described substrate, and wherein said common electrode wire constitutes a storage capacitors with the described reflective pixel electrode that is positioned at its top.

11. an one pixel structure process method is characterized in that, described one pixel structure process method comprises:

One substrate is provided;

Form a grid on described substrate;

Form a pattern dielectric layer on described substrate, and described pattern dielectric layer covers described grid;

Form a patterned semiconductor layer on described pattern dielectric layer, and described patterned semiconductor layer comprises that one is disposed at channel layer and a plurality of projection of described grid top;

Form a patterned metal layer on described substrate, described patterned metal layer comprises one source pole, a drain electrode and a reflective pixel electrode that is connected with described drain electrode, wherein said source electrode and described drain electrode cover the subregion of described channel layer respectively, and described reflective pixel electrode covers described these projections, and described grid, described pattern dielectric layer, described patterned semiconductor layer, described source electrode and described drain electrode constitute a transistor;

Form a flatness layer on described transistor;

On described flatness layer, make a contact hole, to expose the subregion of described reflective pixel electrode; And

Form a transparent pixels electrode on described flatness layer, described transparent pixels electrode is electrically connected with described reflective pixel electrode by described contact hole.

12. one pixel structure process method according to claim 11, it is characterized in that, the step that wherein forms described patterned semiconductor layer comprises and forms a semi-conductor layer and an ohmic contact layer in regular turn, and wherein said ohmic contact layer is disposed between described source electrode and the described channel layer and between described drain electrode and the described channel layer.

13. one pixel structure process method according to claim 11, it is characterized in that, wherein said pattern dielectric layer has identical pattern with described patterned semiconductor layer, and described pattern dielectric layer is between described substrate and described patterned semiconductor layer.

14. one pixel structure process method according to claim 11, it is characterized in that, do not had one first thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and had one second thickness by the described pattern dielectric layer that described patterned semiconductor layer covered, and described first thickness is less than or equal to described second thickness.

15. one pixel structure process method according to claim 11 is characterized in that, wherein said pattern dielectric layer only is distributed between described patterned semiconductor layer and the described substrate.

16. one pixel structure process method according to claim 11 is characterized in that, wherein forms after the described patterned metal layer, also comprises forming a protective layer to cover described transistor.

17. one pixel structure process method according to claim 11 is characterized in that, the thickness of wherein said flatness layer is about 0.5 micron to 6 microns.

18. one pixel structure process method according to claim 11 is characterized in that, the described pattern dielectric layer under wherein said projection and the described projection forms a projection, and the thickness of described projection is about 0.1 micron to 1.5 microns.

19. one pixel structure process method according to claim 11, it is characterized in that, when wherein forming described grid, also comprise forming a common electrode line on described substrate, and described common electrode wire constitutes a storage capacitors with the described reflective pixel electrode that is positioned at its top.

20. one pixel structure process method according to claim 11 is characterized in that, the step that wherein forms described pattern dielectric layer and form described patterned semiconductor layer comprises:

Form a dielectric materials layer and semiconductor material layer in regular turn on described substrate and cover described grid; And

Described dielectric materials layer of patterning and described semiconductor material layer are to form described pattern dielectric layer and described patterned semiconductor layer simultaneously, wherein said pattern dielectric layer covers described grid, and described patterned semiconductor layer comprises described channel layer and described these projections that are disposed at described grid top.

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