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CN101295095B - Semi-penetration semi-reflection type liquid crystal display panel and manufacturing method thereof - Google Patents

Semi-penetration semi-reflection type liquid crystal display panel and manufacturing method thereof Download PDF

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CN101295095B
CN101295095B CN2008101093629A CN200810109362A CN101295095B CN 101295095 B CN101295095 B CN 101295095B CN 2008101093629 A CN2008101093629 A CN 2008101093629A CN 200810109362 A CN200810109362 A CN 200810109362A CN 101295095 B CN101295095 B CN 101295095B
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dielectric layer
interlayer dielectric
layer
electrode
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CN101295095A (en
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陈昱丞
杨敦钧
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AUO Corp
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AU Optronics Corp
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Abstract

The invention provides a transflective liquid crystal display panel and a manufacturing method thereof, the display panel comprises a substrate, a first polysilicon pattern arranged in a reflection area of a pixel, a second polysilicon pattern arranged in a peripheral area of the pixel, an insulating layer arranged on the first polysilicon pattern, the second polysilicon pattern and the substrate, a grid arranged on the insulating layer of the reflection area of the pixel, a common electrode arranged on the insulating layer of the peripheral area of the pixel, a first interlayer dielectric layer arranged on the insulating layer, the grid and a common electrode, a reflection electrode arranged on the first interlayer dielectric layer, a second interlayer dielectric layer arranged on the first interlayer dielectric layer and the reflection electrode, and a penetration electrode arranged on the second interlayer dielectric layer and electrically connected with the reflection electrode through an opening of the second interlayer dielectric layer. The second polysilicon pattern, the common electrode and the insulating layer therebetween constitute a storage capacitor. The reflective electrode is arranged above the thin film transistor, so that the area of the reflective region can be increased. The storage capacitor is arranged below the data line, so that the aperture opening ratio can be improved.

Description

Semi-penetrating and semi-reflective liquid crystal display panel and preparation method thereof
Technical field
The invention relates to a kind of semi-penetrating and semi-reflective liquid crystal display panel and preparation method thereof, refer to a kind of high aperture and the simple semi-penetrating and semi-reflective liquid crystal display panel of technology and preparation method thereof especially.
Background technology
LCD is according to the source difference of illumination light, can divide into penetration, reflective, and three kinds of semi-penetration, semi-reflectives etc.Penetrating LCD needs in the back side of display panels the backlight module that is used for producing light to be set, and the light of its generation can allow the observer see that by anterior view the picture of LCD shows by display panels.Reflective liquid-crystal display is to use surround lighting as light source, and needs to be provided with in pixel region reflecting electrode; When reflective liquid-crystal display display frame, surround lighting is entered in the display panels and by reflecting electrode by the front (sightingpiston) of display panels light is reflected, and the observer can watch the picture of LCD to show by this.As for semi-penetrated semi-reflected liquid crystal display then is the LCD that has the pattern of penetrating and reflective-mode simultaneously, that is each pixel region of display panels all includes penetrating region and echo area, wherein penetrating region is to use backlight, and the echo area then is to use surround lighting as light source.
Please refer to Fig. 1.Fig. 1 is the synoptic diagram of known semi-penetrating and semi-reflective liquid crystal display panel.As shown in Figure 1, known semi-penetrating and semi-reflective liquid crystal display panel comprises substrate 10, and definition has echo area 12 and penetrating region 14 on it.Be provided with thin film transistor (TFT) in the echo area 12, it has semiconductor layer, and semiconductor layer comprises passage 16, source electrode 18, drain electrode 20, two slight doped-drain 21, gate insulator 22 and grid 24, wherein source electrode 18 and drain electrode 20 are arranged at the both sides of passage 16 respectively, two slight doped-drain 21 be arranged at respectively between source electrode 18 and the passage 16 and drain electrode 20 and passage 16 between, gate insulator 22 is covered on passage 16, source electrode 18 and the drain electrode 20, and grid 24 is arranged on the gate insulator 22 and respective channel 16.
Be coated with first interlayer dielectric layer 26 on gate insulator 22 and the grid 24, and first interlayer dielectric layer 26 gate insulator 22 corresponding with its below have two openings, expose source electrode 18 respectively and drain 20.First interlayer dielectric layer 26 is provided with data line 28 and drain electrode connection gasket 30, and wherein data line 28 is inserted in the opening of source electrode 18 tops and electrically connected with source electrode 18 by this, and drain electrode connection gasket 30 is then inserted drain electrode 20 top openings and electrically connected with drain electrode 20 by this.In echo area 12, be coated with second interlayer dielectric layer 32 on first interlayer dielectric layer 26, data line 28 and the drain electrode connection gasket 30, and second interlayer dielectric layer 32 has opening, expose drain electrode connection gasket 30.Second interlayer dielectric layer 32 and first interlayer dielectric layer 26 are provided with through electrode 34, wherein through electrode 34 is overlapped on the drain electrode connection gasket 30 by the opening of second interlayer dielectric layer 32, electrically connect with drain electrode 20 by this, and through electrode 34 extends to penetrating region 14.In addition, on the through electrode 34 of echo area 12, be coated with a reflecting electrode 36, and electrically connect with drain electrode 20 by through electrode 34 and drain electrode connection gasket 30.
Yet known semi-penetrating and semi-reflective liquid crystal display panel has following shortcoming.At first, known semi-penetrating and semi-reflective liquid crystal display panel must utilize at least eight road lithography process, define the pattern of semiconductor layer, source/drain, slight doped-drain, grid, first interlayer dielectric layer, data line and drain electrode connection gasket, second interlayer dielectric layer, through electrode and reflecting electrode respectively, so technology is comparatively complicated.In addition, because the echo area is provided with second interlayer dielectric layer, and penetrating region is not provided with second interlayer dielectric layer, make echo area and penetrating region have difference in height, and this difference in height easily causes the rub degree of difficulty of (rubbing) alignment pattern of follow-up brush, and in follow-up liquid crystal process, also can cause the degree of difficulty that liquid crystal gap (Cell Gap) is highly controlled and gap (spacer) is arranged.
Summary of the invention
One of purpose of the present invention is to propose a kind of semi-penetrating and semi-reflective liquid crystal display panel and preparation method thereof, to simplify the technology and the structure thereof of semi-penetrating and semi-reflective liquid crystal display panel.
For reaching above-mentioned purpose, the present invention proposes a kind of semi-penetrating and semi-reflective liquid crystal display panel, comprising: substrate, polysilicon layer, insulation course, ground floor metal, first interlayer dielectric layer, second layer metal, second interlayer dielectric layer, and through electrode.Substrate comprises echo area, penetrating region and surrounding zone.Polysilicon layer is arranged on the substrate, and polysilicon layer comprises that first poly-silicon pattern is arranged at the echo area, and second poly-silicon pattern is arranged at the surrounding zone, and wherein first poly-silicon pattern comprises passage, and source electrode and drain electrode are positioned at the both sides of passage.Insulation course is arranged on polysilicon layer and the substrate.The ground floor metal is arranged on the insulation course, and the ground floor metal comprises the grid respective channel, and common electrode is to should second poly-silicon pattern, and wherein second poly-silicon pattern, common electrode and insulation course therebetween constitute storage capacitors.First interlayer dielectric layer is arranged on insulation course and the ground floor metal, and first interlayer dielectric layer has two openings, exposes source electrode and drain electrode respectively.Second layer metal is arranged on first interlayer dielectric layer, second layer metal comprises reflecting electrode and data line, wherein reflecting electrode is arranged at the echo area and sees through the corresponding opening that drains of first interlayer dielectric layer and electrically connects with drain electrode, data line is arranged at the surrounding zone and extends to the echo area, and data line sees through the opening and the source electrode electric connection of the corresponding source electrode of first interlayer dielectric layer in the echo area.Second interlayer dielectric layer is arranged on first interlayer dielectric layer and the second layer metal, and second interlayer dielectric layer has an opening and exposes the part second layer metal.Through electrode is arranged on second interlayer dielectric layer, and through electrode is arranged at penetrating region and extends to the echo area and the intersection of penetrating region, and through electrode sees through opening and the reflecting electrode and the drain electrode electric connection of second interlayer dielectric layer.
For reaching above-mentioned purpose, the present invention provides a kind of method of making semi-penetrating and semi-reflective liquid crystal display panel in addition, comprising: substrate is provided, and on substrate, define the echo area, penetrating region and surrounding zone; On substrate, form polysilicon layer, and utilize the first road lithography process to form first poly-silicon pattern in the echo area, and form second poly-silicon pattern in the surrounding zone; Utilize the second road lithography process in first poly-silicon pattern, to form passage, and form source electrode and drain electrode, and on first poly-silicon pattern, second poly-silicon pattern and substrate, form insulation course in the both sides of passage; On insulation course, form the ground floor metal, and utilize the 3rd road lithography process to form the grid respective channel in the echo area, and in corresponding second poly-silicon pattern of surrounding zone formation common electrode, wherein passage, source electrode, drain electrode, insulation course and grid constitute a thin film transistor (TFT), and second poly-silicon pattern, common electrode and insulation course therebetween constitute storage capacitors; On insulation course and ground floor metal, form first interlayer dielectric layer, and utilize the 4th road lithography process in first interlayer dielectric layer, to form two openings, expose source electrode and drain electrode respectively; On first interlayer dielectric layer, form second layer metal, and utilize the 5th road lithography process to form reflecting electrode in the echo area, and in surrounding zone formation data line, and make data line partly extend to the echo area, wherein this reflecting electrode sees through the opening of the corresponding drain electrode of first interlayer dielectric layer and drains and electrically connects, and data line sees through the opening and the source electrode electric connection of the corresponding source electrode of first interlayer dielectric layer in the echo area; On first interlayer dielectric layer and second layer metal, form second interlayer dielectric layer, and utilize the 6th road lithography process in this second interlayer dielectric layer, to form an opening, expose the part second layer metal; And on second interlayer dielectric layer, form transparency conducting layer, and utilize the 7th road lithography process to form through electrode, through electrode is arranged at penetrating region and extends to the echo area and the intersection of penetrating region, and through electrode sees through opening and the reflecting electrode and the drain electrode electric connection of second interlayer dielectric layer.
Because method of the present invention only need be utilized seven road lithography process, can produce semi-penetrating and semi-reflective liquid crystal display panel, therefore can simplify technology.In addition, reflecting electrode of the present invention is arranged at the top of thin film transistor (TFT), therefore can increase the area of echo area.Moreover storage capacitors is arranged at the below of data line, therefore can promote aperture opening ratio.
Description of drawings
Fig. 1 is the synoptic diagram of known semi-penetrating and semi-reflective liquid crystal display panel.
Fig. 2 to Figure 17 is the method synoptic diagram of a preferred embodiment of making semi-penetrating and semi-reflective liquid crystal display panel of the present invention.
Figure 18 and Figure 19 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of another preferred embodiment of the present invention.
Figure 20 and Figure 21 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of the another preferred embodiment of the present invention.
Figure 22 is the synoptic diagram of periphery circuit region of the present invention.
Drawing reference numeral:
10 substrates, 12 echo areas
14 penetrating regions, 16 passages
20 drain electrodes of 18 source electrodes
21 slight doped-drain 22 gate insulators
24 grids, 26 first interlayer dielectric layers
28 data lines, 30 drain electrode connection gaskets
32 second interlayer dielectric layers, 34 through electrodes
36 reflecting electrodes, 50 substrates
51 cushions, 52 echo areas
54 penetrating regions, 56 surrounding zones
58 first poly-silicon patterns, 60 second poly-silicon patterns
62 passages, 63 slight doped-drain
66 drain electrodes of 64 source electrodes
68 insulation courses, 70 sweep traces
72 grids, 74 common electrodes
76 first interlayer dielectric layer 76A inorganic dielectric layer
The organic dielectric layer 76C of 76B sensitization contoured surface
76D opening 77 intermediate tone masks
78 reflecting electrode 78A reflecting electrode contoured surface
80 data lines, 82 second interlayer dielectric layers
82A opening 84 through electrodes
84A slit 86 transparent conductive patterns
86A slit 90 CMOS transistors
92 nmos pass transistors, 94 PMOS transistors
Embodiment
For making those skilled in the art can further understand the present invention, hereinafter the spy enumerates several preferred embodiments of the present invention, and cooperate appended graphic, describe in detail constitution content of the present invention and the effect desiring to reach.
Please refer to Fig. 2 to Figure 17.Fig. 2 to Figure 17 is the method synoptic diagram of a preferred embodiment of making semi-penetrating and semi-reflective liquid crystal display panel of the present invention.For ease of explanation, only show a pixel region in graphic, and Fig. 2, Fig. 4, Fig. 6, Fig. 8, Figure 10, Figure 12, Figure 14 and Figure 16 are the top view of pixel region, and Fig. 3, Fig. 5, Fig. 7, Fig. 9, Figure 11, Figure 13, Figure 15 and Figure 17 are the diagrammatic cross-section of pixel region along hatching line AA ' and BB '.As Fig. 2 and shown in Figure 3, substrate 50 at first is provided, and on substrate 50, define echo area 52, penetrating region 54 and surrounding zone 56.Then optionally on substrate 50, form a cushion 51 (Fig. 2 does not show) earlier.Subsequently, on substrate 50, form polysilicon layer again, low-temperature polycrystalline silicon layer for example, and utilize the first road lithography process to cooperate etching technics 52 to form first poly-silicon pattern 58 in the echo area, and 56 form second poly-silicon pattern 60 in the surrounding zone, wherein first poly-silicon pattern 58 is used to make the semiconductor layer of thin film transistor (TFT), and second poly-silicon pattern 60 is as the bottom electrode of storage capacitors, and first poly-silicon pattern 58 and second poly-silicon pattern 60 are electric connection in present embodiment, but are not limited thereto.
As Fig. 4 and shown in Figure 5, utilize the second road lithography process to cooperate high concentration ion cloth to plant technology subsequently and carry out implanting ions in first poly-silicon pattern 58 and second poly-silicon pattern 60, wherein the mask pattern that part first poly-silicon pattern 58 forms by photoresistance in the second road lithography process (figure does not show) is stopped that formation is not mixed, the not doped region of first poly-silicon pattern 58 forms passage 62 by this, the doped region of passage 62 both sides then forms source electrode 64 and drain electrode 66, and second poly-silicon pattern 60 also can because of doping tool electric conductivity with bottom electrode as storage capacitors.The thin film transistor (TFT) of present embodiment can be N type or P type, so high concentration ion cloth is planted the admixture that uses and can optionally be P type or N type.Thin film transistor (TFT) that what deserves to be explained is present embodiment in addition designs for bigrid, so the layout of passage 62 is as shown in Figure 4, however application of the present invention be not limited thereto, and also can be the design of general single grid.
As Fig. 6 and shown in Figure 7, on first poly-silicon pattern 58, second poly-silicon pattern 60 and substrate 50, form insulation course 68 (Fig. 6 does not show) subsequently, wherein the insulation course 68 in passage 62 tops is the usefulness as gate insulator.In first poly-silicon pattern 58, form passage 62, and the step that forms source electrode 64 and drain electrode 66 in the both sides of passage 62, be not limited to prior to carrying out before the step that on first poly-silicon pattern 58, second poly-silicon pattern 60 and substrate 50, forms insulation course 68.In other words, also can on first poly-silicon pattern 58, second poly-silicon pattern 60 and substrate 50, after the formation insulation course 68, in first poly-silicon pattern 58, form passage 62 again, and form source electrode 64 and drain 66 earlier in the both sides of passage 62.Then on insulation course 68, form the ground floor metal again, and 52 formation sweep traces 70, grid 72 electrically connect and respective channel 62 with sweep trace 70 in the echo area to utilize one the 3rd road lithography process to cooperate etching technics, and 56 form common electrodes 74 corresponding second poly-silicon patterns 60 in the surrounding zone, wherein common electrode 74 also is the top electrode of storage capacitors, so second poly-silicon pattern 60, the common electrode 74 of surrounding zone 56 and be positioned at second poly-silicon pattern 60 and the insulation course of 74 of common electrodes 68 constitutes storage capacitors.
As Fig. 8 and shown in Figure 9, then carry out low concentration implanting ions technology, to form slight doped-drain 63.In the present embodiment, because the undersized of grid 72 in passage 62, therefore can directly be utilized grid 72 to form slight doped-drain 63 as shade by being doped in passage 62 both sides, and needn't use extra mask.
As Figure 10 and shown in Figure 11, then on insulation course 68 and ground floor metal, form first interlayer dielectric layer 76 (Figure 10 does not show), and in the echo area 52 first interlayer dielectric layer 76 forms contoured surface, in first interlayer dielectric layer 76 and following pairing insulation course 68 thereof, form two openings again, expose source electrode 64 and drain electrode 66 respectively.In present embodiment, first interlayer dielectric layer 76 includes for example silicon nitride of inorganic dielectric layer 76A, and the organic dielectric layer 76B of sensitization with sensitometric characteristic.In addition, in the present embodiment, the contoured surface 76C of first interlayer dielectric layer 76 and opening 76D use shadow tone (halftone) mask 77 by the 4th road lithography process and cooperate etching technics to form, its practice is as described below: at first carry out the 4th road lithography process, utilize intermediate tone mask 77 control exposures, make the zone of the organic dielectric layer 76B of the corresponding sensitization of semi-opaque region 77A of intermediate tone mask at desire formation contoured surface 76C, and the corresponding desire of the full photic zone 77B that makes intermediate tone mask forms the zone of opening 76D, thus because the regional exposure amount of desire formation contoured surface 76C is less, therefore behind exposure imaging, only can cause the effect of contoured surface 76C in the surface of the organic dielectric layer 76B of sensitization formation micro pattern, and on the other hand since desire she to form the exposure in zone of opening 76D bigger, the organic dielectric layer 76B of sensitization that therefore should the zone can all be removed behind exposure imaging and form opening 76D.Then carry out etching technics again, by opening 76D etching inorganic dielectric layer 76A and insulation course 68, until exposing source electrode 64 and drain electrode 66.
Present embodiment system utilizes intermediate tone mask to form the rough surperficial 76C of fluctuating and the opening 76D of first interlayer dielectric layer 76, is not limited to this and can utilizes alternate manner to reach yet the present invention makes the mode of contoured surface 76C and opening 76D.For instance, form contoured surface 76C and can utilize different masks to be formed respectively with the step of opening 76D, perhaps contoured surface 76C can utilize laser technology to be formed, and uses the exposure imaging mode to form and be not limited thereto.
As Figure 12 and shown in Figure 13, then on first interlayer dielectric layer 76, form a second layer metal (figure does not show), and utilize the 5th road lithography process to cooperate etching technics in echo area 52, to form reflecting electrode 78, and in surrounding zone 56, form data line 80, and make data line 80 parts extend to echo area 52, wherein reflecting electrode 78 is through the opening and drain electrode 66 electric connections of the 76 corresponding drain electrodes 66 of first interlayer dielectric layer, and 52 opening and the source electrodes 64 that then see through first interlayer dielectric layer, 76 corresponding source electrodes 64 electrically connect data line 80 in the echo area.In addition, because first interlayer dielectric layer 76 has contoured surface 76C in echo area 52, therefore the reflecting electrode 78 that therefore stacks thereon also has contoured surface 78A, and can allow reflection ray assemble, and reaches the effect that improves reflectivity.
As Figure 14 and shown in Figure 15, on first interlayer dielectric layer 76 and second layer metal, form second interlayer dielectric layer 82 subsequently, and utilize the 6th road lithography process to cooperate etching technics in second interlayer dielectric layer 82, to form an opening 82A, expose part second layer metal (edge of reflecting electrode 78).As Figure 16 and shown in Figure 17, on second interlayer dielectric layer 82, form a transparency conducting layer (figure does not show) at last, and utilize one the 7th road lithography process to cooperate etching technics to form through electrode 84, wherein through electrode 84 is arranged in the penetrating region 54 and extends to the intersection of echo area 52 and penetrating region 54, and through electrode 84 can see through opening and the reflecting electrode 78 of second interlayer dielectric layer 82 and 66 electric connections that drain by this.In addition, in present embodiment, through electrode 84 trims substantially with data line 80 and overlapping (as Figure 16 and shown in Figure 17), can avoid producing stray capacitance by this, but the present invention is not as limit, and through electrode 84 also can not overlap with data line 80 and not trim, or is different relative positions.
Above-mentioned for the present invention makes the preferred embodiment of the method and the structure thereof of semi-penetrating and semi-reflective liquid crystal display panel, however semi-penetrating and semi-reflective liquid crystal display panel of the present invention is not limited to this, and other different enforcement sample attitude can be arranged.Please refer to Figure 18 to Figure 21.Figure 18 and Figure 19 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of another preferred embodiment of the present invention, and Figure 20 and Figure 21 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of the another preferred embodiment of the present invention, wherein for ease of comparing the similarities and differences of each embodiment, in various embodiments of the present invention, similar elements is used same numeral, and no longer adds to give unnecessary details.
As Figure 18 and shown in Figure 19, different with previous embodiment be in, the semi-penetrating and semi-reflective liquid crystal display panel of present embodiment has the transparent conductive patterns 86 of float (floating) in addition, be positioned at the surface of second interlayer dielectric layer 82 of echo area 52, wherein transparent conductive patterns 86 is same transparency conducting layer with through electrode 84, and need not increase additional technique by the definition of the 7th road lithography process, but transparent conductive patterns 86 does not electrically connect with through electrode 84, and the effect of transparent conductive patterns 86 is to make echo area 52 consistent with the character of surface of penetrating region 54, for example highly consistent, to reduce the rub degree of difficulty of alignment pattern of follow-up brush.
As Figure 20 and shown in Figure 21, different with previous embodiment be in, the through electrode 84 of the semi-penetrating and semi-reflective liquid crystal display panel of present embodiment has many slit 84A, and transparent conductive patterns 86 also optionally has many slit 86A.The slit 84A of through electrode 84 and the slit 86A of transparent conductive patterns 86 all can define in the 7th road lithography process in the lump, need not increase additional technique, and the slit 86A of the slit 84A of through electrode 84 and transparent conductive patterns 86 can make liquid crystal molecule towards the different directions orientation, and is applied in the liquid crystal display panel with wide visual angle.
Please refer to Figure 22.Figure 22 is the synoptic diagram of periphery circuit region of the present invention.As shown in figure 22, the making of the control element of the periphery circuit region of present embodiment can with the process integration of the thin film transistor (TFT) of pixel region, and control element is that the CMOS transistor 90 that a nmos pass transistor 92 and PMOS transistor 94 are formed constitutes in present embodiment, yet application of the present invention is not limited to this, the also visual circuit design of control element and be single nmos pass transistor or single PMOS transistor.
In sum, method of the present invention only need use seven road lithography process can produce semi-penetrating and semi-reflective liquid crystal display panel, and is the design of single liquid crystal gap (single cell gap), therefore has the advantage of work simplification.In addition, first interlayer dielectric layer of the present invention comprises inorganic dielectric layer and organic dielectric layer, can reduce the coupling of lead crossover region (ground floor metal and second layer metal), reduce stray capacitance, and the organic dielectric layer of sensitization can pass through exposure imaging mode define pattern, so can reduce the burden of deposition and etching technics.Therefore moreover reflecting electrode is arranged at the top of thin film transistor (TFT), only is arranged at the practice in the capacitive region compared to known reflecting electrode, can increase the area of echo area.In addition, storage capacitors is arranged at the below of data line, therefore can promote aperture opening ratio.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (19)

1.一种半穿透半反射式液晶显示面板,其特征在于,所述半穿透半反射式液晶显示面板包括:1. A transflective liquid crystal display panel, characterized in that, the transflective liquid crystal display panel comprises: 一基板,包括一反射区、一穿透区与一周边区;A substrate, including a reflection area, a penetration area and a peripheral area; 一多晶硅层,设置于所述基板上,所述多晶硅层包括一第一多晶硅图案设置于所述反射区,以及一第二多晶硅图案设置于所述周边区,其中所述第一多晶硅图案包括一通道,以及一源极与一漏极位于所述通道的两侧;A polysilicon layer disposed on the substrate, the polysilicon layer includes a first polysilicon pattern disposed on the reflective area, and a second polysilicon pattern disposed on the peripheral area, wherein the first The polysilicon pattern includes a channel, and a source and a drain are located on both sides of the channel; 一绝缘层,设置于所述多晶硅层与所述基板上;an insulating layer disposed on the polysilicon layer and the substrate; 一第一层金属,设置于所述绝缘层上,所述第一层金属包括一栅极对应所述通道,以及一共通电极对应所述第二多晶硅图案,其中所述第二多晶硅图案、所述共通电极及其间的所述绝缘层构成一储存电容,所述通道、所述源极、所述漏极、所述绝缘层与所述栅极构成一薄膜晶体管,栅极的尺寸略小于通道;A first layer of metal, disposed on the insulating layer, the first layer of metal includes a gate corresponding to the channel, and a common electrode corresponding to the second polysilicon pattern, wherein the second polysilicon pattern The silicon pattern, the common electrode and the insulating layer therebetween form a storage capacitor, the channel, the source, the drain, the insulating layer and the gate form a thin film transistor, and the gate Dimensions are slightly smaller than the channel; 一第一层间介电层,设置于所述绝缘层与所述第一层金属上,所述第一层间介电层具有两开口,分别曝露出所述源极与所述漏极,所述第一层间介电层包括一无机介电层与一感光有机介电层;a first interlayer dielectric layer disposed on the insulating layer and the first layer of metal, the first interlayer dielectric layer has two openings exposing the source and the drain respectively, The first interlayer dielectric layer includes an inorganic dielectric layer and a photosensitive organic dielectric layer; 一第二层金属,设置于所述第一层间介电层上,所述第二层金属包括一设置于所述薄膜晶体管上方的反射电极与一数据线,其中所述反射电极设置于所述反射区并透过所述第一层间介电层对应所述漏极的所述开口与所述漏极电性连接,所述数据线设置于所述周边区并延伸至所述反射区,且所述数据线于所述反射区透过所述第一层间介电层对应所述源极的所述开口与所述源极电性连接,所述储存电容设置于所述数据线的下方;A second layer of metal disposed on the first interlayer dielectric layer, the second layer of metal includes a reflective electrode and a data line disposed above the thin film transistor, wherein the reflective electrode is disposed on the The reflective region is electrically connected to the drain through the opening of the first interlayer dielectric layer corresponding to the drain, and the data line is arranged in the peripheral region and extends to the reflective region , and the data line is electrically connected to the source through the opening of the first interlayer dielectric layer corresponding to the source in the reflection area, and the storage capacitor is arranged on the data line below; 一第二层间介电层,设置于所述第一层间介电层与所述第二层金属上,所述第二层间介电层具有一开口曝露出部分所述第二层金属;以及A second interlayer dielectric layer disposed on the first interlayer dielectric layer and the second layer of metal, the second interlayer dielectric layer has an opening exposing part of the second layer of metal ;as well as 一穿透电极,设置于所述第二层间介电层上,所述穿透电极设置于所述穿透区并延伸至所述反射区与所述穿透区的交界处,且所述穿透电极透过所述第二层间介电层的所述开口与所述反射电极及所述漏极电性连接,所述穿透电极与所述数据线大体上切齐且未重叠。a penetrating electrode disposed on the second interlayer dielectric layer, the penetrating electrode is disposed in the penetrating area and extends to the junction of the reflecting area and the penetrating area, and the The penetrating electrode is electrically connected to the reflective electrode and the drain through the opening of the second interlayer dielectric layer, and the penetrating electrode is substantially aligned with the data line without overlapping. 2.如权利要求1所述的半穿透半反射式液晶显示面板,其特征在于,所述第二层间介电层为一感光有机介电层。2. The transflective liquid crystal display panel as claimed in claim 1, wherein the second interlayer dielectric layer is a photosensitive organic dielectric layer. 3.如权利要求1所述的半穿透半反射式液晶显示面板,其特征在于,所述第一层间介电层于所述反射区具有一起伏表面,藉此设置于所述第一层间介电层上的所述反射电极具有一起伏表面。3. The transflective liquid crystal display panel according to claim 1, wherein the first interlayer dielectric layer has an undulating surface in the reflective area, thereby being disposed on the first The reflective electrode on the interlayer dielectric layer has an undulating surface. 4.如权利要求1所述的半穿透半反射式液晶显示面板,其特征在于,穿透电极另包括一浮置的透明导电层,设置于所述反射区的所述第二层间介电层的表面。4. The transflective liquid crystal display panel according to claim 1, wherein the transmissive electrode further comprises a floating transparent conductive layer, which is disposed on the second interlayer interlayer of the reflective region. surface of the electrical layer. 5.如权利要求4所述的半穿透半反射式液晶显示面板,其特征在于,穿透电极所述透明导电层具有多条狭缝。5. The transflective liquid crystal display panel according to claim 4, wherein the transparent conductive layer of the penetrating electrode has a plurality of slits. 6.如权利要求1所述的半穿透半反射式液晶显示面板,其特征在于,所述穿透电极具有多条狭缝。6. The transflective liquid crystal display panel according to claim 1, wherein the transmissive electrode has a plurality of slits. 7.如权利要求1所述的半穿透半反射式液晶显示面板,其特征在于,所述基板与所述多晶硅层间设有一缓冲层。7. The transflective liquid crystal display panel as claimed in claim 1, wherein a buffer layer is disposed between the substrate and the polysilicon layer. 8.一种制作半穿透半反射式液晶显示面板的方法,其特征在于,所述方法包括:8. A method for making a transflective liquid crystal display panel, characterized in that the method comprises: 提供一基板,并于所述基板上定义出一反射区、一穿透区与一周边区;providing a substrate, and defining a reflection region, a penetration region and a peripheral region on the substrate; 于所述基板上形成一多晶硅层,并利用一第一道微影工艺于所述反射区形成一第一多晶硅图案,以及于所述周边区形成一第二多晶硅图案;forming a polysilicon layer on the substrate, and forming a first polysilicon pattern in the reflective area by a first lithography process, and forming a second polysilicon pattern in the peripheral area; 利用一第二道微影工艺于所述第一多晶硅图案中形成一通道,以及于所述通道的两侧形成一源极与一漏极;forming a channel in the first polysilicon pattern by a second lithography process, and forming a source and a drain on both sides of the channel; 于所述第一多晶硅图案、所述第二多晶硅图案与所述基板上形成一绝缘层;forming an insulating layer on the first polysilicon pattern, the second polysilicon pattern and the substrate; 于所述绝缘层上形成一第一层金属,并利用一第三道微影工艺于所述反射区形成一栅极对应所述通道,以及于所述周边区形成一共通电极对应所述第二多晶硅图案,其中所述通道、所述源极、所述漏极、所述绝缘层与所述栅极构成一薄膜晶体管,且所述第二多晶硅图案、所述共通电极及其间的所述绝缘层构成一储存电容,栅极的尺寸略小于通道;forming a first layer of metal on the insulating layer, and using a third lithography process to form a gate corresponding to the channel in the reflective area, and forming a common electrode corresponding to the first channel in the peripheral area Two polysilicon patterns, wherein the channel, the source, the drain, the insulating layer and the gate form a thin film transistor, and the second polysilicon pattern, the common electrode and The insulating layer therebetween constitutes a storage capacitor, and the size of the gate is slightly smaller than that of the channel; 于所述绝缘层与所述第一层金属上形成一第一层间介电层,并利用一第四道微影工艺于所述第一层间介电层中形成两开口,分别曝露出所述源极与所述漏极,形成所述第一层间介电层的步骤包括:形成一无机介电层,于所述无机介电层上形成一感光有机介电层介电层;A first interlayer dielectric layer is formed on the insulating layer and the first layer of metal, and a fourth lithography process is used to form two openings in the first interlayer dielectric layer, respectively exposing The step of forming the first interlayer dielectric layer for the source electrode and the drain electrode includes: forming an inorganic dielectric layer, and forming a photosensitive organic dielectric layer dielectric layer on the inorganic dielectric layer; 于所述第一层间介电层上形成一第二层金属,并利用一第五道微影工艺于所述反射区形成一反射电极,以及于所述周边区形成一数据线,并使所述数据线部分延伸至所述反射区,其中所述反射电极透过所述第一层间介电层对应所述漏极的所述开口与所述漏极电性连接,所述反射电极设置于所述薄膜晶体管的上方,而所述数据线于所述反射区透过所述第一层间介电层对应所述源极的所述开口与所述源极电性连接,所述储存电容设置于所述数据线的下方;forming a second layer of metal on the first interlayer dielectric layer, and using a fifth lithography process to form a reflective electrode in the reflective area, and form a data line in the peripheral area, and make The data line partially extends to the reflective region, wherein the reflective electrode is electrically connected to the drain through the opening of the first interlayer dielectric layer corresponding to the drain, and the reflective electrode disposed above the thin film transistor, and the data line is electrically connected to the source through the opening of the first interlayer dielectric layer corresponding to the source in the reflective area, the The storage capacitor is arranged under the data line; 于所述第一层间介电层与所述第二层金属上形成一第二层间介电层,并利用一第六道微影工艺于所述第二层间介电层中形成一开口,曝露出部分所述第二层金属;以及forming a second interlayer dielectric layer on the first interlayer dielectric layer and the second metal layer, and forming a second interlayer dielectric layer in the second interlayer dielectric layer by using a sixth lithography process an opening exposing a portion of said second layer of metal; and 于所述第二层间介电层上形成一透明导电层,并利用一第七道微影工艺形成一穿透电极,所述穿透电极设置于所述穿透区并延伸至所述反射区与所述穿透区的交界处,且所述穿透电极透过所述第二层间介电层的所述开口与所述反射电极及所述漏极电性连接,所述穿透电极与所述数据线大体上切齐且未重叠。forming a transparent conductive layer on the second interlayer dielectric layer, and using a seventh lithography process to form a penetrating electrode, the penetrating electrode is arranged in the penetrating region and extends to the reflective region and the penetration region, and the penetration electrode is electrically connected to the reflective electrode and the drain through the opening of the second interlayer dielectric layer, the penetration The electrodes are substantially aligned with and not overlapped with the data lines. 9.如权利要求8所述的方法,其特征在于,在利用所述第四道微影工艺于所述第一层间介电层中形成所述两开口的步骤中,包括利用一半色调掩膜一并使所述反射区的所述感光有机介电层形成一起伏表面。9. The method according to claim 8, wherein the step of forming the two openings in the first interlayer dielectric layer using the fourth lithography process comprises using a half-tone mask film together to form an undulating surface of the photosensitive organic dielectric layer of the reflective area. 10.如权利要求8所述的方法,其特征在于,所述方法另包括利用另一掩膜使所述反射区的所述感光有机介电层形成一起伏表面。10. The method as claimed in claim 8, further comprising using another mask to form an undulating surface on the photosensitive organic dielectric layer in the reflective area. 11.如权利要求8所述的方法,其特征在于,所述方法另包括利用一激光工艺使所述反射区的所述第一层间介电层形成一起伏表面。11. The method of claim 8, further comprising forming a relief surface on the first interlayer dielectric layer of the reflective region by using a laser process. 12.如权利要求8所述的方法,其特征在于,在形成所述穿透电极的步骤中,另包括于所述反射区内形成一浮置的透明导电图案。12 . The method according to claim 8 , further comprising forming a floating transparent conductive pattern in the reflective region during the step of forming the penetrating electrode. 13 . 13.如权利要求12所述的方法,其特征在于,在形成所述透明导电图案的步骤中,另包括于所述透明导电图案中形成多条狭缝。13. The method according to claim 12, further comprising forming a plurality of slits in the transparent conductive pattern in the step of forming the transparent conductive pattern. 14.如权利要求8所述的方法,其特征在于,在形成所述穿透电极的步骤中,另包括于所述穿透电极中形成多条狭缝。14. The method according to claim 8, further comprising forming a plurality of slits in the penetrating electrode during the step of forming the penetrating electrode. 15.如权利要求8所述的方法,其特征在于,所述方法另包括形成一缓冲层于所述基板与所述多晶硅层之间。15. The method of claim 8, further comprising forming a buffer layer between the substrate and the polysilicon layer. 16.如权利要求8所述的方法,其特征在于,利用所述第二道微影工艺于所述第一多晶硅图案中形成所述通道,以及于所述通道的两侧形成所述源极与所述漏极的步骤,是先于在所述第一多晶硅图案、所述第二多晶硅图案与所述基板上形成所述绝缘层的步骤。16. The method of claim 8, wherein the channel is formed in the first polysilicon pattern by the second lithography process, and the channels are formed on both sides of the channel. The steps of source and drain are prior to the step of forming the insulating layer on the first polysilicon pattern, the second polysilicon pattern and the substrate. 17.如权利要求8所述的方法,其特征在于,在所述第一多晶硅图案、所述第二多晶硅图案与所述基板上形成所述绝缘层的步骤,是先于利用所述第二道微影工艺于所述第一多晶硅图案中形成所述通道,以及于所述通道的两侧形成所述源极与所述漏极的步骤。17. The method according to claim 8, wherein the step of forming the insulating layer on the first polysilicon pattern, the second polysilicon pattern and the substrate is prior to using The second lithography process forms the channel in the first polysilicon pattern, and forms the source and the drain on both sides of the channel. 18.如权利要求8所述的方法,其特征在于,所述基板另包含一周边电路区,且所述方法另包含于制作所述薄膜晶体管的步骤中,于所述周边电路区内整合制作至少一控制元件。18. The method according to claim 8, wherein the substrate further includes a peripheral circuit area, and the method further includes in the step of manufacturing the thin film transistor, integrated manufacturing in the peripheral circuit area at least one control element. 19.如权利要求18所述的方法,其特征在于,所述控制元件包括一NMOS晶体管、一PMOS晶体管或一CMOS晶体管。19. The method of claim 18, wherein the control element comprises an NMOS transistor, a PMOS transistor or a CMOS transistor.
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