CN101109882A - Pixel structure and manufacturing method thereof - Google Patents

Abstract

The utility model discloses a dot structure and the manufacturing method thereof. Firstly, the first graphic conductor layer is formed on the base plate and comprises a grid and a data line, and then a grid isolation layer is formed on the base plate, so as to cover the first graphic conductor layer. Also, a semiconductor channel layer is formed on the grid isolation layer above the grid. Afterwards, the second graphic conductor layer is formed on the grid isolation layer and the semiconductor channel layer. Such second graphic conductor layer comprises a scan line, a common electrode wire, a source electrode and a drain electrode. The scan line is electrically connected with the grid; the common electrode wire is arranged above the data line, while the source electrode and the drain electrode are situated on the semiconductor channel layer. In addition, the source electrode is electrically connected with the data line. At the same time, the protective layer is formed on the base plate to cover the second graphic conductor layer, and then the pixel element electrode is formed on the protective layer. Meanwhile, the electrical connection is made between the pixel element electrode and the drain electrode.

Description

Pixel structure and manufacturing method thereof

technical field

The present invention relates to a pixel structure and a manufacturing method thereof, and in particular to a pixel structure with a high aperture ratio and a manufacturing method thereof.

Background technique

In the life of the 3C era, there are many kinds of information devices on the market, such as mobile phones, digital cameras, digital video cameras, notebook computers, desktop computers and other digital tools, all of which are developing in a more convenient, multi-functional and beautiful direction. . In most of the information devices, the flat-panel display is used as the main communication interface, and the display function of the flat-panel display makes it more convenient for users to operate the product. Among them, liquid crystal display has become the mainstream of the market due to its superior characteristics such as power saving, high image quality, good space utilization efficiency, low power consumption, and no radiation.

Generally speaking, the pixel structure of a liquid crystal display includes scan lines, data lines, active elements and pixel electrodes. In the pixel structure, the stray capacitance (Capacitance between pixel and data line, C _pd ) between the data line and the pixel electrode is one of the factors affecting the aperture ratio. In detail, when the distance between the data line and the pixel electrode is shortened, the stray capacitance (C _pd ) between the data line and the pixel electrode will increase accordingly. In order to avoid the stray capacitance (C pd ) between the data line and the pixel electrode _pd ) caused by the crosstalk effect (cross talk), designers usually keep a certain distance between the data line and the pixel electrode to reduce the vertical crosstalk effect (vertical cross talk), however, the distance between the data line and the pixel electrode The farther it is, the more the pixel aperture ratio will drop.

In order to reduce the crosstalk effect of the above-mentioned pixel structure and maintain the aperture ratio of the pixel structure at a certain level, many pixel structures have been proposed successively. For example, a thicker insulating layer can be disposed between the pixel electrode and the data line to reduce the effect of stray capacitance. However, the common insulating layer material is organic material, such as acrylic resin, which not only has the disadvantage of easily absorbing moisture and causing poor adhesion, but also has the disadvantage of making the pixel structure integral due to the fact that the material itself cannot be completely bleached during the process. The disadvantage of decreased penetration.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for manufacturing a pixel structure to reduce the crosstalk effect generated when the pixel electrode is too close to the data line.

The present invention further provides a pixel structure with a higher aperture ratio.

The invention provides a method for manufacturing a pixel structure. First, a first patterned conductor layer is formed on the substrate, which includes gates and data lines. Next, a gate insulating layer is formed on the substrate to cover the first patterned conductor layer, and a semiconductor channel layer is formed on the gate insulating layer above the gate. Then, a second patterned conductor layer is formed on the gate insulating layer and the semiconductor channel layer, which includes scanning lines, common electrode lines, source electrodes and drain electrodes. The scanning line is electrically connected to the gate, the common electrode line is located above the data line, and the source and drain are located on the semiconductor channel layer, and the source is electrically connected to the data line. Subsequently, a protection layer is formed on the substrate to cover the second patterned conductor layer, and then a pixel electrode is formed on the protection layer, and the pixel electrode is electrically connected to the drain.

In an embodiment of the present invention, the above-mentioned pixel electrodes partially overlap with the common electrode lines to form a storage capacitor.

In an embodiment of the present invention, the above-mentioned method for forming a semiconductor channel layer includes the following steps. First, a semiconductor material layer is formed on the gate insulating layer, and a deposition or doping process is performed to form an ohmic contact layer on the upper surface of the semiconductor material layer. Then, the semiconductor material layer is patterned to form a semiconductor channel layer.

In an embodiment of the present invention, the above-mentioned method for forming a gate insulating layer is, for example, firstly forming a first dielectric layer on the substrate, and then forming a first contact window and a second contact window in the first dielectric layer , so as to expose parts of the gate and data lines respectively.

In an embodiment of the present invention, the aforementioned scan line is electrically connected to the gate through the first contact window.

In an embodiment of the present invention, the above-mentioned source is electrically connected to the data line through the second contact window.

In an embodiment of the present invention, the above-mentioned method for forming a protective layer includes forming a second dielectric layer on the substrate to cover the second patterned conductor layer, and then forming a third contact window in the second dielectric layer , to expose part of the drain area.

In an embodiment of the present invention, the aforementioned pixel electrode is electrically connected to the drain through the third contact window.

In an embodiment of the present invention, the above-mentioned manufacturing method of the pixel structure further includes forming a connection layer on one side of the gate when forming the first patterned conductor layer. In addition, after forming the semiconductor channel layer and before forming the second patterned conductor layer, a fourth contact window can be formed in the gate insulating layer to expose part of the connection layer, so that after the second patterned conductor layer is formed , the drain is electrically connected to the connection layer through the fourth contact window.

In an embodiment of the present invention, the above-mentioned method for manufacturing the pixel structure further includes forming a fifth contact window in the protective layer and the gate insulating layer after forming the protective layer and before forming the pixel electrode, so as to expose a portion After forming the connection layer and forming the pixel electrode, the pixel electrode is electrically connected to the connection layer through the fifth contact window.

According to the manufacturing method of the pixel structure in the above-mentioned embodiments, the present invention further provides a pixel structure suitable for being disposed on a substrate. The pixel structure includes a first patterned conductor layer, a gate insulating layer, a semiconductor channel layer, a second patterned conductor layer, a protection layer and a pixel electrode. The first patterned conductor layer includes gates and data lines, and the gate insulation layer covers the first patterned conductor layer. The semiconductor channel layer is arranged on the gate insulation layer above the gate, and the second patterned conductor layer is arranged on the gate insulation layer and the semiconductor channel layer. The second patterned conductor layer includes a scan line, a common electrode line, and a source and a drain, wherein the scan line is electrically connected to the gate, the common electrode line is located above the data line, and the source and drain are located on the semiconductor channel layer, And the source is electrically connected to the data line. In addition, the protection layer covers the second patterned conductor layer, and the pixel electrode is disposed on the protection layer, and the pixel electrode is electrically connected to the drain.

In an embodiment of the present invention, the upper surface of the semiconductor channel layer further includes an ohmic contact layer.

In an embodiment of the present invention, the above-mentioned gate insulation layer has a first contact window and a second contact window, which are respectively located above the gate electrode and the data line. Meanwhile, the scan line is electrically connected to the gate through the first contact window, and the source is electrically connected to the data line through the second contact window.

In an embodiment of the present invention, the protection layer has a third contact window located above the drain, and the pixel electrode is electrically connected to the drain through the third contact window.

In an embodiment of the present invention, the above-mentioned first patterned conductor layer further includes a connection layer located under the drain electrode and the pixel electrode. In addition, the gate insulating layer has, for example, a fourth contact window, so that the drain is electrically connected to the connection layer through the fourth contact window. In addition, the protection layer and the gate insulation layer have, for example, a fifth contact window, so that the pixel electrode is electrically connected to the connection layer through the fifth contact window.

The present invention further proposes a pixel structure suitable for being configured on a substrate. The pixel structure includes a first patterned conductor layer, a gate insulating layer, a semiconductor channel layer, a second patterned conductor layer, a protection layer and a pixel electrode. The first patterned conductor layer is disposed on the substrate, and the first patterned conductor layer at least includes a gate and a connection layer. The gate insulation layer covers the first patterned conductor layer. The semiconductor channel layer is configured on the gate insulating layer above the gate. The second patterned conductor layer is disposed on the gate insulation layer and the semiconductor channel layer, and the second patterned conductor layer at least includes a source electrode and a drain electrode. The first patterned conductor layer, the semiconductor channel layer and the second patterned conductor layer together constitute a thin film transistor and data lines and scan lines electrically connected to the thin film transistor. The protection layer covers the second patterned conductor layer. The pixel electrode is disposed on the protective layer, and the pixel electrode is electrically connected to the drain through the connection layer.

In an embodiment of the present invention, the above-mentioned data line includes a first line segment and a second line segment, and the first line segment is formed by part of the first patterned conductor layer, and the second line segment is formed by the second patterned conductor layer The layer is formed and electrically connected with the first line segment.

The invention also provides a liquid crystal display panel, which includes a first substrate, a second substrate and a liquid crystal layer. The first substrate includes the pixel structure described in any one of the above embodiments, and the second substrate is disposed opposite to the first substrate. Meanwhile, the liquid crystal layer is disposed between the first substrate and the second substrate.

In the pixel structure and its manufacturing method of the present invention, the common electrode line is arranged between the pixel electrode and the data line, which helps to reduce the effect of stray capacitance and increase the aperture ratio of the pixel structure. In addition, in the present invention, while forming the first patterned conductor layer, a connection layer is formed so that the pixel electrode and the drain are electrically connected through the connection layer. In this way, there will be no disconnection between the pixel electrode and the drain electrode, and when the pixel structure of the present invention is applied to a liquid crystal display, the common electrode line above the connection layer also helps to assist the liquid crystal molecules in the direction of tilting.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

1A to 1F are schematic top views of a method for manufacturing a pixel structure according to an embodiment of the present invention;

Fig. 2A to Fig. 2F are respectively the cross-sectional views taken along section line AA', section line BB' and section line CC' in Fig. 1A to Fig. 1F;

FIG. 3A is a schematic top view of a pixel structure according to another embodiment of the present invention;

Fig. 3B is a sectional view taken along the section line D-D' of Fig. 3A;

FIG. 4 is a schematic top view of a pixel structure according to another embodiment of the present invention;

FIG. 5 is a liquid crystal display panel according to an embodiment of the present invention.

Among them, reference signs:

100: substrate 110: first patterned conductor layer

112: grid 114, 414: data line

116: Connection layer 120: Gate insulating layer

120a: first dielectric layer 122: first contact window

124: Second contact window 126: Fourth contact window

130: Semiconductor channel layer 132: Ohmic contact layer

132a: patterned doped semiconductor material layer 140: second patterned conductor layer

142, 418: Scanning line 144: Common electrode line

146: Source 148, 446: Drain

150: protective layer 152: third contact window

154: Fifth contact window 160: Pixel electrode

170, 300, 400, 540: pixel structure 180: thin film transistor

414A: The first line segment 414B: The second line segment

416: sixth contact window 500: liquid crystal display panel

510: First substrate 520: Second substrate

530: liquid crystal layer Cst: storage capacitor

Detailed ways

1A to 1F are schematic top views of a method for manufacturing a pixel structure according to an embodiment of the present invention, and FIG. 2A to FIG. The cross-sectional view indicated by line CC'. The manufacturing method of the pixel structure in this embodiment includes the following steps. First, referring to FIG. 1A and FIG. 2A , a first patterned conductor layer 110 is formed on a substrate 100 , wherein the first patterned conductor layer 110 includes a gate 112 and a data line 114 . The way of forming the first patterned conductor layer 110 includes forming a first conductor layer (not shown) on the substrate 100 and patterning the first conductor layer (not shown).

In this embodiment, the substrate 100 is, for example, a light-transmitting substrate such as a glass substrate or a plastic substrate, and the material of the first conductor layer can be any material used in the fabrication of the grid 112 and the fabrication of the data lines 114 in the technical field of the present invention. one or more materials. For example, the material of the first patterned conductor layer 110 is, for example, aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), gold (Au), or an alloy composed of these metals. Layer metal layer or composite metal layer.

1B and FIG. 2B , a first dielectric layer 120 a is formed on the substrate 100 to cover the first patterned conductor layer 110 , and a semiconductor channel layer 130 is formed on the first dielectric layer 120 a above the gate 112 . In this embodiment, the method of forming the first dielectric layer 120a is, for example, chemical vapor deposition. For example, the material of the first dielectric layer 120a is a dielectric material such as silicon dioxide, silicon nitride or silicon oxynitride.

In addition, the method of forming the semiconductor channel layer 130 includes the following steps. First, a semiconductor material layer (not shown) such as amorphous silicon is formed on the gate insulating layer 120, and a doping process is performed to form a doped semiconductor material layer (not shown) on the upper surface of the semiconductor material layer (not shown). shown), such as N-type doped semiconductor layer (N+doped semiconductor layer). Then, the semiconductor material layer (not shown) is patterned to form the semiconductor channel layer 130 above the gate 112 and the patterned doped semiconductor material layer 132 a on the upper surface thereof.

Referring to FIG. 1C and FIG. 2C , a first contact window 122 and a second contact window 124 are formed in the first dielectric layer 120 a to form a gate insulating layer 120 . It can be seen from FIG. 1C and FIG. 2C that the first contact window 122 exposes a part of the gate 112 , and the second contact 124 exposes a part of the data line 114 . In the present embodiment, the first contact window 122 and the second contact window 124 in the first dielectric layer 120 a are formed by, for example, a photolithographic etching process.

Then, referring to FIG. 1D and FIG. 2D , a second patterned conductor layer 140 is formed on the gate insulating layer 120 , the semiconductor channel layer 130 and the patterned doped semiconductor material layer 132 a. Specifically, the way of forming the second patterned conductor layer 140 is, for example, to form a second conductor layer (not shown) on the gate insulating layer 120 and the semiconductor channel layer 130, and place the second conductor layer (not shown) patterning to form the second patterned conductor layer 140 . It should be noted that, while the second conductor layer (not shown) is being patterned, part of the patterned doped semiconductor material layer 132a will be removed together. In detail, after the second conductor layer (not shown) is patterned, the scan lines 142 , the common electrode lines 144 , the source electrodes 146 and the drain electrodes 148 are formed without being covered by the source electrodes 146 and the drain electrodes 148 The remaining patterned doped semiconductor material layer 132a is removed to form the ohmic contact layer 132 until a portion of the semiconductor channel layer 130 is exposed.

It can be seen from FIGS. 1D and 2D that the scan line 142 is electrically connected to the gate 112 through the first contact window 122 , and the common electrode line 144 is located above the data line 114 . In addition, the source electrode 146 is electrically connected to the data line 114 through the second contact window 124 .

Then, referring to FIG. 1E and FIG. 2E , a protection layer 150 is formed on the gate insulating layer 120 to cover the second patterned conductor layer 140 . The method for forming the protective layer 150 includes forming a second dielectric layer (not shown) covering the gate insulating layer 120 and the second patterned conductor layer 140 on the substrate 100 first, and then forming a second dielectric layer (not shown) on the second dielectric layer (not shown). As shown), a third contact window 152 is formed to expose a part of the drain 148 . In this embodiment, the material of the protective layer 150 includes silicon oxide, silicon nitride or silicon oxynitride.

Subsequently, referring to FIG. 1F and FIG. 2F , a pixel electrode 160 is formed on the protection layer 150 , so that the pixel electrode 160 is electrically connected to the drain electrode 148 through the third contact window 152 . The pixel electrode 160 may be formed by forming a transparent conductive layer (not shown) of indium tin oxide, indium zinc oxide or other materials on the protective layer 150, and patterning the transparent conductive layer (not shown) to A pixel electrode 150 is formed. In addition, for example, the common electrode line 144 partially overlaps with the pixel electrode 160 to form a storage capacitor Cst.

It can be seen from FIG. 1F and FIG. 2F that the pixel structure 170 is configured on the substrate 100, which includes a first patterned conductor layer 110, a gate insulating layer 120, a semiconductor channel layer 130, a second patterned conductor layer 140, and a protective layer 150. and the pixel electrode 160 . Specifically, the gate insulation layer 120 covers the first patterned conductor layer 110 . The semiconductor channel layer 130 is disposed on the gate insulating layer 120 , and the second patterned conductive layer 140 is disposed on the gate insulating layer 120 and the semiconductor channel layer 130 . In addition, the passivation layer 150 covers the second patterned conductor layer 140 , and the pixel electrode 160 is disposed on the passivation layer 150 .

In detail, the first patterned conductor layer 110 includes a gate 112 and a data line 114 , and the second patterned conductor layer 140 includes a scan line 142 , a common electrode line 144 , and a source 146 and a drain 148 . Meanwhile, the semiconductor channel layer 130 is located above the gate 112 , the common electrode line 144 is located above the data line 114 , and the source electrode 146 and the drain electrode 148 are located on the semiconductor channel layer 130 . In addition, the gate insulating layer 120 has, for example, a first contact window 122 located above the gate 112 and a second contact window 124 located above the data line 114, and the scan line 142 is electrically connected to the gate 112 through the first contact window 122, The source electrode 146 is electrically connected to the data line 114 through the second contact window 124 . In addition, the passivation layer 150 has, for example, a third contact window 152 to electrically connect the drain electrode 148 to the pixel electrode 160 . In general, the first patterned conductor layer 110 , the semiconductor channel layer 130 and the second patterned conductor layer 140 together constitute a thin film transistor 180 and a data line 114 and a scan line 142 electrically connected to the thin film transistor 180 .

Generally speaking, the closer the distance between the data line 114 and the pixel electrode 160 is, the greater the effect of the stray capacitance between them is, so that the voltage of the pixel electrode 160 is easily affected by the different voltages transmitted by the data line 114, resulting in obvious crosstalk. effect. In order to avoid the crosstalk effect, the overlapping area between the data line 114 and the pixel electrode 160 is usually reduced, but this limits the aperture ratio. In the pixel structure 170 of this embodiment, since the common electrode line 144 disposed between the data line 114 and the pixel electrode 160 can shield the stray capacitance effect generated between the data line 114 and the pixel electrode 160, the pixel electrode 160 The configuration of the pixel structure 170 is not limited thereby, and the aperture ratio of the pixel structure 170 can be effectively improved. Furthermore, the data line 114 formed by part of the first patterned conductor layer 110 is a continuous line segment, so the data line 114 is less likely to be disconnected, which helps to improve the quality of the pixel structure 170 .

In this embodiment, the common electrode line 144 partially overlaps with the pixel electrode 160 to form a storage capacitor Cst. Meanwhile, it should be noted that the common electrode line 144 is, for example, disposed between two adjacent data lines 114 and surrounds the edge of the pixel electrode 160 (as shown in FIG. 1F ). Therefore, the arrangement of the common electrode lines 144 will not greatly decrease the aperture ratio of the pixel structure 170 . When the common electrode line 144 surrounding the edge of the pixel electrode 160 has a common voltage, it is helpful to form a deformed electric field that changes from the edge of the pixel structure 170 to the center of the pixel structure 170 . Therefore, the application of the pixel structure 170 in the liquid crystal display panel can make the liquid crystal molecules have a faster reaction rate, and the liquid crystal molecules can tilt towards the correct direction. Of course, the pixel structure 170 of the present invention is not limited to surrounding the pixel electrode 160 with the common electrode line 144 . In other words, the common electrode lines 114 may also be distributed linearly or in other ways.

Of course, the first patterned conductor layer 110, the semiconductor channel layer 130 and the second patterned conductor layer 140 can be connected through other different connection methods to form the thin film transistor 180 and the data line 114 electrically connected to the thin film transistor 180 and the scanning Line 142. FIG. 3A is a schematic top view of a pixel structure according to another embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line D-D' of FIG. 3A . Please refer to FIG. 3A first, the components of the pixel structure 300 and the pixel structure 170 are substantially the same, and the differences are as follows. In the pixel structure 300 , the first patterned conductor layer 110 further includes a connection layer 116 located under the drain electrode 148 and the pixel electrode 160 . Meanwhile, please refer to FIG. 3A and FIG. 3B , in the pixel structure 300 , for example, the gate insulating layer 120 has a fourth contact window 126 , so that the drain electrode 148 is electrically connected to the connection layer 116 through the fourth contact window 126 . In addition, the passivation layer 150 and the gate insulating layer 120 have, for example, a fifth contact window 154 , so that the pixel electrode 160 is electrically connected to the connection layer 116 through the fifth contact window 154 . At this time, the drain electrode 148 is electrically connected to the pixel electrode 160 through the connection layer 116 , for example.

In detail, the method for electrically connecting the drain electrode 148 to the pixel electrode 160 in this embodiment includes the following steps. Firstly, while forming the first patterned conductor layer 110 , for example, the connection layer 116 on one side of the gate 112 may be formed. That is to say, the connection layer 116 is directly formed on the substrate 100 in this embodiment. In addition, after forming the semiconductor channel layer 130 and before forming the second patterned conductor layer 140, for example, the fourth contact window 126 can be formed in the gate insulating layer 120, so that after the second patterned conductor layer 140 is formed, the drain The electrode 148 is electrically connected to the connection layer 116 through the fourth contact window 126 . In addition, after the protective layer 150 is formed and before the pixel electrode 160 is formed, for example, the fifth contact window 154 is formed in the protective layer 150 to be in the gate insulating layer 120, and after the pixel electrode 160 is formed, the pixel electrode 160 passes through the fifth contact. The window 154 is electrically connected to the connection layer 116 .

When the fourth contact window 126 and the fifth contact window 154 are formed, the range of the contact window (126 or 154) may exceed the range of the connection layer 116 due to an alignment error in the process, thereby exposing a part around the connection layer 116 Substrate 100. After forming the drain electrode 148 or the pixel electrode 160 , a part of the drain electrode 148 or the pixel electrode 160 is directly formed on the substrate 100 . At this time, part of the drain electrode 148 and the pixel electrode 160 will extend from the upper surface of the connection layer 116 to one side of the connection layer 116 and still be a continuously deposited film layer. In other words, even if there is a slight error in the process of forming the contact window ( 126 or 154 ), the connection between the pixel electrode 160 and the connection layer 116 and between the connection layer 116 and the drain 146 is still quite good. That is, the pixel structure 300 of this embodiment has a high process yield.

In addition, the connection layer 116 in this embodiment is located under the ring-shaped common electrode line 144 , so the area around the pixel electrode 160 is affected by the common voltage of the common electrode line 144 , for example. At this time, when the pixel structure 300 is applied to a liquid crystal display panel, the common voltage of the common electrode line 144 is helpful to assist the arrangement of the liquid crystal molecules in a specific direction. Furthermore, when the liquid crystal display panel with the pixel structure 300 is subjected to single-point pressure (such as pressing the liquid crystal display panel with a finger), the liquid crystal molecules can quickly restore their correct alignment direction due to the configuration of the common electrode lines 144 . That is to say, the design of the pixel structure 300 helps to improve the quality of the liquid crystal display panel.

In addition, the pixel structure of the present invention can also have other types of designs. For example, FIG. 4 is a schematic top view of a pixel structure according to another embodiment of the present invention. Please refer to FIG. 4 , the pixel structure 400 is roughly similar to the pixel structure 300, the difference is that: the data line 414 of the pixel structure 400 can be divided into two line segments, wherein the first line segment 414A can be formed by the first patterned conductor layer. The second line segment 414B is formed by the second patterned conductor layer. In other words, the data lines of the pixel structure 400 are not made of only one conductive layer.

The first line segment 414A and the second line segment 414B are electrically connected to each other, for example, through the sixth contact window 416 , and the drain 446 is, for example, directly connected to the second line segment 414B. That is to say, both the drain electrode 446 and the second line segment 414B are made of the second patterned metal layer, for example. In addition, the scan lines 418 and the gates 112 in the pixel structure 400 are, for example, formed by the first patterned conductor layer. Meanwhile, the second line segment 414B crosses over the scan line 142 and is electrically connected to the first line segment 414A. Wherein, the drain electrode 148 is also electrically connected to the pixel electrode 160 through a connection layer 116 . The common electrode line 144 of the pixel structure 400 can also avoid the crosstalk phenomenon generated when the data line 414 transmits signals, and contributes to the good quality of the liquid crystal display panel.

FIG. 5 is a liquid crystal display panel according to an embodiment of the present invention. Referring to FIG. 5 , the liquid crystal display panel 500 includes a first substrate 510 , a second substrate 520 and a liquid crystal layer 530 . The first substrate 510 includes a plurality of pixel structures 540 , and the second substrate 520 is disposed opposite to the first substrate 510 . The second substrate 520 can be, for example, a color filter. Meanwhile, the liquid crystal layer 530 is disposed between the first substrate 510 and the second substrate 520 . The pixel structure 540 is any pixel structure in the above-mentioned embodiments, and the design of the common electrode line can reduce the stray capacitance between the pixel electrode and the data line, so as to avoid the crosstalk effect. The same conductor layer can be used to form the data lines in the pixel structure 540 to reduce the contact resistance of the data lines, so the quality of data transmission is quite good, that is, the liquid crystal display panel 500 with the pixel structure 540 has good quality. At the same time, in the pixel structure 540, a connection layer can be used to electrically connect the drain electrode and the pixel electrode, so as to avoid disconnection between the drain electrode and the pixel electrode, which helps to improve the process yield of the liquid crystal display panel 500 . Furthermore, in the pixel structure of the present invention, the common electrode lines are disposed around the pixel electrodes, and the common voltage thereof is helpful for the arrangement of liquid crystal molecules in the auxiliary liquid crystal layer 530 . In particular, the common voltage of the common electrode line can make the liquid crystal molecules near the thin film transistors tend to the correct alignment direction, so that the liquid crystal display panel 500 can maintain good display quality.

Certainly, the present invention also can have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these Corresponding changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (18)

1. A method for manufacturing a pixel structure, comprising: forming a first patterned conductor layer on a substrate, the first patterned conductor layer including a gate and a data line; forming a gate insulating layer on the substrate to cover the first patterned conductor layer; forming a semiconductor channel layer on the gate insulating layer above the gate; forming a second patterned conductor layer on the gate insulating layer and the semiconductor channel layer, the second patterned conductor layer includes a scan line, a common electrode line, a source and a drain, wherein the scan line electrically connected to the gate, the common electrode line is located above the data line, and the source and the drain are located on the semiconductor channel layer, and the source is electrically connected to the data line; forming a protection layer on the substrate to cover the second patterned conductor layer; and A pixel electrode is formed on the protection layer, and the pixel electrode is electrically connected with the drain. 2. The method for manufacturing the pixel structure according to claim 1, wherein the method for forming the semiconductor channel layer comprises: forming a semiconductor material layer on the gate insulation; performing a doping process to form an ohmic contact layer on the upper surface of the semiconductor material layer; and The semiconductor material layer is patterned to form the semiconductor channel layer. 3. The method for manufacturing the pixel structure according to claim 1, wherein the method for forming the gate insulating layer comprises: forming a first dielectric layer on the substrate; and A first contact window and a second contact window are formed in the first dielectric layer to respectively expose parts of the gate and the data line. 4. The manufacturing method of the pixel structure according to claim 3, wherein the scan line is electrically connected to the gate through the first contact window and the source is electrically connected to the data line through the second contact window. sexual connection. 5. The manufacturing method of the pixel structure according to claim 1, wherein the method for forming the protective layer comprises: forming a second dielectric layer on the substrate and covering the second patterned conductor layer; and A third contact window is formed in the second dielectric layer to expose a part of the drain. 6 . The manufacturing method of the pixel structure according to claim 5 , wherein the pixel electrode is electrically connected to the drain through the third contact window. 7 . The method for manufacturing a pixel structure according to claim 1 , further comprising forming a connection layer on one side of the gate when forming the first patterned conductor layer. 8. The manufacturing method of the pixel structure according to claim 7, further comprising forming a fourth contact window on the gate insulating layer after forming the semiconductor channel layer and before forming the second patterned conductor layer layer to expose a part of the connection layer, so that after the second patterned conductor layer is formed, the drain is electrically connected to the connection layer through the fourth contact window. 9. The manufacturing method of the pixel structure according to claim 8, further comprising forming a fifth contact window on the protective layer and the gate insulating layer after forming the protective layer and before forming the pixel electrode In order to expose a part of the connection layer and form the pixel electrode, the pixel electrode is electrically connected to the connection layer through the fifth contact window. 10. A pixel structure suitable for being configured on a substrate, characterized in that the pixel structure comprises: A first patterned conductor layer, configured on the substrate, the first patterned conductor layer includes a gate and a data line; a gate insulating layer covering the first patterned conductor layer; a semiconductor channel layer configured on the gate insulating layer above the gate; A second patterned conductor layer, disposed on the gate insulating layer and the semiconductor channel layer, the second patterned conductor layer includes a scanning line, a common electrode line, a source and a drain, the scanning line electrically connected to the gate, the common electrode line is located above the data line, and the source and the drain are located on the semiconductor channel layer, and the source is electrically connected to the data line; a protective layer covering the second patterned conductor layer; and A pixel electrode is arranged on the protection layer, and the pixel electrode is electrically connected with the drain. 11 . The pixel structure according to claim 10 , wherein the gate insulating layer has a first contact window and a second contact window respectively located above the gate electrode and the data line. 12. The pixel structure according to claim 11, wherein the scan line is electrically connected to the gate through the first contact window, and the source is electrically connected to the data line through the second contact window. 13. The pixel structure according to claim 10, wherein the protective layer has a third contact window located above the drain, and the pixel electrode is electrically connected to the drain through the third contact window. 14 . The pixel structure according to claim 10 , wherein the first patterned conductor layer further comprises a connection layer located under the drain electrode and the pixel electrode. 15. The pixel structure according to claim 14, wherein the gate insulation layer has a fourth contact window, so that the drain is electrically connected to the connection layer through the fourth contact window. 16. The pixel structure according to claim 14, wherein the protection layer and the gate insulating layer have a fifth contact window, so that the pixel electrode is electrically connected to the connection layer through the fifth contact window . 17. A pixel structure, suitable for being configured on a substrate, characterized in that the pixel structure comprises: A first patterned conductor layer, configured on the substrate, the first patterned conductor layer at least includes a gate and a connection layer; a gate insulating layer covering the first patterned conductor layer; a semiconductor channel layer configured on the gate insulating layer above the gate; A second patterned conductor layer, disposed on the gate insulating layer and the semiconductor channel layer, the second patterned conductor layer at least includes a source and a drain, characterized in that the first patterned conductor layer . The semiconductor channel layer and the second patterned conductor layer jointly constitute a thin film transistor and a data line and a scanning line electrically connected to the thin film transistor; a protective layer covering the second patterned conductor layer; and A pixel electrode is arranged on the protection layer, and the pixel electrode is electrically connected with the drain through the connection layer. 18. The pixel structure according to claim 17, wherein the data line comprises a first line segment and a second line segment, and the first line segment is formed by part of the first patterned conductor layer, and the The second line segment is formed by the second patterned conductor layer and is electrically connected with the first line segment.

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