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CA2014048A1 - Dispositif a semiconducteurs - Google Patents

Dispositif a semiconducteurs

Info

Publication number
CA2014048A1
CA2014048A1 CA2014048A CA2014048A CA2014048A1 CA 2014048 A1 CA2014048 A1 CA 2014048A1 CA 2014048 A CA2014048 A CA 2014048A CA 2014048 A CA2014048 A CA 2014048A CA 2014048 A1 CA2014048 A1 CA 2014048A1
Authority
CA
Canada
Prior art keywords
region
type
semiconductor device
insulation film
conductive layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2014048A
Other languages
English (en)
Other versions
CA2014048C (fr
Inventor
Hiroshi Hatano
Ichiro Yoshii
Satoru Takatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2014048A1 publication Critical patent/CA2014048A1/fr
Application granted granted Critical
Publication of CA2014048C publication Critical patent/CA2014048C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CA002014048A 1989-04-07 1990-04-06 Dispositif a semiconducteurs Expired - Fee Related CA2014048C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-88730 1989-04-07
JP1088730A JPH079932B2 (ja) 1989-04-07 1989-04-07 半導体装置

Publications (2)

Publication Number Publication Date
CA2014048A1 true CA2014048A1 (fr) 1990-10-07
CA2014048C CA2014048C (fr) 1994-12-20

Family

ID=13951034

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002014048A Expired - Fee Related CA2014048C (fr) 1989-04-07 1990-04-06 Dispositif a semiconducteurs

Country Status (5)

Country Link
EP (1) EP0391420B1 (fr)
JP (1) JPH079932B2 (fr)
KR (1) KR930003559B1 (fr)
CA (1) CA2014048C (fr)
DE (1) DE69033187T2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670816A (en) * 1989-04-07 1997-09-23 Kabushiki Kaisha Toshiba Semiconductor device
JP2596340B2 (ja) * 1993-10-08 1997-04-02 日本電気株式会社 半導体装置
JP3689505B2 (ja) * 1995-11-01 2005-08-31 キヤノン株式会社 半導体装置の作製方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3338758A (en) * 1964-12-31 1967-08-29 Fairchild Camera Instr Co Surface gradient protected high breakdown junctions
JPS5694768A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Semiconductor memory device
US4506436A (en) * 1981-12-21 1985-03-26 International Business Machines Corporation Method for increasing the radiation resistance of charge storage semiconductor devices
JPS602782B2 (ja) * 1982-06-30 1985-01-23 富士通株式会社 半導体記憶装置
JPS61124150A (ja) * 1984-11-20 1986-06-11 Nec Corp 半導体集積回路装置
JPS61164265A (ja) * 1985-01-16 1986-07-24 Nec Corp Ｍｉｓ型半導体集積回路装置
JPH0783046B2 (ja) * 1985-03-22 1995-09-06 日本電気株式会社 半導体集積回路装置及びその製造方法

Also Published As

Publication number Publication date
DE69033187D1 (de) 1999-08-05
JPH02267970A (ja) 1990-11-01
KR930003559B1 (ko) 1993-05-06
EP0391420B1 (fr) 1999-06-30
KR900017179A (ko) 1990-11-15
JPH079932B2 (ja) 1995-02-01
CA2014048C (fr) 1994-12-20
DE69033187T2 (de) 1999-12-02
EP0391420A2 (fr) 1990-10-10
EP0391420A3 (fr) 1991-04-17

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed