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KR910007068A - 유전체분리구조를 갖춘 반도체기판의 제조방법 - Google Patents

유전체분리구조를 갖춘 반도체기판의 제조방법 Download PDF

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Publication number
KR910007068A
KR910007068A KR1019900014439A KR900014439A KR910007068A KR 910007068 A KR910007068 A KR 910007068A KR 1019900014439 A KR1019900014439 A KR 1019900014439A KR 900014439 A KR900014439 A KR 900014439A KR 910007068 A KR910007068 A KR 910007068A
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KR
South Korea
Prior art keywords
manufacturing
semiconductor substrate
semiconductor substrates
separation structure
high concentration
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Application number
KR1019900014439A
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English (en)
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KR940008557B1 (ko
Inventor
마사노부 오기노
츠토무 아마이
다카노부 가마쿠라
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR910007068A publication Critical patent/KR910007068A/ko
Application granted granted Critical
Publication of KR940008557B1 publication Critical patent/KR940008557B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

유전체분리구조를 갖춘 반도체기판의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체기판의 제조공정도.

Claims (2)

  1. 소정의 도전형 제1 및 제2반도체기판(70, 72)의 적어도 각 한쪽면을 경면연마하는 제1공정과, 상기 제1공정과 의해 경면연마된 상기 한쪽면상의 어느 것에 유전체막(71)을 형성하는 제2공정, 상기 제2공정에 의해 형성된 상기 유전체막(71)이 삽입장착되도록 해서 상기 제1 및 제2반도체기판(70, 72)의 각 경면측을 대면시켜 접합하고 열처리하는 제3공정, 상기 제3공정에 의해 각 경면측을 대면시켜 접합한 상기 제1 및 제2반도체기판(70,72)의 어느 한쪽면을 상기 유전체막(71)측을 기준으로 소정의 두께로 연삭하는 제4공정, 상기 제4공정에 의해 소정의 두께로 연삭된 면에 저농도불순물을 도입하는 제5공정, 상기 제5공정에 의해 고농도불순물이 도입된 면상에 저농도불순물반도체층(74)을 형성하는 제6공정을 구비한 것을 특징으로 하는 반도체기판의 제조방법.
  2. 제1항에 있어서, 제5공정에서 소정의 두께로 연삭된 면에 고농도 N형 불순물과 고농도 P형 불순물을 각각 소정의 영역에 도입하는 것을 특징으로 하는 반도체기판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900014439A 1989-09-13 1990-09-13 유전체분리구조를 갖춘 반도체기판의 제조방법 KR940008557B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP23745789 1989-09-13
JP01-237457 1989-09-13
JP2175527A JP2825322B2 (ja) 1989-09-13 1990-07-03 誘電体分離構造を有する半導体基板の製造方法
JP02-175527 1990-07-03

Publications (2)

Publication Number Publication Date
KR910007068A true KR910007068A (ko) 1991-04-30
KR940008557B1 KR940008557B1 (ko) 1994-09-24

Family

ID=26496780

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014439A KR940008557B1 (ko) 1989-09-13 1990-09-13 유전체분리구조를 갖춘 반도체기판의 제조방법

Country Status (4)

Country Link
EP (1) EP0418737B1 (ko)
JP (1) JP2825322B2 (ko)
KR (1) KR940008557B1 (ko)
DE (1) DE69027082T2 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69127582T2 (de) * 1990-05-18 1998-03-26 Fujitsu Ltd Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates
EP0525256A1 (en) * 1991-07-25 1993-02-03 Motorola, Inc. Method of fabricating isolated device regions
TW211621B (ko) * 1991-07-31 1993-08-21 Canon Kk
SE469863B (sv) * 1991-10-15 1993-09-27 Asea Brown Boveri Halvledarkomponent, halvledarskiva för framställning av halvledarkomponent samt förfarande för framställning av sådan halvledarskiva
SE500815C2 (sv) * 1993-01-25 1994-09-12 Ericsson Telefon Ab L M Dielektriskt isolerad halvledaranordning och förfarande för dess framställning
SE500814C2 (sv) * 1993-01-25 1994-09-12 Ericsson Telefon Ab L M Halvledaranordning i ett tunt aktivt skikt med hög genombrottsspänning
JP3957038B2 (ja) 2000-11-28 2007-08-08 シャープ株式会社 半導体基板及びその作製方法
JP2012064802A (ja) * 2010-09-16 2012-03-29 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0671043B2 (ja) * 1984-08-31 1994-09-07 株式会社東芝 シリコン結晶体構造の製造方法
JPS61182240A (ja) * 1985-02-08 1986-08-14 Toshiba Corp 半導体装置の製造方法
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
JPS63311753A (ja) * 1987-06-15 1988-12-20 Sanyo Electric Co Ltd 半導体集積回路の製造方法
JPH01196169A (ja) * 1988-01-30 1989-08-07 Sony Corp 半導体装置の製造方法
JP2788269B2 (ja) * 1988-02-08 1998-08-20 株式会社東芝 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP0418737B1 (en) 1996-05-22
KR940008557B1 (ko) 1994-09-24
JP2825322B2 (ja) 1998-11-18
DE69027082T2 (de) 1996-10-31
EP0418737A1 (en) 1991-03-27
DE69027082D1 (de) 1996-06-27
JPH03174740A (ja) 1991-07-29

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