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A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all... more
A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz
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The design cycle of the proposed asynchronous multiple functional unit networks, from CAD tool coding to post-layout scalability, adheres to the attributes of rapid prototyping. These attributes come in five flavors: an OOP style in CAD... more
The design cycle of the proposed asynchronous multiple functional unit networks, from CAD tool coding to post-layout scalability, adheres to the attributes of rapid prototyping. These attributes come in five flavors: an OOP style in CAD tools; a short design, modify, evaluate and profile cycle at the dataflow graph level; the reuse of predesigned components; effective event realization of the asynchronous behavior; and rapid VLSI realization. At the modeling level, a dataflow graph modeling tool specifies and profiles the asynchronous systems rapidly and accurately. At the architectural level, several multiple functional unit networks illustrate two rarely addressed issues in asynchronous design: modularity and scalability, which are the keys to rapid prototyping. Networks in a distributor approach and a tournament protocol are presented, where fixed and greedy operand assignments are used respectively. The tournament protocol also leads to a short physical design time and a compact VLSI layout for its regular structure
Research Interests: Computer Science, Object Oriented Programming, Computational Modeling, VLSI, Field-Programmable Gate Arrays, and 11 moreRapid Prototyping, Protocols, Very Large Scale Integration, Modularity, Prototypes, Scalability, Network Topology, Physical Design, Integrated Circuit Design, Graph Model, and Modeling Tool
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Research Interests: Engineering, Computer Science, Optimal Control, Semiconductor Manufacturing, Power Consumption, and 10 moreTemperature, Low Power Electronics, Variational Approach, Thermal management, Perforation, Dynamic Voltage and Frequency Scaling, Calculus of Variation, Power Modeling, Speed Control, and Time varying
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Research Interests:
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Abstract In this paper, we present a design space exploration of optimal many-core processors for the physics-based sound synthesis of guitar by quantitatively evaluating the impact of a sample-per-processing element (SPE) ratio-the... more
Abstract In this paper, we present a design space exploration of optimal many-core processors for the physics-based sound synthesis of guitar by quantitatively evaluating the impact of a sample-per-processing element (SPE) ratio-the amount of sample data directly ...
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Research Interests:
The increasing popularity of low power computing drives the need for increasing battery life-time by power-optimizing application programs. This requires a tool capable of providing a system-level energy model. We present a methodology... more
The increasing popularity of low power computing drives the need for increasing battery life-time by power-optimizing application programs. This requires a tool capable of providing a system-level energy model. We present a methodology for simulating and profiling energy consumed by software applications running on computing systems. The uniqueness of our framework lies in its ability to capture at a fine granularity, power behavior of the software executing on the system as well as of each of the hardware components in the system and its applicability to a wide variety of computing systems. We demonstrate our work on a real world platform, the Itsy, a handheld computer developed by Compaq's Western Research Labs.
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Research Interests: Computer Science, Network Flows, Embedded and Reconfigurable Systems, Hardware, Reconfigurable Hardware, and 11 moreLow Power Electronics, Acm, Waste minimisation, Network Flow, Polynomials, Embedded System, Dynamic Reconfiguration, Control Flow Graph, Application Software, Optimal Solution, and Polynomial Time
Research Interests: Engineering, Thermal Engineering, Computer Science, Optimal Control, Simulation, and 13 morePower Consumption, Frequency, Throughput, Temperature measurement, Chip, Thermal management, Multicore Processing, Power Reduction, Speed Control, Performance Optimization, Process Capability, Multi-Core Processor, and statistical power analysis
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Research Interests: Mathematics, Stochastic Process, Computer Science, Monte Carlo Simulation, Statistical Analysis, and 14 moreMonte Carlo, Stochastic analysis, Stochastic processes, Power Analysis, Process Variation, Efficient Algorithm for ECG Coding, Power Grid, Variational Analysis, Correlations, Polynomial Chaos, Discrete random variable, Galerkin Method, Process Variations, and Integrated Circuit Design
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ABSTRACT Chalcogenide glass-based programmable metallization cell (PMC) devices undergo Ag+-ion transport and controlled resistance change under the application of electrical bias. In this paper, photo-doped PMC devices are characterized... more
ABSTRACT Chalcogenide glass-based programmable metallization cell (PMC) devices undergo Ag+-ion transport and controlled resistance change under the application of electrical bias. In this paper, photo-doped PMC devices are characterized with impedance spectroscopy. Photo doping is an important step in PMC fabrication as it introduces the mobile Ag into the electrolyte and, therefore, has a significant effect on device characteristics. Data obtained from measurements on devices with different areas in both their high resistance state (HRS) and low resistance state (LRS) are used to parameterize equivalent circuit models. The models elucidate the differences in the HRS and LRS electrical properties.
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Edge- Valued Binary-Decision Diagrams (EVBDD)S are directed acyclic graphs which can represent and manipulate integer functions as effectively as Ordered Binary-Decision Diagrams (OBDDS) do for Boolean functions, They have been used to... more
Edge- Valued Binary-Decision Diagrams (EVBDD)S are directed acyclic graphs which can represent and manipulate integer functions as effectively as Ordered Binary-Decision Diagrams (OBDDS) do for Boolean functions, They have been used to perform logic verification and compute decomposability of Boolean functions. In this paper, rue present a new EVBDD application for solving Integer Linear Programs (ILP), which is an Np-hard
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Research Interests: Mathematics, Computer Science, Distributed Computing, Linear Programming, Convex Optimization, and 15 moreEnergy Consumption, Energy efficiency, Numerical Simulation, Circuits, CDMA, Convex Programming, Energy efficient, Interior Point Method, Energy Efficiency, Numerical Solution, Geometric Programming, Code Division Multiple Access, Electrical And Electronic Engineering, LINEAR PROGRAM, and Fast Algorithm
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Research Interests: Distributed Computing, Production, Statistical Analysis, Computer Hardware, Fault Tolerance, and 13 moreQuality Assurance, Computer Software, Sampling methods, Sequential Analysis, Probability Mass Function, Random Testing, Waiting Time, Random Sequences, Sequential Sampling, Fault Coverage, Expected Value, Higher order, and Probability Generating Function
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Research Interests: Engineering, Computer Science, Computer Aided Design, Computer Hardware, Failure Analysis, and 10 moreNoise estimation, Mean Time To Failure, High performance, Lower Bound, Upper Bound, Electrical And Electronic Engineering, Noise analysis, Integrated Circuit Design, Probability of Failure, and Probabilistic Approach
Formal Verification Design-Intent Coverage—A New Paradigm for Formal Property Verification................................................... P. Basu, S. Das, A. Banerjee, P. Dasgupta, PP Chakrabarti, CR Mohan, L. Fix, and R. Armoni 1922 Hardware/Software Co-Design PrePack: Predictive Packetizing...more
In this paper we present a dynamically reconfigurable mixed-signal circuit using the new technology of Field Programmable Analog Arrays (FPAA) combined with existing well established technology of Field Programmable Gate Arrays (FPGA). A... more
In this paper we present a dynamically reconfigurable mixed-signal circuit using the new technology of Field Programmable Analog Arrays (FPAA) combined with existing well established technology of Field Programmable Gate Arrays (FPGA). A FPAA can be used to build filters for analog ...
Research Interests: Process Control, Digital Control, Adaptive Filtering, New Technology, Reconfigurable Hardware, and 9 moreDigital Systems, Analog, Adaptive Filter, Western, Field Programmable Gate Array, Field Programmable Analog Array, Hardware Implementation of Algorithms, Dynamic Reconfiguration, and Switched capacitor
... The fth column indicates the switching activity per gate SWPG of the circuit and the last column labeled as ATA shows the average ... Brain Nalle, Stephen Lim, Hector Sanchez, and Dr. ShervinHojat of Somerset Design Center, Motorola... more
... The fth column indicates the switching activity per gate SWPG of the circuit and the last column labeled as ATA shows the average ... Brain Nalle, Stephen Lim, Hector Sanchez, and Dr. ShervinHojat of Somerset Design Center, Motorola Inc., for their help in con-ducting the ...
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In technology mapping, enumeration of subcircuits or cuts to be replaced by a standard cell is an important step that decides both the quality of the solution and execution speed. In this work, we view cuts as set of edges instead of as... more
In technology mapping, enumeration of subcircuits or cuts to be replaced by a standard cell is an important step that decides both the quality of the solution and execution speed. In this work, we view cuts as set of edges instead of as set of nodes and based on it, provide a classification of cuts. It is shown that if enumeration is restricted to a subclass of cuts called unidirectional cuts, the quality of solution does not degrade. We also show that such cuts are equivalent to a known class of cuts called strong line cuts first proposed in [14]. We propose an efficient enumeration method based on a novel graph pruning algorithm that utilizes network flow to approximate minimum strong line cut. The runtimes for the proposed enumeration method are shown to be quite practical for enumeration of a large number of cuts.
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The next significant step in the evolution and proliferation of artificial intelligence technology will be the integration of neural network (NN) models within embedded and mobile systems. This calls for the design of compact, energy... more
The next significant step in the evolution and proliferation of artificial intelligence technology will be the integration of neural network (NN) models within embedded and mobile systems. This calls for the design of compact, energy efficient NN models in silicon. In this article, we present a scalable application-specific integrated circuit (ASIC) design of an energy-efficient Long Short-Term Memory (LSTM) accelerator, named ELSA, which is suitable for energy-constrained devices. It includes several architectural innovations to achieve small area and high energy efficiency. To reduce the area and power consumption of the overall design, the compute-intensive units of ELSA employ approximate multiplications and still achieve high performance and accuracy. The performance is further improved through efficient synchronization of the elastic pipeline stages to maximize the utilization. The article also includes a performance model of ELSA, as a function of the hidden nodes and timeste...
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This article demonstrates an unconventional approach to computing logic functions for use in ASICs, and a fully automated approach to technology mapping for standard cell ASICs using the new cells. The approach results in a significant... more
This article demonstrates an unconventional approach to computing logic functions for use in ASICs, and a fully automated approach to technology mapping for standard cell ASICs using the new cells. The approach results in a significant reduction in power, leakage, area and wire-length, without sacrificing performance of the design. At the heart of this approach is a configurable threshold logic gate. Using a standard cell library of such gates, a new technology mapping algorithm is applied to automatically transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. The mapping algorithm is based on logic decomposition of Boolean functions into specific threshold functions. This approach was used to fabricate a 32-bit signed 2-stage Wallace-Tree multiplier in a 65-nm LP technology. Simulation and chip measurement results of the multiplier show a 33% improvement in dynamic power at 30% switching activity, 24% lower core area, 45% lower wire-length and 50% lower leakage without any performance degradation, compared to a functionally equivalent, conventional standard cell implementation. Similar results are shown for a FIR filter, a 32-bit MIPS, a 128-bit AES encryption circuit and a floating-point multiplier.
... Let IS,i represent the sub-threshold leakage of a gate i. In this work the sub-threshold leakage of a circuit is modeled using the BSIM model [10] as ... where ωn is the solution of c − ω tan(ωa) = 0 and ω + c tan(ωa)=0 for odd and... more
... Let IS,i represent the sub-threshold leakage of a gate i. In this work the sub-threshold leakage of a circuit is modeled using the BSIM model [10] as ... where ωn is the solution of c − ω tan(ωa) = 0 and ω + c tan(ωa)=0 for odd and even n respectively. ...
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ABSTRACT Increasing variability in the manufacturing process and growing com-plexity of the integrated circuits has given rise to many design and ver-ification challenges. Statistical analysis of circuits and current source based gate... more
ABSTRACT Increasing variability in the manufacturing process and growing com-plexity of the integrated circuits has given rise to many design and ver-ification challenges. Statistical analysis of circuits and current source based gate delay models have started to replace the ...