DYNAMICALLY RECONFIGURABLE ANALOG/DIGITAL HARDWARE IMPLEMENTATION USING FPGA AND FPAA TECHNOLOGIES Cornel Reiser1, Lech Znamirowski 2, Olgierd A. Palusinski 3, Sarma B.K.Vrudhula3, Daler Rakhmatov3 1 Institut fuer Theoretische Elektrotechnik, University of Karlsruhe, 76128 Karlsruhe, Germany E-mail: cornel.reiser@stud.uni-karlsruhe.de 2 Instytut Informatyki, Technical University of Silesia, Ul. Akademicka 16, 44-100 Gliwice, Poland E-mail: lznamiro@top.iinf.polsl.gliwice.pl 3 Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721, USA E-mail: palusinski@ece.arizona.edu KEYWORDS Reconfigurable hardware, mixed-signal circuits, adaptive filtering, analog and digital arrays. ABSTRACT In this paper we present a dynamically reconfigurable mixed-signal circuit using the new technology of Field Programmable Analog Arrays (FPAA) combined with existing well established technology of Field Programmable Gate Arrays (FPGA). A FPAA can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experiment described in this paper takes advantage of performance and programmability of the FPAA for filtering of an analog signal controlled by a digital system. Investigations of such a hardware in application to adaptive signal filtering and process control are in progress. The paper will present results of work on adaptive filtering with dynamic reconfiguration based on 2 parallel FPAA chips cooperating with a digital control system. Theoretical studies and measurements of transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions as well as for model modifications. INTRODUCTION Digital circuits can be applied to implement highaccuracy and high-complexity signal processing algorithms for low frequency signals where power dissipated during the operations is not critical. Analog circuits offer advantages in applications where signal frequencies are high and low power dissipation is essential. However, the accuracy of analog circuits is limited and they can not be used to implement algorithms of high complexity. Consequently, processing in a large system is assigned accordingly to analog and digital circuits to take advantage of specific circuit properties for overall performance optimization, such as power minimization. If the processing requirements and algorithms change over time, the optimal assignment of processing functions may change and dynamic reassignment of functions and reconfiguration of circuits may be necessary. The new technology of Field Programmable Analog Arrays (FPAA) in combination with the well known technology of Field Programmable Gate Arrays (FPGA) provides a basis for the development of a dynamically reconfigurable analog/digital hardware. Such a mixed-signal circuit is very suitable for applications in mobile systems such as cell phones and other portable telecommunication systems in general, because of the opportunity for reducing power dissipation through proper assignment of hardware processing functions to analog and digital circuits. THE FIELD PROGRAMMABLE ANALOG ARRAY (FPAA) A Field Programmable Analog Array (FPAA), built in CMOS technology, contains uncommitted operational amplifiers, switches, and banks of programmable switched capacitors (S/C) and can be used to build filters for analog signals as well as a large number of diverse analog applications. The parameters of a given application, such as a filter, are functions of the capacitor values. The chip is divided into 20 identical, configurable analog blocks (CABs), each composed of an operational amplifier, five capacitor banks, and switches that can be used to interconnect the cell components and determine their operation. There are both static and dynamic CMOS switches. The static switches are used to determine the configuration of cell components and inter-cell connections. These switch settings are determined once during the programming phase of an application after which they remain unchanged. The dynamic switches are associated with capacitors and are switched periodically during the circuit operation changing the effective function of capacitors as typically exploited in switched capacitor (S/C) circuits. Both static and dynamic switches are electronically controlled and thus the functionality of each CAB, the capacitor sizes, and the interconnections between CABs are programmable. As a result many diverse circuit architectures can be implemented. The FPAA used in this study is Motorola’s MPAA020 which contains 41 operational amplifiers, 100 programmable capacitors, 6864 electronic switches arranged into the 20 CABs, and 13 input/output buffers. The array is structured in a grid that contains the 20 CABs arranged in a 4x5 matrix. Configuring an analog design within the array is performed by downloading 6K bits of data via RS232 communications from a PC or EPROM. The data stream contains information to configure the individual cells, the cell to cell interconnections, internal voltage reference as well as the input and output connections. During the configuration download process all cells are placed in a power-down mode to protect the CABs against undesirable high currents. The switches allow control over the circuit connectivity and capacitor values in addition to other features. The complexity of control is so high that a supporting software was developed to facilitate the chip programming. The software allows a user to easily manipulate these fieldprogrammable switches in order to implement a specific circuit. The chip programming software is called EasyAnalog and runs under Windows 3.1, Windows 95, and Windows NT operating systems. The basic interface window of EasyAnalog displays a simplified view of 20 CABs, 13 I/O isolation amplifiers, and inter-cell connecting lines. With a “point and click” action the user can select and place “macros” from a function library onto the chip in any feasible cell location. Each macro is a pre-configured sub-circuit such as a gain-stage, filter, full-wave rectifier, or biquad, just to mention some examples. Several macros can be placed onto the chip and “wired” together as required by an application. There are also some “pre-wired” application circuits, stored in a library, which can be selected and placed on the chip. Parameters of the library components can be selected and changed, as needed in the application, using pull-down menus and pop-up windows. (Birk 1998; Palusinski et al. 1998) The FPAA technology is suitable for numerous engineering applications like electrical signal filtering, construction of controllers and phase correctors for continuous and sampled data feedback systems, conditioning of sensor signals and signal generation. The power of the FPAA is that it can be reconfigured “on the fly” to implement different device or parameter settings and that’s why the chip is so suitable for dynamic reconfiguration as it is demonstrated in the experimental investigations presented in this paper. SYSTEM DESCRIPTION The basic concept of reconfigurable hardware is illustrated here using 2 parallel FPAAs which are being switched by a multiplexer. A digital system controls the switching and provides communication to the FPAAs in control of reconfiguration. At the moment all the control is done by a PC and the software EasyAnalog , but future implementations will use a FPGA. Future plans also include digitization of the analog signal input and output to the FPGA in order to implement a digital feedback loop for comparison and control of the filter behavior. The control signal for the multiplexer is generated on the FPAA during the programming phase. So when the FPAA starts to work after reconfiguration a high peak appears that enters into an adjustable time delay circuit on the control board and then to the multiplexer in order to interchange the analog outputs of the FPAAs. The block diagram of the system is shown in Figure-1. Digital Input Digital Feed Back PC/FPGA Download Control 1 ADC ADC FPAA 1 IN 1 Control Board Analog Input Analog Output IN 2 FPAA 2 Control 2 Figure-1 Block diagram of the system composed of 2 parallel FPAAs In this system one FPAA can filter the analog input signal while the other one is ‘off-line’ waiting for reprogramming and subsequent switching to the on-line mode by the multiplexer after which time the first FPAA can then be reprogrammed and prepared for future on-line filtering. This system provides a steady output signal without an interruption when there’s a need for redefinition of the analog filter function. The described process is illustrated in Figure-2. FPAA1 switching moment A delicate aspect of the dynamic reconfiguration is the transition behavior of the switching from one FPAA to the other. After the FPAA is reprogrammed it cannot be put immediately “on-line” because the signal needs some time to settle and reach a steady state. That’s why it is necessary to provide a time delay between the end of the programming phase and the actual physical switching. switching moment filtering signal off-line filtering signal programming t FPAA2 off-line programming filtering signal off-line programming t Output t switching delay switching delay Figure-2 Timing diagram of reprogramming and filtering of 2 parallel FPAAs for uninterrupted processing of an analog input signal. We shall analyze this circuit using sinusoidal analog input signals as this will demonstrate of how switching between the two FPAAs is carried out. For example if one changes the quality factor of a low-pass filter and switches at the peak of the output signal there will be a jump in the output as illustrated in Figure-3. Such a jump should be avoided because it causes an injection of high frequency components. For this reason it is necessary to switch at the zero crossing of the sinusoidal signal to avoid undesirable jumps of the amplitude. However, if the corner frequency of the filter or the whole filter in general will be changed, one has to deal with discontinuities in the amplitude as well as a phase shift. 2πf 0 2 s + Q s + 4π f 0 = 0 2 2 (3) For the unit-step input and the Laplace inversion obtained the output time response is given by (Nagrath 1975) h( t ) = R | G S1 − | T − 2πf 0 t 2Q e (1 − 1 4Q 2 ) * sin LM2πf 0 (1 − 1 N 4Q2 U )t + tan −1 ( 4Q 2 − 1) O (4) PV QW The steady-state value of h(t) is given as hss = lim h ( t ) = G (5) t →∞ It can be observed that the time response h(t) oscillates between a pair of envelopes before reaching steady-state for Q>0.5. The transient is comprised of a product of an − exponentially decaying term e oscillating term sin 2πf0 (1− 1 4Q 2 2 πf 0 t 2Q and a sinusoidally )t + tan − 1 ( 4Q 2 − 1) . The time constant of the exponential envelope is T = Figure-3 High pass filter switching from Q=20 to Q=0.5 after time delay To properly control the switching of the system it is necessary to investigate the system transitions in order to determine the settling time which would allow a selection of appropriate time delay. SETTLING TIME OF SYSTEMS OF 2ND ORDER The analysis presented here is applicable to any secondorder system (biquad). The transfer function of a low pass biquad is 4π 2 f 2G Hlow pass ( s ) = − 2 2πf 0 2 2 s + Q s + 4π f 0 0 Q . π f0 The settling time ts is defined as the time period the signal needs to get within a certain tolerance band around the steady-state value and stays within these bounds. Considering only the exponentially decaying envelope for a tolerance band of 1% the settling time is given by − πf 0 ts e Q = 0.01 (1 − 14Q2 ) − For Q>>0.5 we have e πf 0 t Q s (6) ≈ 0.01 . This yields the settling time t s ts = 4.605Q πf 0 (7) (1) where G is the pass-band gain (DC-Gain), Q is the quality factor, and f 0 is the corner frequency of the filter. The time response of this system is characterized by the roots of the denominator polynomial q(s), which in fact are the poles of the transfer function. The denominator polynomial q(s) is therefore called the characteristic polynomial and q( s ) = 0 (2) is called the characteristic equation. The characteristic equation of the system under consideration is This formula (7) is applicable for all biquad filters. MEASUREMENTS OF SETTLING TIME The measurements were performed to verify the analytical results and to demonstrate that the described settling behavior is observable for an input step function as well as sinusoidal signals. A constant pass-band gain of G=1 was used in all measurements. An example of a measurement performed to determine a settling time in the system is given in Figure-4. The relative error between the calculated and the linear fit of this measured values is 2.05% and is mainly caused by reading errors of the oscilloscope because of the low resolution. The errors of other filter measurements are shown in Table-1. The settling behavior of biquad filters for various quality factors and corner frequencies are shown in Figure-6. Inspection of the graph indicates that the settling time increases significantly for very low corner frequencies and follows linearly with increasing quality factor. This means that one has to switch with a long time delay for filters with low corner frequency and high quality factor in order to avoid perturbations. Figure-4 Settling behavior of band pass filter after switching Cumulative results of measurements of the settling time as a function of the biquad quality factor are shown in Figure-5. The plot shows that the behavior of a high pass biquad filter (high Q) with corner frequency of 25 kHz follows the analysis presented here. For linearization of the distributed measured values the method of linear regression was used (Allen and Holberg 1975). Title: /home/cornel/matlab/plots/HQ3D_lf_plot.eps Creator: MATLAB, The Mathworks, Inc. CreationDate: 10/02/98 17:03:39 Title: /home/cornel/matlab/plots/HPHQ25_linR_plot.eps Creator: MATLAB, The Mathworks, Inc. CreationDate: 10/23/98 11:55:42 Figure-6 Settling time behavior versus quality factor and corner frequency During various measurements it was observed that for both inputs, step function and sinusoidal signal, the output is wedged into the exponential envelope described before. This means that the measured settling time of a step input is also the time period within which the sinusoidal signal settles in. Figure-5 Settling behavior of high pass filter at corner frequency of 25 kHz Table-1 Relative errors of the measured settling time of various filters Filter Corner frequency Relative error high pass 100 kHz 0.55% band stop 50 kHz 1.35% band pass 50 kHz 1.46% band pass 10 kHz 3.42% low pass 25 kHz 6.32% CASCADING BIQUADS For filters of higher order it is also necessary to investigate the settling behavior. In a simple experiment we investigated how the chip behaves when identical biquads with known settling time are cascaded. All the cascaded (2 up to 10) biquads are identical with the same corner frequency and quality factor. The cumulative results are shown in Figure-7. Title: /home/cornel/matlab/plots/Cas2Q1_plot.eps Creator: MATLAB, The Mathworks, Inc. CreationDate: 10/09/98 11:54:31 systems show also the analogous behavior of the settling time with respect to changes of the characteristic values, the corner frequency and the quality factor, to that of a biquad filter. ACKNOWLEDGEMENTS This work was carried out at the Center for Low Power Electronics which is supported by the National Science Foundation, the Department of Commerce of the State of Arizona, and companies in the microelectronics industry, including Ambit, Analog Devices, Analogy, Burr Brown, Gain Technology, Intel, InterHDL, Microchip, Motorola, Raytheon, Rockwell, Texas Instruments, and Western Design. REFERENCES Allen, P.E. and D.R. Holberg. 1975. CMOS Analog Circuit Design, Oxford University Press, New York Birk, C. 1998. “Evaluation of Filters implemented using a Field Programmable Analog Array”,WMC’98 - ICSEE, San Diego, California, Jan. 11-14, 1998. Figure-7 Settling behavior of identical cascaded high pass biquad filters versus corner frequency. Additional measurements with different quality factors showed the same result with regard to the shape of the curve. It can be easily observed that the settling time of the entire circuit follows the reciprocal value of the corner frequency. This is analogous to the theoretical and measured results for the settling time of a particular biquad shown in the previous sections. SUMMARY This paper presents a model for dynamic reconfiguration of analog filters using 2 parallel Field Programmable Analog Arrays controlled by a digital system and switched by a multiplexer. Performance imperfections caused by the switching process are discussed. In order to determine a certain time delay to “hide” these perturbations, analytical investigations about settling behavior of filters of 2nd order were done and compared to measured values. It is shown that this theoretical rule can be used for determination of the time delay for optimization of the transition behavior switching from one FPAA to another. Measurements of cascaded Nagrath, I.J. 1975. Control systems engineering, John Wiley & Sons, New York Palusinski, O.A.; D.M. Gettman; D. Anderson; H. Anderson; C. Marcjan. “Filtering applications of Field Programmable . Journal of Circuits, Systems and Computers. World Scientific Pub, Oct. 1998 (in print).