Static random access memory

The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPCt cores, high-performance

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip,

The development of flexible and inexpensive controller for large scale light emitting diode (LED) video display image rendering is presented. The concept and system components of such system are presented. Controller is capable of discrete pixel intensity dimming by using the pulse width modulation (PWM). It can control the LED boards containing pixel arrays or the individual pixels/pixel strings. High dimming resolution usually contradicts with high refresh frequency and number of controllable LEDs. Thanks to novel dimming technique the dimming resolution can be varied without significant loss of refresh frequency or number of controllable LEDs. Data between the structure blocks circulates in a series fashion using the conventional shielded twisted pair (STP) cable. The structure and functional diagram of the serializer and deserializer needed for data transmission are presented. Control is accomplished by personal computer (PC) via a high speed universal serial bus (USB2) interfac...

Ternary content addressable memory (TCAM) is a high performance search engine which accesses the data based on
its contents in a single clock cycle. To reduce the power consumption of the TCAM cell when we search the data. Most memory
devices store and retrieve data by addressing specific memory location. As a result this path often becomes the limiting factor for
the systems that rely on fast memory access. In this paper to design six transistors based SRAM design with eight transistors of
two side self gating TCAM and to design four transistors using transmission gate logic function of XOR based TCAM. This
design is to increase the matched line search process and to reduce the overall dynamic power consumption level of TCAM array
design. Our proposed work is to design CMOS based RAM and Ternary CAM memory architecture. This design is used to find
matched line data effectively and to reduce the leakage power level for match line searching process

This article presents a correlation between dynamic power supply current and pattern sensitive faults in SRAMs. It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells. Switching of the logic state of a memory cell results in a transient current pulse in the power supply rails. A new

As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography (HOMA) in [2] and [3]. Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that their electrical characteristics are comparable to those of existing bitcells.

In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bitline to resolve the write '1' issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby.

In this paper, the impact of process/technology co-optimization on silicon-on-insulator (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal–oxide–semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a "~2 times" improvement in static random-access memory and digital input/output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are

Random Access Memory (SRAM) design. SRAM are widely used in computer systems and many portable devices. Proposed SRAM is faster because of precharging at a desired voltage. For the most recent CMOS technologies leakage power dissipation has become a ...

A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm2 low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.

This paper proposes a high-speed multi-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. It investigates the impact of process, voltage and temperature (PVT) variations on its design metrics and compares the results with its counterpart – CMOS-based 7T SRAM cell. The proposed design offers 77.4× improvement in write access time along with 88.1× reduction in write access

We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of catalyst, adds a functionally redundant block—which includes a piece of combinational logic and several other registers—to the circuits under consideration so that the timing critical paths are divided into stages. During this transformation, the circuit's functionality is not affected, while the speed is improved significantly. This technique has been successfully applied to an industrial application—a Built-In Self-Test (BIST) circuit for static random access memories (SRAMs). The synthesis result indicates a 47% clock cycle time reduction.

SUMMARY A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a veryhigh-speed and low-power memorysy stem that also includes refresh-free, compact RTD-based memorycells. By combining RTDs with n-type transistors of conventional com- plementarymetal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) familyof logic circuits, having verylow power-delayproduct and good noise immunity , has recentlybeen developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stabilityanaly sis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable ...