WORKSHOP ON

PROGRAMMABLE
LOGIC DEVICES

Discrete logic ICs / ASICs

Prior to the invention of programmable logic electronic systems designers had to use specialized integrated circuits, each of which contained just a few gates. Such chips were called discrete logic. In order to create even a moderately complex device one had to mount a few tens of chips on one board. This led to more complex board layout and reduced performance.

Why VLSI?

Integration improves the design

Lower parasitics = higher speed Lower power consumption Physically smaller / Handy

Integration reduces manufacturing cost - (almost) no manual assembly

VLSI Applications
VLSI is an implementation technology for electronic circuitry analog or digital

It is concerned with forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor
Microprocessors personal computers microcontrollers Memory - DRAM / SRAM Special Purpose Processors - ASICS (CD players, DSP applications) Has made highly sophisticated control systems mass-producable and therefore cheap

Moores Law
In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months i.e., grow exponentially with time Amazing visionary million transistor/chip barrier was crossed in the 1980s. 2300 transistors, 1 MHz clock (Intel 4004) - 1971 42 Million, 2 GHz clock (Intel P4) - 2001 140 Million transistor (HP PA-8500)

IC technology

Three types of IC technologies

Full-custom/VLSI Semi-custom ASIC (gate array and standard cell) PLD (Programmable Logic Device)

Full-custom/VLSI
All layers are optimized for an embedded systems particular digital implementation
Placing transistors Sizing transistors Routing wires

Benefits

Excellent performance, small size, low power High NRE cost (e.g., $300k), long time-to-market

Drawbacks

Semi-custom
Lower layers are fully or partially built Benefits

Designers are left with routing of wires and maybe placing some blocks Good performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k) Still require weeks to months to develop

Drawbacks

DEFINITION

Devices in which logic function is programmed by the user and in some cases can be reprogrammed many times, are called as Programmable logic devices.

ADVANTAGES
1. More logic in smaller area.

2. Rewiring and replacing not require for change in logic design.

3. Implementation time require is less.

4. In system programmability.

DISADVANTAGES

Programmable interconnects consumes most of the die area, more than an ASIC for the same functionality
Operating speed is less than ASIC, for the same functionality due to added interconnect delays in the path

Types of PLDs
1. Simple Programmable Logic Devices SPLDs

2. Complex Programmable Logic Devices CPLDs

3. Field Programmable Gate Array FPGA

ROM

Fixed AND Plane and Programmable OR plane

Input products are hard-wired and include all possible minterms. Output summation circuitry is programmable.

 ROMs are based on this decoder implementation of functions. A blank ROM just provides a decoder and several OR gates. The connections between the decoder and the OR gates are programmable, so different functions can be implemented. To program a ROM, you just make the desired connections between the decoder outputs and the OR gate inputs.

PLA: Programmable Logic Array The first kind of programmable logic device (named Programmable Logic Array) was introduced in early 70's. PLAs were one-time programmable chips containing AND and OR gates and able to implement a simple logic function represented as a disjunctive normal form.
Contains AND and OR array. AND array infers product terms for input variables. OR array makes ORing of product terms to form output functions.

PLA
Programmable AND Plane Programmable OR Plane

Programmable Node Un-programmed Connect Disconnect X Y O1 O2 O3 O4

X X Y Y

XY X Input product circuitry is programmable. XY Y Output summation circuitry is programmable. XY XY

PAL: Programmable Array Logic

AND array is programmable . OR array is fixed.

PAL
Programmable AND Plane Fix OR Plane

O1

O2

O3

O4

Input product circuitry is programmable. Output summation circuitry is hardwired.

PLA v.s. PAL

PLAs are more flexible than PALs since both AND & OR planes are programmable in PLAs. Because both AND & OR planes are programmable, PLAs are expensive to fabricate and have large propagation delay. By using fix OR gates, PALs are cheaper and faster than PLAs. Logic expanders increase the flexibilities of PALs, but result in significant propagation delay. PALs usually contain D flip-flops connected to the outputs of implement sequential circuits. PLAs and PALs are usually referred to as SPLD. OR gates to

PLD Summary

The OR gates

GAL16V8
Each output is programmable as combinational or registered Also has programmable output polarity

And Plane

XOR gates to make inverting or non-inverting buffer

PLDs

16V8 (20 Pins)

can have 16 inputs (max) and/or 8 outputs (marcrocells) has 32 inputs to each of the AND gates (product terms)
22V10 (24 pins) can have 22 inputs and/or 10 outputs (max) has 44 inputs to each of the AND gates

How about a 128V64 for larger applications?

It will be slower and will more wasted silicon space

Solution? Use CPLDs

CPLD
A CPLD comprises multiple PAL-like blocks on a single chip with programmable interconnect to connect the blocks. CPLD Architecture
I/O block I/O block I/O block PAL-like block PAL-like block

Programmable interconnect I/O block

PAL-like block

PAL-like block

Who makes the CPLDs?

Manufacturer
Altera
Altmel Cypress Lattice Philips Vantis Xilinx

CPLD Products

URL

MAX 5000, 7000 & 9000 www.altera.com ATF & ATV www.atmel.com FLASH370, Ultra37000 www.cypress.com ispLSI 1000 to 8000 www.latticesemi.com XPLA www.philips.com MACH 1 to 5 www.vantis.com XC9500 www.xilinx.com

Lets takes a look at this

Approximate Gate Counts

SPLDs Equivalent gates 0 ~ 200 CPLDs 200 ~ 12,000 FPGAs 1000 ~ 1,000,000

Modern CPLD

This is equivalent to13 22v10,s in single chip 128 FlipFlops or Logic Elements Electricaly Reprogrammable Can be programmed in number of different Languages

The Xilinx 9500-series CPLD

The internal PLDs are called Configurable Functional Blocks (FBs or CFBs) Each FB has 36 inputs and 18 Macrocells (effectively a 36V18) Each CLPD is packaged in a plastic-leaded chip carrier (PLCC) The number of I/O pins are much less than the total number of Macrocells in family of devices

Xinlinx CPLDs

Architecture of Xilinx 9500-family CPLD

36 Signal pins

18 outputs

Global Clock Global set/reset

Global 3 state control

18 Output enable signals

Architecture of Xilinx FB

Most CLPDs have fewer AND terms per macrocell XC9500 has 5 whereas 16V8 has 8 and 22V10 has 8-16 Buteach macrocell can use unused ANDs from its neighboring macrocells using the product-term-allocators

XC9500 Product term allocator and macrocell

ISP

Switch matrix for XC95108

Could be anything from a limited set of multiplexers to a full crossbar. Multiplexer -- small, fast, but difficult fitting Crossbar -- easy fitting but large and slow
1

Slide Switches

CPLD successful indication

9 Pin RS 232 Serial Port

Momentary Push Buttons

Reset Switch

8 LED outputs

10 Pin FRC Connector

On Board Regulators

AC Power 9V Adaptor

16 MHz Crystal Osc

Xilinx XC95xxxXL CPLD Adaptor

2 Seven Segment LED Display

26 Pin FRC Connector

JTAG Support Power Indication LED

CPLD Connection to 7 Segment Display

Pin Layout

FRC Connector Details

EEPROM Switching Technology

EEPROM Switching Technology

Anti-Fuse Structure

SRAM Switching Technology

Summary of programming Technologies

Design Flow

Schematic Entry
Schematic Design Entry is used when a visual design process is desired (similar to Electronics WorkBench / Multisim). Examples of visual design components:
Logic Gates Latches and Flip-Flops

Counters and Registers

Multiplexers and De-multiplexers Etc

Disadvantages to Graphical Design

Disadvantages of the graphical design:

Takes much longer to design more complex circuits that may require extensive design time (especially Booleanbased circuits such as decoders). More complex circuits means difficulty routing wires and troubleshooting. Limited logic operations to the device models available. Files created are proprietary, so will only work with that manufacturers software and devices.

Hardware Descriptive Language

Any Language That defines Digital Circuit.
A language that has explicit notion of Time. Language that is combination of sequential and concurrent statements A language that exhibits circuit connectivity between hardware blocks.

Quick History of HDLs

Verilog HDL

Structural Model

Gate level Model

Simple Behavioral Model

Why use VHDL?

Levels of Abstraction

Data Flow Level

In this style of modeling the flow of data through the entity is expressed using concurrent signal assignment statements.

Structural level Behavioral level

In this style of modeling the entity is described as a set of interecoconnected statements.

This style of modeling specifies the behaviour of an entity as a set of statements that are executed sequentially in the specified order.

Standard Libraries
Include library ieee; before entity declaration.

ieee.std_logic_1164 defines a standard for designers to use in describing interconnection data types used in VHDL modeling.
ieee.std_logic_arith provides a set of arithmetic, conversion, comparison functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector. Ieee.std_logic_unsigned provides a set of unsigned arithmetic, conversion, and comparison functions for std_logic_vector. See all available packages at
http://www.cs.umbc.edu/portal/help/VHDL/stdpkg.html

Entity Declaration
An entity declaration describes the interface of the component. Avoid using Alteras primitive names which can be found at

c:/altera/91/quartus/common/help/webhelp/master.htm#

PORT clause indicates input and output ports. An entity can be thought of as a symbol for a component.

Port Declaration
PORT declaration establishes the interface of the object to the outside world. Three parts of the PORT declaration
Name

Mode

Any identifier that is not a reserved word. In, Out, Inout, Buffer Any declared or predefined datatype.

Data type

Sample PORT declaration syntax:

Architecture Declaration
Architecture declarations describe the operation of the component.

Many architectures may exist for one entity, but only one may be active at a time.
An architecture is similar to a schematic of the component.

Synthesis
Check for syntax and logic errors

syntax: grammar of the language logic: how your Model responds to stimuli
entity declaration architecture body put each design unit in a separate file -- helps a lot.

Analyze each design unit separately

Analyzed design units are placed in a library

make sure your Model is truly OK

Simulation
Discrete event simulation

time advances in discrete steps when signal values changeevents occur

specified in wait statements resumes and schedules new values on output signals schedules transactions event on a signal if value changes

A processes is sensitive to events on input signals

Simulating a Design
Simulate a design:
Select Sources for: Behavioral Simulation Expand Xilinx ISE Simulator in the Processes for Source window Double-click Simulate Behavioral Model or Simulate Post-Place & Route Model
You can also simulate after Translate or after Map

What is Implementation?

More than just Place & Route Implementation includes many phases
o Translate: Merge multiple design files into a single netlist
o Map: Group logical symbols from the netlist (gates) into physical components (slices and IOBs) o Place & Route: Place components onto the chip, connect the components, and extract timing data into reports

Each phase generates files that allow you to use other Xilinx tools
o Floorplanner, FPGA Editor, XPower

Download
Once a design is implemented, you must create a file that the FPGA can understand
o This file is called a bitstream: a BIT file (.bit extension)

The BIT file can be downloaded directly into the FPGA, or the BIT file can be converted into a PROM file, which stores the programming information

In System Programmability

BIBLIOGRAPHY
www.xilinx.com www.wikipedia.com www.altera.com www.google.com

Books referred
Principles of VLSI Design, Kamran, Eshargian Pearson Education. Fundamentals of Digital Design, Brown Vranesic TM-Hill Publication.