FPGA and PLD survey

Sandeep Srivastava
 Introduction
• The process of designing digital hardware has changed
dramatically over the past few years prompted by the
development of FPDs
• Unlike previous generations of technology, in which
board-level designs included large numbers of SSI chips
containing basic gates, virtually every digital design
produced today consists mostly of high-density devices.
• This applies not only to custom devices like processors
and memory, but also for logic circuits such as state
machine controllers, counters, registers, and decoders.
 Introduction
• There are three main categories of Field
Programmable Devices:
• Simple PLDs (SPLDs)
• Complex PLDs (CPLDs)
• Field-Programmable Gate Arrays (FPGAs).
 Introduction
• The advantages of FPDs are –
– instant manufacturing turnaround
– low start-up costs, low financial risk
– since programming is done by the end user, ease
of design changes.
 Definition of Field Programmable Device

• FPD is a general term that refers to any type of

integrated circuit used for implementing digital
hardware, where the chip can be configured by the
end user to realize different designs.
• Programming of such a device often involves placing
the chip into a special programming unit, but some
chips can also be configured “in-system”.
• Another name for FPDs is programmable logic
devices (PLDs)
 PLA and PAL
• A Programmable Logic Array (PLA) is a
relatively small FPD that contains two levels of
logic, an AND-plane and an OR-plane, where
both levels are programmable. They can either
be embedded into full-custom chips or
provided as separate ICs.
• A Programmable Array Logic (PAL) is a
relatively small FPD that has a programmable
AND-plane followed by a fixed OR-plane
 SPLD and CPLD
• SPLD refers to any type of Simple PLD, usually
either a PLA or PAL
• CPLD refers to a more Complex PLD that
consists of an arrangement of multiple SPLD-
like blocks on a single chip.
 FPGA
• A Field-Programmable Gate Array is an FPD
featuring a general structure that allows very
high logic capacity.
• Whereas CPLDs feature logic resources with a
wide number of inputs (AND planes), FPGAs
offer more narrow logic resources.
• FPGAs also offer a higher ratio of flip-flops to
logic resources than do CPLDs.
 Evolution of Programmable Logic Devices

• The first type of user-programmable chip that could

implement logic circuits was the Programmable Read-
Only Memory (PROM), in which address lines can be
used as logic circuit inputs and data lines as outputs.
• Logic functions, however, rarely require more than a
few product terms, and a PROM contains a full
decoder for its address inputs.
• PROMS are thus an inefficient architecture for
realizing logic circuits, and so are rarely used in
practice for that purpose.
 PLA
• The first device developed later specifically for implementing logic circuits
was the Field-Programmable Logic Array (FPLA), or simply PLA for short. A
PLA consists of two levels of logic gates: a program mable “wired” AND-plane
followed by a programmable “wired” OR-plane.
• A PLA is structured so that any of its inputs (or their complements) can be
AND’ed together in the AND-plane; each AND-plane output can thus
correspond to any product term of the inputs.
• Similarly, each OR-plane output can be configured to produce the logical sum
of any of the AND-plane outputs.
• With this structure, PLAs are well-suited for implementing logic functions in
sum-of-products form.
• They are also quite versatile, since both the AND terms and OR terms can
have many inputs (this feature is often referred to as wide AND and OR
gates).
 PAL
• PALs feature only a single level of programmability, consisting of a
programmable “wired” AND-plane that feeds fixed OR-gates. To compensate
for lack of generality incurred because the OR-plane is fixed, several variants
of PALs are produced, with different numbers of inputs and outputs, and
various sizes of OR-gates.
• PALs usually contain flip-flops connected to the OR-gate outputs so that
sequential circuits can be realized. PAL devices are important because when
introduced they had a profound effect on digital hardware design, and also
they are the basis for some of the newer, more sophisticated architectures.
• Variants of the basic PAL architecture are featured in several other products
known by different acronyms.
• All small PLDs, including PLAs, PALs, and PAL-like devices are grouped into a
single category called Simple PLDs (SPLDs), whose most important
characteristics are low cost and very high pin-to-pin speed-performance.
Structure of a PAL
 CPLD
• As technology has advanced, it has become possible to produce
devices with higher capacity than SPLDs.
• The difficulty with increasing capacity of a strict SPLD architecture
is that the structure of the programmable logic-planes grow too
quickly in size as the number of inputs is increased.
• The only feasible way to provide large capacity devices based on
SPLD architectures is then to integrate multiple SPLDs onto a
single chip and provide interconnect to programmably connect
the SPLD blocks together.
• Many commercial FPD products exist on the market today with
this basic structure, and are collectively referred to as Complex
PLDs (CPLDs).
 MPGA’s
• The highest capacity general purpose logic chips available
today are the traditional gate arrays sometimes referred
to as Mask-Programmable Gate Arrays (MPGAs).
• MPGAs consist of an array of pre-fabricated transistors
that can be customized into the user’s logic circuit by
connecting the transistors with custom wires.
• Customization is performed during chip fabrication by
specifying the metal interconnect, and this means that in
order for a user to employ an MPGA a large setup cost is
involved and manufacturing time is long.
 Development of FPGA’s
• Although MPGAs are clearly not FPDs, they
motivated the design of the user-programmable
equivalent: Field-Programmable Gate Arrays (FPGAs).
• Like MPGAs, FPGAs comprise an array of
uncommitted circuit elements, called logic blocks,
and interconnect resources, but FPGA configuration
is performed through programming by the end user.
• The following slide shows a typical FPGA Architecture
Structure of an FPGA
 User Programmable Switch Technologies
• The first type of user-programmable switch developed was
the fuse used in PLAs. Fuses are still used in some smaller
devices
• Fuses were quickly replaced by newer technology.
• For higher density devices, where CMOS dominates the IC
industry, different approaches to implementing
programmable switches have been developed.
• For CPLDs the main switch technologies (in commercial
products) are floating gate transistors like those used in
EPROM and EEPROM, and for FPGAs they are SRAM and
antifuse.
 EPROM/EEPROM switch technology
• An EEPROM or EPROM transistor is used as a programmable switch for
CPLDs (and also for many SPLDs) by placing the transistor between two
wires in a way that facilitates implementation
• of wired-AND functions. This is illustrated in the following slide, which shows
EPROM transistors as they might be connected in an AND-plane of a CPLD.
• An input to the AND-plane can drive a product wire to logic level ‘0’ through
an EPROM transistor, if that input is part of the corresponding product term.
• For inputs that are not involved for a product term, the appropriate EPROM
transistors are programmed to be permanently turned off. A diagram for an
EEPROM based device would look similar.
• Current commercial FPGA products are based either on SRAM or antifuse
technologies.
EPROM Programmable Switches
SRAM-controlled Programmable Switches
SRAM Controlled Programmable Switches
• An example of usage of SRAM-controlled switches is
illustrated in above slide, showing two applications of
SRAM cells: for controlling the gate nodes of pass-transistor
switches and to control the select lines of multiplexers that
drive logic block inputs.
• The figures gives an example of the connection of one logic
block (represented by the AND-gate in the upper left
corner) to another through two pass-transistor switches,
and then a multiplexer, all controlled by SRAM cells.
• Whether an FPGA uses pass-transistors or multiplexers or
both depends on the particular product.
Actel Antifuse Structure
 Antifuse Switch Technology
• The other type of programmable switch used in FPGAs is the antifuse.
• Antifuses are originally open-circuits and take on low resistance only when
programmed.
• Antifuses are suitable for FPGAs because they can be built using modified
CMOS technology. As an example, Actel’s antifuse structure, known as PLICE ,
is depicted in following slide.
• The figure shows that an antifuse is positioned between two interconnect
wires and physically consists of three sandwiched layers: the top and bottom
layers are conductors, and the middle layer is an insulator.
• When unprogrammed, the insulator isolates the top and bottom layers, but
when programmed the insulator changes to become a low-resistance link.
PLICE uses Poly-Si and n+ diffusion as conductors and ONO as an insulator,
but other antifuses rely on metal for conductors, with amorphous silicon as
the middle layer
Summary of Programming Technologies
 CAD Tool Flow
• When designing circuits for implementation in FPDs, it is essential to employ
Computer-Aided Design (CAD) programs. Such software tools are discussed
briefly in this section to provide a feel for the design process involved.
• CAD tools are important not only for complex devices like CPLDs and FPGAs,
but also for SPLDs. A typical CAD system for SPLDs would include software
for the following tasks: initial design entry, logic optimization, device fitting,
simulation, and configuration.
• This design flow is illustrated in the following slide, which also indicates how
some stages feed back to others.
• Design entry may be done either by creating a schematic diagram with a
graphical CAD tool, by using a text based system to describe a design in a
simple hardware description language, or with a mixture of design entry
methods.
CAD Tool Flow
 CAD Tool Flow
• Since initial logic entry is not usually in an optimized
form, algorithms are employed to optimize the
circuits, after which additional algorithms analyse
the resulting logic equations and “fit” them into the
SPLD.
• Simulation is used to verify correct operation, and
the user would return to the design entry step to fix
errors. When a design simulates correctly it can be
loaded into a programming unit and used to
configure an SPLD.
 CAD Tool Flow
• The steps involved for implementing circuits in CPLDs are similar to
those for SPLDs, but the tools themselves are more sophisticated.
Because the devices are complex and can accommodate large designs,
it is more common to use a mixture of design entry methods for
different modules of a complete circuit.
• For instance, some modules might be designed with a small hardware
description language like ABEL, others drawn using a symbolic
schematic capture tool, and still others described via a full-featured
hardware description language such as VHDL.
• Also, for CPLDs the process of “fitting” a design may require steps
similar to those described below for FPGAs, depending on how
sophisticated the CPLD is. The necessary software for these tasks is
supplied either by the CPLD manufacturer or a third party.
 CAD Tool Flow
• The design process for FPGAs is similar to that for CPLDs, but
additional tools are needed to support the increased complexity
of the chips.
• The major difference is in the “device fitter” step that comes after
logic optimization and before simulation, where FPGAs require at
least three steps: a technology mapper to map from basic logic
gates into the FPGA’s logic blocks, placement to choose which
specific logic blocks to use in the FPGA, and a router to allocate
the wire segments in the FPGA to interconnect the logic blocks.
• With this added complexity, the CAD tools might require a fairly
long period of time (often more than an hour or even several
hours) to complete their tasks.