Introduction to Programmable Logic Devices

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VLSI Design Styles

Full Custom Mask Design Standard Cell Design Gate Arrays Programmable Logic
Design Investment Increasing (for a given application)

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1. Full custom design

Designers hand draws geometries which specify transistors and other devices for an integrated circuit (transistor/circuit level). Smallest die area (high transistors density) Very high development cost. Design time can be very long and so fabrication time (at least 6-8 weeks).
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 The first custom chip cost is very high but each one after is much cheaper so high volume products is designed (memory chips,micro-processors). Memory chips are the most popular designs done with full custom designs.

Mask layout of Pentium II micro-processor

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2. Standard Cell Design

Almost like the full custom design but commonly used logic cells are developed ,characterized and stored in standard cell library. Standardization is achieved at the logic or function level (transistor). Example on standard cell contents : SSI logic: nand, nor, xor, inverters, buffers, latches, registers. MSI logic: decoders, encoders, adders, comparators Memories: RAM, ROM
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To enable automated placement and routing of inter-cell connections , each cell layout has fixed height so cells can be abutted side-by-side.

Standard cell

Standard cell row

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3. Gate arrays
The design is mapped onto an array of transistors which is already created on a wafer GA implementation require two-step manufacturing : Array of uncommitted transistors on the GA chip (manufacture) Defining the metal interconnects between the transistors of array (user)
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Uncommitted cell
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Committed cell 4-input (NOR)

Introduction
 Comparison of Standard Logic Circuits and Programmable Logic Circuits  Evolution and Overview of PLC:
 PROM, PLA, PAL  CPLD FPGA

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Comparison of Standard Logic Circuits and Programmable Logic Circuits

Standard Logic Circuits Realize single function or set of functions, once defined and with no possibility of changing.

Programmable Logic Circuits

Contains great number of standard logic circuits Possibility of realizing many various functions Hardware can configure any time user need to only by programming.

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Standard Logic Circuits

Appropriate for many applications because of possibility of realization in mass production for relative low cost. Standard logic circuits are sometimes the best choice in high-performance devices.

Disadvantage:
Not permitting design updates (function changes) with no hardware replacement necessary.

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Field- Programmable Logic Devices

Component function is defined by users program. Logic Cells Fields are interconnected by programming. Advantages: - Flexible design that changes by reprogramming, ease of
design changes - Reduce prototype-product time - Large scale integration (over 100 000 gates) - Reliability increased, low financial risk - Smaller device, low start-up cost

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FPLDs Representatives
PLA - Programmable Logic Arrays PAL - Programmable Array Logic
Programmable logic device

PLD

CPLD - Complex Programmable Logic Devices FPGA - Field Programmable Gate Arrays

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Evolution of PLD: Why not PROM?

A special device (called a burner),
used to put the information, supplies an electrical current to specific cells in the ROM that effectively blows a fuse in them = burning the PROM. From that point on, chip is read-only. PROM was the first type of user-programmable chip; address lines = logic circuit inputs data lines = logic circuit outputs PROMs are inefficient architecture for realizing logic circuit:

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Evolution of PLD: PLA

PLA was the first device

developed for implementing

Consist of two levels of logic gates programmable wired AND-plane & OR-plane

f ( x1 ,..., xn ) ! ( x1 ,..., xn )

Drawbacks:
Expensive to manufacture Offered somewhat poor speed-performance
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Evolution of PLD: PAL

Overcame weaknesses of PLA

Single level of programmability consists of a programmable wired AND-plane & fixed ORgates
Simpler to program and cheaper implementation Limited numbers of terms in each output
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Note:

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PAL is a trademark of Advanced Micro Devices

Evolution of PLD: Register PLA

Contain flip flops connected to the OR gate outputs sequential circuits can be realized Importance:
Profound effect on digital hardware design Basis for more sophisticated architecturesTECHNOLOGY AND DESIGN 8/18/2011 VLSI

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Evolution of PLD: CPLD

Programmable possibility to produceInterconnect devices Technology advanced Array with higher capacity than SPLDs. - Capable of Structure grows too quickly in size connecting any LAB input or as the number of inputs is increased output to any other LAB Integrating multiple SPLDs onto a single chip -

the only feasible way to provide large capacity devices Logic Array based on SPLD Blocks
Programmably connect the SPLD blocks together
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- Complex SPLDlike structure

Logic capacity up to the equivalent of about 50 typical SPLD devices 10/13

... and finally...

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4. FPGA
What does 'Field Programmable' mean? A typical integrated circuit (IC) performs a particular function defined at the time of manufacture. A program written by someone other than the device manufacturer defines the FPGAs function. Depending on the particular device, the program is: - 'burned as part of a board assembly process - loaded from an external memory each time the device is powered up
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Evolution of PLD: FPGA

contains a set of basic functions (gates, FFs, densities - memory cells)

Difficult extending CPLDs architectures to higher

a different approach is needed

FPGAs comprise an array of uncommited circuit elements, called logic blocks, and interconnect resources FPGA configuration is performed through programming by the end user. Xilinx FPGA Configuration
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Four main categories of FPGA currently available

Logic block interconnections Symmetric array Row-based

Logic block

interconnections
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Hierarchical PLD

Currently there are four technologies in use

Static RAM cells
Connection are made using transistors,transmission gates or multiplexers controlled by SRAM cells (determine logic functions & interconnections).

Anti-Fuse
Resides in high-impedance state,or can be programmed into low-impedance (fused)

EPROM/EEPROM transistors
Same method as EPROM memories.

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The FPGA has 3 configurable elements

Configurable Logic Block (CLB) Input/Output Block (IOB) Interconnections

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CLB
Provides the functional elements for constructing users logic. May be physically implemented using LUT,multiplexers and gates.

IOB
Provides the interface between the package pins and internal signal lines.
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Programmable interconnections
Provide routing paths to connect the inputs and outputs of CLB and IOB. Composed of metal segments with programmable switching points to implement the desired routing

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