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EVALUATION TEST
Duration:- 2 Hours Total Marks:100
Section 1: DFT Basics 25 Marks
1) Why DFT? How it is different from function testing? Explain with an example? 2) List out the physical defects in CMOS? 3) What is a yield and DPPM? 4) Explain ASIC and FPGA flows? 5) What are ASIC components and how we are testing? 6) List out the DFT tools and vendors? 7) Where we are inserting DFT logics in ASIC flow? 8) How to test the chip and what is measured? 9) Write DFT architecture diagram including Clocks? 10) Draw the clock gating cell and explain with an example? 11) How to enter to Test Mode? 12) What are Test plans required for DFT Architecture? 13) What is the difference between Functional testing and DFT Testing? 14) How do you take care of unresolved reference modules during your runs?
Section 2 : Scan Insertion 75 Marks
1) Why Scan ? List out the modes in the scan insertion with waveforms? 2) What is the difference between flop and scan flop , explain with waveforms? 3) What are the inputs to the scan insertion and explain the scan insertion flow? 4) Explain scan DRC rules S1, S2, C6, C7, D5 & D6? 5) How we take care of shift resisters during scan? 6) What do you mean by scan chain balancing? Why it is required? List out the parameters? 7) How does scan chain works , explain with an example? 8) Why lock-up latches are required during scan and list out the scenarios?
Test clock-1 Test clock-2 With Skew Without Skew
Positive triggered Positive triggered Yes no Positive triggered Negative triggered yes yes Negative triggered Positive triggered yes no Negative triggered Negative triggered yes no
9) What is the difference between test mode and scan enable in both functional and DFT modes? 10) What is a clock skew, explain with an example? 11) What are advantages and disadvantage of Bottom up and Top-down approach? 12) What is the difference between lockup latch and terminal lockup latch? 13) What is CTL ? Why it is required during Scan insertion? 14) What is controllability and observability? 15) How do you take care negative edge flops in the design during scan?
