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Scan Insertion Lab Observation: - Covert Normal Flops To Scannable Flops

The document summarizes the process of inserting scan chains into a synthesized netlist using the dc_shell tool. Key steps include invoking dc_shell, reading in the verilog netlist and library, setting the current design and linking to the library, specifying a multiplexed scan configuration, compiling the scan which converts normal flops to scannable flops, and writing the scan-inserted netlist to a new verilog file.

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Ilaiyaveni Iyandurai
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93 views2 pages

Scan Insertion Lab Observation: - Covert Normal Flops To Scannable Flops

The document summarizes the process of inserting scan chains into a synthesized netlist using the dc_shell tool. Key steps include invoking dc_shell, reading in the verilog netlist and library, setting the current design and linking to the library, specifying a multiplexed scan configuration, compiling the scan which converts normal flops to scannable flops, and writing the scan-inserted netlist to a new verilog file.

Uploaded by

Ilaiyaveni Iyandurai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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SCAN INSERTION LAB OBSERVATION

Lab 1: -
Covert Normal flops to Scannable flops:

Invoke The Tool : (dc_shell)

 dc_shell
(OR)
 tcsh
 source /tools/synopsys/source.sh
 dc_shell

Inputs: -

• Synthesis Netlist:-

Gate level netlist [div.v] from synthesis team

• Library Model:-

saed90nm_typ_ht.db

•Tool commands (Command Description )

read_verilog div.v (Read Netlist & Library)

current_design div_1 (To set the current design)

link (to link design with technology library)

set_scan_configuration -style multiplexed flip_flop (scan configuration)

compile_scan (convert flops to scannable flops)

write - output div_compile_scan.v -heir -format verilog (write SI netlist to


separate file)

Outputs: -
• Scan inserted Netlist:-

Gate level netlist [scanned]

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