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Scan insertion and ATPG are used to check the functionality of the design for correctness. The DFT library defines a function of the lowest level netlist module. The LibComp tool automates the conversion from Verilog simulation to a DFT ATPG library. The set_current_design command elaborates the design and identifies any missing components. Black boxes are used to maintain controllability and observability for ATPG during scan insertion without losing design information. The test procedure file defines the stimulus for shifting scan data through the defined scan chains.

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45 views4 pages

4new Text Document

Scan insertion and ATPG are used to check the functionality of the design for correctness. The DFT library defines a function of the lowest level netlist module. The LibComp tool automates the conversion from Verilog simulation to a DFT ATPG library. The set_current_design command elaborates the design and identifies any missing components. Black boxes are used to maintain controllability and observability for ATPG during scan insertion without losing design information. The test procedure file defines the stimulus for shifting scan data through the defined scan chains.

Uploaded by

balukrish2018
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Scan insertion and ATPG are used to check the functionality of the design for

correctness.

True
??False
Correct
The DFT library defines a function of the …… level netlist module.

highest
?? lowest
Correct
The LibComp tool is a Verilog simulation to DFT ATPG library conversion engine that
automates much or all of the conversion effort.

??True
False
Correct
The ……… command elaborates the design and tells us if anything is missing.

set_system_mode
??set_current_design
create_flat_model
Incorrect
If you want to create a black box for module, The add_black_boxes command is used
with …… switch.

–instances
–auto
?? –modules
Incorrect
The advantage of using black boxes is that we don’t lose controllability and
observability for ATPG.

True
??False
Incorrect

The test procedure file defines the stimulus for shifting scan data through the
defined scan chains.

?? True
False
Correct
The ……… procedure defines the procedure to bring non scan state elements into a
desired state.

load/unload
??test_setup
shift procedure
Correct
The events for the capture cycle are ………….(Select all that apply)

?? forcing the scan enable off


?? forcing primary inputs
?? measuring primary outputs
?? pulsing the capture clock
Incorrect
When performing design rule checking, we trace the scan chains from the ………….

scan input to the scan output


??scan output to the scan input
Correct
The …………… command which identifies each control signal of every sequential element.

analyze_scan_chains
?? analyze_control_signals
add_control_points
Correct
The analyze_control_signals command with the ………… argument performs an implicit
add_clocks for you.

?? –auto_fix
–report_only
–verbose
Correct
The Tessent utility stil2mgc translates a Synopsys STIL file into a Tessent Scan
dofile and test procedure file.

??True
False
Correct
The ……… contains information about setting up scan circuitry.

test procedure file


?? dofile
Correct
The ……… specify the scan circuitry operation.

??test procedure file


dofile
Correct

After the scan insertion process, the outputs are …… . (Select all that apply)

?? scan inserted netlist


?? dofile
??test procedure file
Incorrect
Test coverage is the total percentage of testable faults the pattern set actually
detects.

??True
False
Correct
To initiate the DRC process, the ……… command is used.

?? check_design_rules
check_synthesis
check_testbench_simulations
Correct
The ……… rules identify inconsistencies in scan data and other definitions.

scannability
?? general
RAM
Incorrect
The Data rules ensure that the order of events has not changed since leaving the
setup mode.

True
?? False
Correct
The command ……… specifies how the tool handles design rule violations.

set_design_level
set_system_mode
?? set_drc_handling
Correct
The command ………… specifies the fault model type for ATPG.

??set_fault_type
add_faults
set_fault_mode
Correct
The create_patterns command …………….(Select all that apply)

?? performs automatic test pattern generation


??identifies and generates the most appropriate pattern types based on the design
saves the current test pattern set to a file in a specified format
Correct
The test pattern …………… format includes the statistics report, scan test patterns,
and the scan cell information.

?? ASCII
binary
PATDB
Incorrect
The test pattern ……… format is the recommended format for archival of patterns.

ASCII
binary
??PATDB
Incorrect

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